firmware/system.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Alan Korr
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 #include <stdio.h>
  20 #include "config.h"
  21
  22 #include "lcd.h"
  23 #include "font.h"
  24 #include "led.h"
  25 #include "system.h"
  26
  27 #define default_interrupt(name,number) \
  28   extern __attribute__((weak,alias("UIE" #number))) void name (void); void UIE##number (void)
  29 #define reserve_interrupt(number) \
  30   void UIE##number (void)
  31
  32 extern void reset_pc (void);
  33 extern void reset_sp (void);
  34
  35 static const char* irqname[] = {
  36     "", "", "", "", "IllInstr", "", "IllSltIn","","",
  37     "CPUAdrEr", "DMAAdrEr", "NMI", "UserBrk",
  38     "","","","","","","","","","","","","","","","","","","",
  39     "Trap32","Trap33","Trap34","Trap35","Trap36","Trap37","Trap38","Trap39",
  40     "Trap40","Trap41","Trap42","Trap43","Trap44","Trap45","Trap46","Trap47",
  41     "Trap48","Trap49","Trap50","Trap51","Trap52","Trap53","Trap54","Trap55",
  42     "Trap56","Trap57","Trap58","Trap59","Trap60","Trap61","Trap62","Trap63",
  43     "Irq0","Irq1","Irq2","Irq3","Irq4","Irq5","Irq6","Irq7",
  44     "Dma0","","Dma1","","Dma2","","Dma3","",
  45     "IMIA0","IMIB0","OVI0","", "IMIA1","IMIB1","OVI1","",
  46     "IMIA2","IMIB2","OVI2","", "IMIA3","IMIB3","OVI3","",
  47     "IMIA4","IMIB4","OVI4","",
  48     "Ser0Err","Ser0Rx","Ser0Tx","Ser0TE",
  49     "Ser1Err","Ser1Rx","Ser1Tx","Ser1TE",
  50     "ParityEr","A/D conv","","","Watchdog","DRAMRefr"
  51 };
  52
  53 reserve_interrupt (          0);
  54 reserve_interrupt (          1);
  55 reserve_interrupt (          2);
  56 reserve_interrupt (          3);
  57 default_interrupt (GII,      4);
  58 reserve_interrupt (          5);
  59 default_interrupt (ISI,      6);
  60 reserve_interrupt (          7);
  61 reserve_interrupt (          8);
  62 default_interrupt (CPUAE,    9);
  63 default_interrupt (DMAAE,   10);
  64 default_interrupt (NMI,     11);
  65 default_interrupt (UB,      12);
  66 reserve_interrupt (         13);
  67 reserve_interrupt (         14);
  68 reserve_interrupt (         15);
  69 reserve_interrupt (         16); // TCB #0
  70 reserve_interrupt (         17); // TCB #1
  71 reserve_interrupt (         18); // TCB #2
  72 reserve_interrupt (         19); // TCB #3
  73 reserve_interrupt (         20); // TCB #4
  74 reserve_interrupt (         21); // TCB #5
  75 reserve_interrupt (         22); // TCB #6
  76 reserve_interrupt (         23); // TCB #7
  77 reserve_interrupt (         24); // TCB #8
  78 reserve_interrupt (         25); // TCB #9
  79 reserve_interrupt (         26); // TCB #10
  80 reserve_interrupt (         27); // TCB #11
  81 reserve_interrupt (         28); // TCB #12
  82 reserve_interrupt (         29); // TCB #13
  83 reserve_interrupt (         30); // TCB #14
  84 reserve_interrupt (         31); // TCB #15
  85 default_interrupt (TRAPA32, 32);
  86 default_interrupt (TRAPA33, 33);
  87 default_interrupt (TRAPA34, 34);
  88 default_interrupt (TRAPA35, 35);
  89 default_interrupt (TRAPA36, 36);
  90 default_interrupt (TRAPA37, 37);
  91 default_interrupt (TRAPA38, 38);
  92 default_interrupt (TRAPA39, 39);
  93 default_interrupt (TRAPA40, 40);
  94 default_interrupt (TRAPA41, 41);
  95 default_interrupt (TRAPA42, 42);
  96 default_interrupt (TRAPA43, 43);
  97 default_interrupt (TRAPA44, 44);
  98 default_interrupt (TRAPA45, 45);
  99 default_interrupt (TRAPA46, 46);
 100 default_interrupt (TRAPA47, 47);
 101 default_interrupt (TRAPA48, 48);
 102 default_interrupt (TRAPA49, 49);
 103 default_interrupt (TRAPA50, 50);
 104 default_interrupt (TRAPA51, 51);
 105 default_interrupt (TRAPA52, 52);
 106 default_interrupt (TRAPA53, 53);
 107 default_interrupt (TRAPA54, 54);
 108 default_interrupt (TRAPA55, 55);
 109 default_interrupt (TRAPA56, 56);
 110 default_interrupt (TRAPA57, 57);
 111 default_interrupt (TRAPA58, 58);
 112 default_interrupt (TRAPA59, 59);
 113 default_interrupt (TRAPA60, 60);
 114 default_interrupt (TRAPA61, 61);
 115 default_interrupt (TRAPA62, 62);
 116 default_interrupt (TRAPA63, 63);
 117 default_interrupt (IRQ0,    64);
 118 default_interrupt (IRQ1,    65);
 119 default_interrupt (IRQ2,    66);
 120 default_interrupt (IRQ3,    67);
 121 default_interrupt (IRQ4,    68);
 122 default_interrupt (IRQ5,    69);
 123 default_interrupt (IRQ6,    70);
 124 default_interrupt (IRQ7,    71);
 125 default_interrupt (DEI0,    72);
 126 reserve_interrupt (         73);
 127 default_interrupt (DEI1,    74);
 128 reserve_interrupt (         75);
 129 default_interrupt (DEI2,    76);
 130 reserve_interrupt (         77);
 131 default_interrupt (DEI3,    78);
 132 reserve_interrupt (         79);
 133 default_interrupt (IMIA0,   80);
 134 default_interrupt (IMIB0,   81);
 135 default_interrupt (OVI0,    82);
 136 reserve_interrupt (         83);
 137 default_interrupt (IMIA1,   84);
 138 default_interrupt (IMIB1,   85);
 139 default_interrupt (OVI1,    86);
 140 reserve_interrupt (         87);
 141 default_interrupt (IMIA2,   88);
 142 default_interrupt (IMIB2,   89);
 143 default_interrupt (OVI2,    90);
 144 reserve_interrupt (         91);
 145 default_interrupt (IMIA3,   92);
 146 default_interrupt (IMIB3,   93);
 147 default_interrupt (OVI3,    94);
 148 reserve_interrupt (         95);
 149 default_interrupt (IMIA4,   96);
 150 default_interrupt (IMIB4,   97);
 151 default_interrupt (OVI4,    98);
 152 reserve_interrupt (         99);
 153 default_interrupt (REI0,   100);
 154 default_interrupt (RXI0,   101);
 155 default_interrupt (TXI0,   102);
 156 default_interrupt (TEI0,   103);
 157 default_interrupt (REI1,   104);
 158 default_interrupt (RXI1,   105);
 159 default_interrupt (TXI1,   106);
 160 default_interrupt (TEI1,   107);
 161 reserve_interrupt (        108);
 162 default_interrupt (ADITI,  109);
 163
 164 /* reset vectors are handled in crt0.S */
 165 void (*vbr[]) (void) __attribute__ ((section (".vectors"))) =
 166 {
 167     /*** 4 General Illegal Instruction ***/
 168
 169     GII,
 170
 171     /*** 5 Reserved ***/
 172
 173     UIE5,
 174
 175     /*** 6 Illegal Slot Instruction ***/
 176
 177     ISI,
 178
 179     /*** 7-8 Reserved ***/
 180
 181     UIE7,UIE8,
 182
 183     /*** 9 CPU Address Error ***/
 184
 185     CPUAE,
 186
 187     /*** 10 DMA Address Error ***/
 188
 189     DMAAE,
 190
 191     /*** 11 NMI ***/
 192
 193     NMI,
 194
 195     /*** 12 User Break ***/
 196
 197     UB,
 198
 199     /*** 13-31 Reserved ***/
 200
 201     UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,UIE29,UIE30,UIE31,
 202
 203     /*** 32-63 TRAPA #20...#3F ***/
 204
 205     TRAPA32,TRAPA33,TRAPA34,TRAPA35,TRAPA36,TRAPA37,TRAPA38,TRAPA39,TRAPA40,TRAPA41,TRAPA42,TRAPA43,TRAPA44,TRAPA45,TRAPA46,TRAPA47,TRAPA48,TRAPA49,TRAPA50,TRAPA51,TRAPA52,TRAPA53,TRAPA54,TRAPA55,TRAPA56,TRAPA57,TRAPA58,TRAPA59,TRAPA60,TRAPA61,TRAPA62,TRAPA63,
 206
 207     /*** 64-71 IRQ0-7 ***/
 208
 209     IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,
 210
 211     /*** 72 DMAC0 ***/
 212
 213     DEI0,
 214
 215     /*** 73 Reserved ***/
 216
 217     UIE73,
 218
 219     /*** 74 DMAC1 ***/
 220
 221     DEI1,
 222
 223     /*** 75 Reserved ***/
 224
 225     UIE75,
 226
 227     /*** 76 DMAC2 ***/
 228
 229     DEI2,
 230
 231     /*** 77 Reserved ***/
 232
 233     UIE77,
 234
 235     /*** 78 DMAC3 ***/
 236
 237     DEI3,
 238
 239     /*** 79 Reserved ***/
 240
 241     UIE79,
 242
 243     /*** 80-82 ITU0 ***/
 244
 245     IMIA0,IMIB0,OVI0,
 246
 247     /*** 83 Reserved ***/
 248
 249     UIE83,
 250
 251     /*** 84-86 ITU1 ***/
 252
 253     IMIA1,IMIB1,OVI1,
 254
 255     /*** 87 Reserved ***/
 256
 257     UIE87,
 258
 259     /*** 88-90 ITU2 ***/
 260
 261     IMIA2,IMIB2,OVI2,
 262
 263     /*** 91 Reserved ***/
 264
 265     UIE91,
 266
 267     /*** 92-94 ITU3 ***/
 268
 269     IMIA3,IMIB3,OVI3,
 270
 271     /*** 95 Reserved ***/
 272
 273     UIE95,
 274
 275     /*** 96-98 ITU4 ***/
 276
 277     IMIA4,IMIB4,OVI4,
 278
 279     /*** 99 Reserved ***/
 280
 281     UIE99,
 282
 283     /*** 100-103 SCI0 ***/
 284
 285     REI0,RXI0,TXI0,TEI0,
 286
 287     /*** 104-107 SCI1 ***/
 288
 289     REI1,RXI1,TXI1,TEI1,
 290
 291     /*** 108 Parity Control Unit ***/
 292
 293     UIE108,
 294
 295     /*** 109 AD Converter ***/
 296
 297     ADITI
 298
 299 };
 300
 301
 302 void system_reboot (void)
 303 {
 304     cli ();
 305
 306     asm volatile ("ldc\t%0,vbr" : : "r"(0));
 307
 308     IPRA = 0;
 309     IPRB = 0;
 310     IPRC = 0;
 311     IPRD = 0;
 312     IPRE = 0;
 313     ICR = 0;
 314
 315     asm volatile ("jmp @%0; mov.l @%1,r15" : :
 316                   "r"(*(int*)0),"r"(4));
 317 }
 318
 319 void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
 320 {
 321     bool state = true;
 322     unsigned int n;
 323     char str[32];
 324
 325     asm volatile ("sts\tpr,%0" : "=r"(n));
 326
 327     /* clear screen */
 328     lcd_clear_display ();
 329 #ifdef HAVE_LCD_BITMAP
 330     lcd_setfont(FONT_SYSFIXED);
 331 #endif
 332     /* output exception */
 333     n = (n - (unsigned)UIE0 - 4)>>2; // get exception or interrupt number
 334     snprintf(str,sizeof(str),"I%02x:%s",n,irqname[n]);
 335     lcd_puts(0,0,str);
 336     snprintf(str,sizeof(str),"at %08x",pc);
 337     lcd_puts(0,1,str);
 338
 339 #ifdef HAVE_LCD_BITMAP
 340     lcd_update ();
 341 #endif
 342
 343     while (1)
 344     {
 345         volatile int i;
 346         led (state);
 347         state = state?false:true;
 348
 349         for (i = 0; i < 240000; ++i);
 350     }
 351 }
 352
 353 asm (
 354     "_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 355     "_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 356     "_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 357     "_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 358     "_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 359     "_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 360     "_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 361     "_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 362     "_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 363     "_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 364     "_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 365     "_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 366     "_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 367     "_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 368     "_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 369     "_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 370     "_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 371     "_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 372     "_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 373     "_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 374     "_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 375     "_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 376     "_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 377     "_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 378     "_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 379     "_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 380     "_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 381     "_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 382     "_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 383     "_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 384     "_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 385     "_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 386     "_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 387     "_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 388     "_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 389     "_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 390     "_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 391     "_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 392     "_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 393     "_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 394     "_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 395     "_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 396     "_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 397     "_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 398     "_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 399     "_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 400     "_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 401     "_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 402     "_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 403     "_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 404     "_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 405     "_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 406     "_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 407     "_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 408     "_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 409     "_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 410     "_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 411     "_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 412     "_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 413     "_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 414     "_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 415     "_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 416     "_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 417     "_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 418     "_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 419     "_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 420     "_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 421     "_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 422     "_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 423     "_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 424     "_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 425     "_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 426     "_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 427     "_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 428     "_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 429     "_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 430     "_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 431     "_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 432     "_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 433     "_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 434     "_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 435     "_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 436     "_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 437     "_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 438     "_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 439     "_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 440     "_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 441     "_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 442     "_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 443     "_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 444     "_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 445     "_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 446     "_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 447     "_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 448     "_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 449     "_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 450     "_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 451     "_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 452     "_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 453     "_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 454     "_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 455     "_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 456     "_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 457     "_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 458     "_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 459     "_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 460     "_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 461     "_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 462     "_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 463     "_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4");
 464
 465 void system_init(void)
 466 {
 467     /* Disable all interrupts */
 468     IPRA = 0;
 469     IPRB = 0;
 470     IPRC = 0;
 471     IPRD = 0;
 472     IPRE = 0;
 473
 474     /* NMI level low, falling edge on all interrupts */
 475     ICR = 0;
 476
 477     /* Enable burst mode on DRAM */
 478     DCR |= 0x1000;
 479
 480     /* Activate Warp mode (simultaneous internal and external mem access) */
 481     BCR |= 0x2000;
 482 }