firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "led.h"
  27 #include "sdmmc.h"
  28 #include "system.h"
  29 #include "kernel.h"
  30 #include "cpu.h"
  31 #include <stdio.h>
  32 #include <stdlib.h>
  33 #include <string.h>
  34 #include "as3525v2.h"
  35 #include "pl081.h"  /* DMA controller */
  36 #include "dma-target.h" /* DMA request lines */
  37 #include "clock-target.h"
  38 #include "panic.h"
  39 #include "stdbool.h"
  40 #include "ata_idle_notify.h"
  41 #include "sd.h"
  42 #include "usb.h"
  43
  44 #ifdef HAVE_HOTSWAP
  45 #include "disk.h"
  46 #endif
  47
  48 #ifdef SANSA_FUZEV2
  49 #include "backlight-target.h"
  50 #endif
  51
  52 #include "lcd.h"
  53 #include <stdarg.h>
  54 #include "sysfont.h"
  55
  56 #define     INTERNAL_AS3525  0   /* embedded SD card */
  57 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  58
  59 /* Clipv2 Clip+ and Fuzev2 OF all occupy the same size */
  60 #define AMS_OF_SIZE 0xf000
  61
  62 /* command flags */
  63 #define MCI_NO_RESP     (0<<0)
  64 #define MCI_RESP        (1<<0)
  65 #define MCI_LONG_RESP   (1<<1)
  66
  67 /* controller registers */
  68 #define SD_BASE 0xC6070000
  69
  70 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  71
  72 #define MCI_CTRL        SD_REG(0x00)
  73
  74 /* control bits */
  75 #define CTRL_RESET      (1<<0)
  76 #define FIFO_RESET      (1<<1)
  77 #define DMA_RESET       (1<<2)
  78 #define INT_ENABLE      (1<<4)
  79 #define DMA_ENABLE      (1<<5)
  80 #define READ_WAIT       (1<<6)
  81 #define SEND_IRQ_RESP   (1<<7)
  82 #define ABRT_READ_DATA  (1<<8)
  83 #define SEND_CCSD       (1<<9)
  84 #define SEND_AS_CCSD    (1<<10)
  85 #define EN_OD_PULLUP    (1<<24)
  86
  87
  88 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  89
  90 #define PWR_CRD_0       (1<<0)
  91 #define PWR_CRD_1       (1<<1)
  92 #define PWR_CRD_2       (1<<2)
  93 #define PWR_CRD_3       (1<<3)
  94
  95 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  96 /* CLK_DIV_0 :    bits 7:0
  97  * CLK_DIV_1 :    bits 15:8
  98  * CLK_DIV_2 :    bits 23:16
  99  * CLK_DIV_3 :    bits 31:24
 100  */
 101
 102 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
 103 /* CLK_SRC_CRD0:  bits 1:0
 104  * CLK_SRC_CRD1:  bits 3:2
 105  * CLK_SRC_CRD2:  bits 5:4
 106  * CLK_SRC_CRD3:  bits 7:6
 107  */
 108
 109 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
 110
 111 #define CCLK_ENA_CRD0   (1<<0)
 112 #define CCLK_ENA_CRD1   (1<<1)
 113 #define CCLK_ENA_CRD2   (1<<2)
 114 #define CCLK_ENA_CRD3   (1<<3)
 115 #define CCLK_LP_CRD0    (1<<16)         /* LP --> Low Power Mode? */
 116 #define CCLK_LP_CRD1    (1<<17)
 117 #define CCLK_LP_CRD2    (1<<18)
 118 #define CCLK_LP_CRD3    (1<<19)
 119
 120 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
 121 /* response timeout bits 0:7
 122  * data timeout bits     8:31
 123  */
 124
 125 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
 126                                         /* 1 bit per card, set = wide bus */
 127 #define WIDTH4_CRD0     (1<<0)
 128 #define WIDTH4_CRD1     (1<<1)
 129 #define WIDTH4_CRD2     (1<<2)
 130 #define WIDTH4_CRD3     (1<<3)
 131
 132 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size  bits 0:15*/
 133 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count  bits 0:31*/
 134 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
 135
 136
 137
 138 #define MCI_ARGUMENT    SD_REG(0x28)
 139 #define MCI_COMMAND     SD_REG(0x2C)
 140
 141 /* command bits (bits 5:0 are the command index) */
 142 #define CMD_RESP_EXP_BIT        (1<<6)
 143 #define CMD_RESP_LENGTH_BIT     (1<<7)
 144 #define CMD_CHECK_CRC_BIT       (1<<8)
 145 #define CMD_DATA_EXP_BIT        (1<<9)
 146 #define CMD_RW_BIT              (1<<10)
 147 #define CMD_TRANSMODE_BIT       (1<<11)
 148 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
 149 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
 150 #define CMD_ABRT_CMD_BIT        (1<<14)
 151 #define CMD_SEND_INIT_BIT       (1<<15)
 152 #define CMD_CARD_NO(x)          ((x)<<16)         /* 5 bits wide  */
 153 #define CMD_SEND_CLK_ONLY       (1<<21)
 154 #define CMD_READ_CEATA          (1<<22)
 155 #define CMD_CCS_EXPECTED        (1<<23)
 156 #define CMD_DONE_BIT            (1<<31)
 157
 158 #define TRANSFER_CMD  (cmd == SD_READ_MULTIPLE_BLOCK ||   \
 159                        cmd == SD_WRITE_MULTIPLE_BLOCK)
 160
 161 #define MCI_RESP0       SD_REG(0x30)
 162 #define MCI_RESP1       SD_REG(0x34)
 163 #define MCI_RESP2       SD_REG(0x38)
 164 #define MCI_RESP3       SD_REG(0x3C)
 165
 166 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 167 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 168                                          * status clear */
 169
 170 /* interrupt bits */                /* C D E   (Cmd) (Data) (End) */
 171 #define MCI_INT_CRDDET  (1<<0)      /*          card detect */
 172 #define MCI_INT_RE      (1<<1)      /* x         response error */
 173 #define MCI_INT_CD      (1<<2)      /*     x     command done */
 174 #define MCI_INT_DTO     (1<<3)      /*     x     data transfer over */
 175 #define MCI_INT_TXDR    (1<<4)      /*          tx fifo data request */
 176 #define MCI_INT_RXDR    (1<<5)      /*          rx fifo data request */
 177 #define MCI_INT_RCRC    (1<<6)      /* x         response crc error */
 178 #define MCI_INT_DCRC    (1<<7)      /*   x       data crc error */
 179 #define MCI_INT_RTO     (1<<8)      /* x         response timeout */
 180 #define MCI_INT_DRTO    (1<<9)      /*   x       data read timeout */
 181 #define MCI_INT_HTO     (1<<10)     /*   x       data starv timeout */
 182 #define MCI_INT_FRUN    (1<<11)     /*   x       fifo over/underrun */
 183 #define MCI_INT_HLE     (1<<12)     /* x x        hw locked while error */
 184 #define MCI_INT_SBE     (1<<13)     /*   x       start bit error */
 185 #define MCI_INT_ACD     (1<<14)     /*          auto command done */
 186 #define MCI_INT_EBE     (1<<15)     /*   x       end bit error */
 187 #define MCI_INT_SDIO    (0xf<<16)
 188
 189 /*
 190  *  STATUS register
 191  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 192  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 193  *  & 8         = MCI_INT_DTO
 194  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 195  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 196  */
 197
 198 #define MCI_CMD_ERROR    \
 199          (MCI_INT_RE   | \
 200           MCI_INT_RCRC | \
 201           MCI_INT_RTO  | \
 202           MCI_INT_HLE)
 203
 204 #define MCI_DATA_ERROR    \
 205         ( MCI_INT_DCRC  | \
 206           MCI_INT_DRTO  | \
 207           MCI_INT_HTO   | \
 208           MCI_INT_FRUN  | \
 209           MCI_INT_HLE   | \
 210           MCI_INT_SBE   | \
 211           MCI_INT_EBE)
 212
 213 #define MCI_STATUS      SD_REG(0x48)
 214
 215 #define FIFO_RX_WM              (1<<0)
 216 #define FIFO_TX_WM              (1<<1)
 217 #define FIFO_EMPTY              (1<<2)
 218 #define FIFO_FULL               (1<<3)
 219 #define CMD_FSM_STATE_B0        (1<<4)
 220 #define CMD_FSM_STATE_B1        (1<<5)
 221 #define CMD_FSM_STATE_B2        (1<<6)
 222 #define CMD_FSM_STATE_B3        (1<<7)
 223 #define DATA_3_STAT             (1<<8)
 224 #define DATA_BUSY               (1<<9)
 225 #define DATA_STAT_MC_BUSY       (1<<10)
 226 #define RESP_IDX_B0             (1<<11)
 227 #define RESP_IDX_B1             (1<<12)
 228 #define RESP_IDX_B2             (1<<13)
 229 #define RESP_IDX_B3             (1<<14)
 230 #define RESP_IDX_B4             (1<<15)
 231 #define RESP_IDX_B5             (1<<16)
 232 #define FIFO_CNT_B00            (1<<17)
 233 #define FIFO_CNT_B01            (1<<18)
 234 #define FIFO_CNT_B02            (1<<19)
 235 #define FIFO_CNT_B03            (1<<20)
 236 #define FIFO_CNT_B04            (1<<21)
 237 #define FIFO_CNT_B05            (1<<22)
 238 #define FIFO_CNT_B06            (1<<23)
 239 #define FIFO_CNT_B07            (1<<24)
 240 #define FIFO_CNT_B08            (1<<25)
 241 #define FIFO_CNT_B09            (1<<26)
 242 #define FIFO_CNT_B10            (1<<27)
 243 #define FIFO_CNT_B11            (1<<28)
 244 #define FIFO_CNT_B12            (1<<29)
 245 #define DMA_ACK                 (1<<30)
 246 #define START_CMD               (1<<31)
 247
 248 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 249 /* TX watermark :    bits 11:0
 250  * RX watermark :    bits 27:16
 251  * DMA MTRANS SIZE : bits 30:28
 252  * bits 31, 15:12 : unused
 253  */
 254 #define MCI_FIFOTH_MASK 0x8000f000
 255
 256 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 257
 258 #define CDETECT_CRD_0   (1<<0)
 259 #define CDETECT_CRD_1   (1<<1)
 260 #define CDETECT_CRD_2   (1<<2)
 261 #define CDETECT_CRD_3   (1<<3)
 262
 263 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 264 #define MCI_GPIO        SD_REG(0x58)
 265 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count (card)*/
 266 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes (FIFO)*/
 267 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce  bits 23:0*/
 268 #define MCI_USRID       SD_REG(0x68)    /* user id */
 269 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 270
 271 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 272 /* bit  0       : card type
 273  * bits 5:1     : maximum card index
 274  * bit  6       : BUS TYPE
 275  * bits 9:7     : DATA WIDTH
 276  * bits 15:10   : ADDR WIDTH
 277  * bits 17:16   : DMA IF
 278  * bits 20:18   : DMA WIDTH
 279  * bit  21      : FIFO RAM INSIDE
 280  * bit  22      : IMPL HOLD REG
 281  * bit  23      : SET CLK FALSE
 282  * bits 25:24   : MAX CLK DIV IDX
 283  * bit  26      : AREA OPTIM
 284  */
 285
 286 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 287 /* bit  0       : SWR
 288  * bit  1       : FB
 289  * bits 6:2     : DSL
 290  * bit  7       : DE
 291  * bit  10:8    : PBL
 292  */
 293
 294 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 295 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 296 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 297 /* bit  0       : TI
 298  * bit  1       : RI
 299  * bit  2       : FBE
 300  * bit  3       : unused
 301  * bit  4       : DU
 302  * bit  5       : CES
 303  * bits 7:6     : unused
 304  * bits 8       : NIS
 305  * bit  9       : AIS
 306  * bits 12:10   : EB
 307  * bits 16:13   : FSM
 308  */
 309
 310 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 311 /* bit  0       : TI
 312  * bit  1       : RI
 313  * bit  2       : FBE
 314  * bit  3       : unused
 315  * bit  4       : DU
 316  * bit  5       : CES
 317  * bits 7:6     : unused
 318  * bits 8       : NI
 319  * bit  9       : AI
 320  */
 321 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 322 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 323
 324 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 325
 326 #define UNALIGNED_NUM_SECTORS 10
 327 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 328 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
 329
 330 static tCardInfo card_info[NUM_DRIVES];
 331
 332 /* for compatibility */
 333 static long last_disk_activity = -1;
 334
 335 #define MIN_YIELD_PERIOD 5  /* ticks */
 336 static long next_yield = 0;
 337
 338 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 339 static const char         sd_thread_name[] = "ata/sd";
 340 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 341 static struct event_queue sd_queue;
 342 #ifndef BOOTLOADER
 343 bool sd_enabled = false;
 344 #endif
 345
 346 static struct wakeup transfer_completion_signal;
 347 static struct wakeup command_completion_signal;
 348 static volatile bool retry;
 349 static volatile int cmd_error;
 350
 351 #if defined(HAVE_MULTIDRIVE)
 352 #define EXT_SD_BITS (1<<2)
 353 #endif
 354
 355 static inline void mci_delay(void) { udelay(1000); }
 356
 357 void INT_NAND(void)
 358 {
 359     MCI_CTRL &= ~INT_ENABLE;
 360     /* use raw status here as we need to check some Ints that are masked */
 361     const int status = MCI_RAW_STATUS;
 362
 363     MCI_RAW_STATUS = status;    /* clear status */
 364
 365     if(status & MCI_DATA_ERROR)
 366         retry = true;
 367
 368     if( status & (MCI_INT_DTO|MCI_DATA_ERROR))
 369         wakeup_signal(&transfer_completion_signal);
 370
 371     cmd_error = status & MCI_CMD_ERROR;
 372
 373     if(status & MCI_INT_CD)
 374         wakeup_signal(&command_completion_signal);
 375
 376     MCI_CTRL |= INT_ENABLE;
 377 }
 378
 379 static inline bool card_detect_target(void)
 380 {
 381 #if defined(HAVE_MULTIDRIVE)
 382 #if defined(SANSA_FUZEV2)
 383     return GPIOA_PIN(2);
 384 #elif defined(SANSA_CLIPPLUS)
 385     return !(GPIOA_PIN(2));
 386 #else
 387 #error "microSD pin not defined for your target"
 388 #endif
 389 #else
 390     return false;
 391 #endif
 392 }
 393
 394 static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
 395         unsigned long *response)
 396 {
 397 #if defined(HAVE_MULTIDRIVE)
 398     if(sd_present(SD_SLOT_AS3525))
 399         GPIOB_PIN(5) = (1-drive) << 5;
 400 #endif
 401
 402     MCI_ARGUMENT = arg;
 403
 404     /* Construct MCI_COMMAND  */
 405     MCI_COMMAND =
 406       /*b5:0*/    cmd
 407       /*b6  */  | ((flags & MCI_RESP)                ? CMD_RESP_EXP_BIT:      0)
 408       /*b7  */  | ((flags & MCI_LONG_RESP)           ? CMD_RESP_LENGTH_BIT:   0)
 409       /*b8      | CMD_CHECK_CRC_BIT       unused  */
 410       /*b9  */  | (TRANSFER_CMD                      ? CMD_DATA_EXP_BIT:      0)
 411       /*b10 */  | ((cmd == SD_WRITE_MULTIPLE_BLOCK)  ? CMD_RW_BIT:            0)
 412       /*b11     | CMD_TRANSMODE_BIT       unused  */
 413       /*b12     | CMD_SENT_AUTO_STOP_BIT  unused  */
 414       /*b13 */  | (TRANSFER_CMD                      ? CMD_WAIT_PRV_DAT_BIT:  0)
 415       /*b14     | CMD_ABRT_CMD_BIT        unused  */
 416       /*b15     | CMD_SEND_INIT_BIT       unused  */
 417    /*b20:16 */  |                                      CMD_CARD_NO(drive)
 418       /*b21     | CMD_SEND_CLK_ONLY       unused  */
 419       /*b22     | CMD_READ_CEATA          unused  */
 420       /*b23     | CMD_CCS_EXPECTED        unused  */
 421       /*b31 */  |                                      CMD_DONE_BIT;
 422
 423 #ifdef SANSA_FUZEV2
 424     extern int buttonlight_is_on;
 425     if(buttonlight_is_on)
 426         _buttonlight_on();
 427     else
 428         _buttonlight_off();
 429 #endif
 430     wakeup_wait(&command_completion_signal, TIMEOUT_BLOCK);
 431
 432     /*  Handle command responses & errors */
 433     if(flags & MCI_RESP)
 434     {
 435         if(cmd_error & (MCI_INT_RCRC | MCI_INT_RTO))
 436             return false;
 437
 438         if(flags & MCI_LONG_RESP)
 439         {
 440             response[0] = MCI_RESP3;
 441             response[1] = MCI_RESP2;
 442             response[2] = MCI_RESP1;
 443             response[3] = MCI_RESP0;
 444         }
 445         else
 446             response[0] = MCI_RESP0;
 447     }
 448     return true;
 449 }
 450
 451 static int sd_wait_for_tran_state(const int drive)
 452 {
 453     unsigned long response;
 454     unsigned int timeout = current_tick + 5*HZ;
 455
 456     while (1)
 457     {
 458         while(!(send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP, &response)));
 459
 460         if (((response >> 9) & 0xf) == SD_TRAN)
 461             return 0;
 462
 463         if(TIME_AFTER(current_tick, timeout))
 464             return -10 * ((response >> 9) & 0xf);
 465
 466         if (TIME_AFTER(current_tick, next_yield))
 467         {
 468             yield();
 469             next_yield = current_tick + MIN_YIELD_PERIOD;
 470         }
 471     }
 472 }
 473
 474
 475 static int sd_init_card(const int drive)
 476 {
 477     unsigned long response;
 478     long init_timeout;
 479     bool sd_v2 = false;
 480
 481     /*  assume 24 MHz clock / 60 = 400 kHz  */
 482     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
 483
 484     /* 100 - 400kHz clock required for Identification Mode  */
 485     /*  Start of Card Identification Mode ************************************/
 486
 487     /* CMD0 Go Idle  */
 488     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 489         return -1;
 490     mci_delay();
 491
 492     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 493       Non v2 cards will not respond to this command*/
 494     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 495         if((response & 0xFFF) == 0x1AA)
 496             sd_v2 = true;
 497
 498     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 499     init_timeout = current_tick + HZ;
 500
 501     do {
 502         /* this timeout is the only valid error for this loop*/
 503         if(TIME_AFTER(current_tick, init_timeout))
 504             return -2;
 505
 506         /* app_cmd */
 507         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP, &response);
 508
 509          /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 510         if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 511                         MCI_RESP, &card_info[drive].ocr))
 512             return -3;
 513     } while(!(card_info[drive].ocr & (1<<31)) );
 514
 515     /* CMD2 send CID */
 516     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
 517         return -4;
 518
 519     /* CMD3 send RCA */
 520     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 521         return -5;
 522
 523 #ifdef HAVE_MULTIDRIVE
 524     /* Make sure we have 2 unique rca numbers */
 525     if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
 526         if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 527             return -6;
 528 #endif
 529     /*  End of Card Identification Mode   ************************************/
 530
 531     /* Attempt to switch cards to HS timings, non HS cards just ignore this */
 532     /*  CMD7 w/rca: Select card to put it in TRAN state */
 533     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 534         return -7;
 535
 536     if(sd_wait_for_tran_state(drive))
 537         return -8;
 538
 539     /* CMD6 */
 540     if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 541         return -9;
 542     mci_delay();
 543
 544     /*  We need to go back to STBY state now so we can read csd */
 545     /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 546     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 547         return -10;
 548
 549     /* CMD9 send CSD */
 550     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 551                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 552         return -11;
 553
 554     sd_parse_csd(&card_info[drive]);
 555
 556     if(drive == INTERNAL_AS3525) /* The OF is stored in the first blocks */
 557         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 558
 559     /*  Card back to full speed  */
 560     MCI_CLKDIV &= ~(0xFF);    /* CLK_DIV_0 : bits 7:0 = 0x00 */
 561
 562     /*  CMD7 w/rca: Select card to put it in TRAN state */
 563     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 564         return -12;
 565
 566 #ifndef BOOTLOADER
 567     /*  Switch to to 4 bit widebus mode  */
 568     if(sd_wait_for_tran_state(drive) < 0)
 569         return -13;
 570     /* CMD55 */              /*  Response is requested due to timing issue  */
 571     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 572         return -14;
 573     /* ACMD6  */
 574     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_NO_RESP, NULL))
 575         return -15;
 576     mci_delay();
 577     /* CMD55 */             /*  Response is requested due to timing issue  */
 578     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 579         return -16;
 580     /* ACMD42  */
 581     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_NO_RESP, NULL))
 582         return -17;
 583     /* Now that card is widebus make controller aware */
 584     MCI_CTYPE |= (1<<drive);
 585 #endif
 586
 587     card_info[drive].initialized = 1;
 588
 589     MCI_CLKENA |= 1<<(drive + 16);      /*  Set low power mode  */
 590
 591     return 0;
 592 }
 593
 594 static void sd_thread(void) __attribute__((noreturn));
 595 static void sd_thread(void)
 596 {
 597     struct queue_event ev;
 598     bool idle_notified = false;
 599
 600     while (1)
 601     {
 602         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 603
 604         switch ( ev.id )
 605         {
 606 #ifdef HAVE_HOTSWAP
 607         case SYS_HOTSWAP_INSERTED:
 608         case SYS_HOTSWAP_EXTRACTED:
 609         {
 610             int microsd_init = 1;
 611             fat_lock();          /* lock-out FAT activity first -
 612                                     prevent deadlocking via disk_mount that
 613                                     would cause a reverse-order attempt with
 614                                     another thread */
 615             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 616                                     into driver that bypass the fat cache */
 617
 618             /* We now have exclusive control of fat cache and ata */
 619
 620             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 621                                     descriptors aren't leaked and any busy
 622                                     ones are invalid if mounting */
 623             /* Force card init for new card, re-init for re-inserted one or
 624              * clear if the last attempt to init failed with an error. */
 625             card_info[SD_SLOT_AS3525].initialized = 0;
 626
 627             if (ev.id == SYS_HOTSWAP_INSERTED)
 628             {
 629                 sd_enable(true);
 630                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 631                 if (microsd_init < 0) /* initialisation failed */
 632                     panicf("microSD init failed : %d", microsd_init);
 633
 634                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 635             }
 636
 637             /*
 638              * Mount succeeded, or this was an EXTRACTED event,
 639              * in both cases notify the system about the changed filesystems
 640              */
 641             if (microsd_init)
 642                 queue_broadcast(SYS_FS_CHANGED, 0);
 643             /* Access is now safe */
 644             mutex_unlock(&sd_mtx);
 645             fat_unlock();
 646             sd_enable(false);
 647         }
 648             break;
 649 #endif
 650         case SYS_TIMEOUT:
 651             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 652             {
 653                 idle_notified = false;
 654             }
 655             else
 656             {
 657                 /* never let a timer wrap confuse us */
 658                 next_yield = current_tick;
 659
 660                 if (!idle_notified)
 661                 {
 662                     call_storage_idle_notifys(false);
 663                     idle_notified = true;
 664                 }
 665             }
 666             break;
 667
 668         case SYS_USB_CONNECTED:
 669             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 670             /* Wait until the USB cable is extracted again */
 671             usb_wait_for_disconnect(&sd_queue);
 672
 673             break;
 674         case SYS_USB_DISCONNECTED:
 675             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 676             break;
 677         }
 678     }
 679 }
 680
 681 static void init_controller(void)
 682 {
 683     int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
 684     int card_mask = (1 << hcon_numcards) - 1;
 685
 686     MCI_PWREN &= ~card_mask;            /*  power off all cards  */
 687
 688     MCI_CLKSRC = 0x00;                  /* All CLK_SRC_CRD set to 0*/
 689     MCI_CLKDIV = 0x00;                  /* CLK_DIV_0 : bits 7:0  */
 690
 691     MCI_PWREN |= card_mask;             /*  power up cards  */
 692     mci_delay();
 693
 694     MCI_CTRL |= CTRL_RESET;
 695     while(MCI_CTRL & CTRL_RESET)
 696         ;
 697
 698     MCI_RAW_STATUS = 0xffffffff;        /* Clear all MCI Interrupts  */
 699
 700     MCI_TMOUT = 0xffffffff;             /*  data b31:8, response b7:0 */
 701
 702     MCI_CTYPE = 0x0;                    /*  all cards 1 bit bus for now */
 703
 704     MCI_CLKENA = card_mask;             /*  Enables card clocks  */
 705
 706     MCI_ARGUMENT = 0;
 707     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 708     while(MCI_COMMAND & CMD_DONE_BIT)
 709         ;
 710
 711     MCI_DEBNCE = 0xfffff;               /* default value */
 712
 713     /* Rx watermark = 63(sd reads)  Tx watermark = 128 (sd writes) */
 714     MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
 715
 716 /*  RCRC & RTO interrupts should be set together with the CD interrupt but
 717  *  in practice sometimes incorrectly precede the CD interrupt.  If we leave
 718  *  them masked for now we can check them in the isr by reading raw status when
 719  *  the CD int is triggered.
 720  */
 721     MCI_MASK |= (MCI_DATA_ERROR | MCI_INT_DTO | MCI_INT_CD);
 722
 723     MCI_CTRL |= INT_ENABLE | DMA_ENABLE;
 724
 725     MCI_BLKSIZ = SD_BLOCK_SIZE;
 726 }
 727
 728 int sd_init(void)
 729 {
 730     int ret;
 731
 732     bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
 733
 734     CGU_IDE =   (1<<7)          /* AHB interface enable */
 735             |   (AS3525_IDE_DIV << 2)
 736             |   1;              /* clock source = PLLA */
 737
 738     CGU_MEMSTICK =  (1<<7)      /* interface enable */
 739                  |  (AS3525_MS_DIV << 2)
 740                  |  1;          /* clock source = PLLA */
 741
 742     CGU_SDSLOT = (1<<7)         /* interface enable */
 743                | (AS3525_SDSLOT_DIV << 2)
 744                | 1;             /* clock source = PLLA */
 745
 746     wakeup_init(&transfer_completion_signal);
 747     wakeup_init(&command_completion_signal);
 748 #ifdef HAVE_MULTIDRIVE
 749     /* clear previous irq */
 750     GPIOA_IC = EXT_SD_BITS;
 751     /* enable edge detecting */
 752     GPIOA_IS &= ~EXT_SD_BITS;
 753     /* detect both raising and falling edges */
 754     GPIOA_IBE |= EXT_SD_BITS;
 755     /* enable the card detect interrupt */
 756     GPIOA_IE |= EXT_SD_BITS;
 757
 758     /* Configure XPD for SD-MCI interface */
 759     CCU_IO |= (1<<2);
 760 #endif
 761
 762     VIC_INT_ENABLE = INTERRUPT_NAND;
 763
 764     init_controller();
 765     ret = sd_init_card(INTERNAL_AS3525);
 766     if(ret < 0)
 767         return ret;
 768
 769     /* init mutex */
 770     mutex_init(&sd_mtx);
 771
 772     queue_init(&sd_queue, true);
 773     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 774             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 775
 776 #ifndef BOOTLOADER
 777     sd_enabled = true;
 778     sd_enable(false);
 779 #endif
 780     return 0;
 781 }
 782
 783 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 784                                 int count, void* buf, bool write)
 785 {
 786     int ret = 0;
 787 #ifndef HAVE_MULTIDRIVE
 788     const int drive = 0;
 789 #endif
 790     bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
 791
 792
 793     mutex_lock(&sd_mtx);
 794 #ifndef BOOTLOADER
 795     sd_enable(true);
 796     led(true);
 797 #endif
 798
 799     if (card_info[drive].initialized <= 0)
 800     {
 801         ret = sd_init_card(drive);
 802         if (!(card_info[drive].initialized))
 803         {
 804             panicf("card not initialised (%d)", ret);
 805             goto sd_transfer_error;
 806         }
 807     }
 808
 809     if(count < 0) /* XXX: why is it signed ? */
 810     {
 811         ret = -18;
 812         goto sd_transfer_error;
 813     }
 814     if((start+count) > card_info[drive].numblocks)
 815     {
 816         ret = -19;
 817         goto sd_transfer_error;
 818     }
 819
 820     /* skip SanDisk OF */
 821     if (drive == INTERNAL_AS3525)
 822         start += AMS_OF_SIZE;
 823
 824     /*  CMD7 w/rca: Select card to put it in TRAN state */
 825     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 826         return -20;
 827
 828     last_disk_activity = current_tick;
 829     dma_retain();
 830
 831     if(aligned)
 832     {
 833         if(write)
 834             clean_dcache_range(buf, count * SECTOR_SIZE);
 835         else
 836             dump_dcache_range(buf, count * SECTOR_SIZE);
 837     }
 838
 839     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 840
 841     do
 842     {
 843         void *dma_buf;
 844         unsigned int transfer = count;
 845
 846         if(aligned)
 847         {
 848             dma_buf = AS3525_PHYSICAL_ADDR(buf);
 849         }
 850         else
 851         {
 852             dma_buf = aligned_buffer;
 853             if(transfer > UNALIGNED_NUM_SECTORS)
 854                 transfer = UNALIGNED_NUM_SECTORS;
 855
 856             if(write)
 857                 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 858         }
 859
 860         /* Interrupt handler might set this to true during transfer */
 861         retry = false;
 862
 863         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
 864
 865         ret = sd_wait_for_tran_state(drive);
 866         if (ret < 0)
 867         {
 868             static const char *st[9] = {
 869                 "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV",
 870                                                                 "PRG", "DIS"};
 871             if(ret <= -10)
 872                 panicf("wait for TRAN state failed (%s) %d",
 873                                                     st[(-ret / 10) % 9], drive);
 874             else
 875                 panicf("wait for state failed");
 876             goto sd_transfer_error;
 877         }
 878
 879         int arg = start;
 880         if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
 881             arg *= SD_BLOCK_SIZE;
 882
 883         if(write)
 884             dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
 885                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 886         else
 887             dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
 888                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 889
 890         unsigned long dummy; /* if we don't ask for a response, writing fails */
 891         if(!send_cmd(drive, cmd, arg, MCI_RESP, &dummy))
 892             panicf("%s multiple blocks failed", write ? "write" : "read");
 893
 894         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 895
 896         last_disk_activity = current_tick;
 897
 898         if(write)
 899         {
 900             /* wait for the card to exit programming state */
 901             while(MCI_STATUS & DATA_BUSY) ;
 902         }
 903
 904         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
 905         {
 906             ret = -666;
 907             panicf("STOP TRANSMISSION failed");
 908             goto sd_transfer_error;
 909         }
 910
 911         if(!retry)
 912         {
 913             if(!write && !aligned)
 914                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 915             buf += transfer * SD_BLOCK_SIZE;
 916             start += transfer;
 917             count -= transfer;
 918         }
 919         else   /*  reset controller if we had an error  */
 920         {
 921             MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 922             while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 923                 ;
 924         }
 925
 926     } while(retry || count);
 927
 928     dma_release();
 929
 930 #ifndef BOOTLOADER
 931     sd_enable(false);
 932     led(false);
 933 #endif
 934     mutex_unlock(&sd_mtx);
 935     return 0;
 936
 937 sd_transfer_error:
 938     panicf("transfer error : %d",ret);
 939     card_info[drive].initialized = 0;
 940     return ret;
 941 }
 942
 943 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 944                     void* buf)
 945 {
 946     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 947 }
 948
 949 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 950                      const void* buf)
 951 {
 952 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
 953 #ifdef HAVE_MULTIDRIVE
 954     (void) drive;
 955 #endif
 956     (void) start;
 957     (void) count;
 958     (void) buf;
 959     return -1;
 960 #else
 961     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 962 #endif /* defined(BOOTLOADER) */
 963 }
 964
 965 #ifndef BOOTLOADER
 966 long sd_last_disk_activity(void)
 967 {
 968     return last_disk_activity;
 969 }
 970
 971 void sd_enable(bool on)
 972 {
 973     if (on)
 974     {
 975         bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
 976         CGU_IDE |= (1<<7);                  /* AHB interface enable */
 977         CGU_MEMSTICK |= (1<<7);             /* interface enable */
 978         CGU_SDSLOT |= (1<<7);               /* interface enable */
 979     }
 980     else
 981     {
 982         CGU_SDSLOT &= ~(1<<7);              /* interface enable */
 983         CGU_MEMSTICK &= ~(1<<7);            /* interface enable */
 984         CGU_IDE &= ~(1<<7);                 /* AHB interface enable */
 985         bitclr32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
 986     }
 987 }
 988
 989 tCardInfo *card_get_info_target(int card_no)
 990 {
 991     return &card_info[card_no];
 992 }
 993 #endif /* BOOTLOADER */
 994
 995 #ifdef HAVE_HOTSWAP
 996 bool sd_removable(IF_MD_NONVOID(int drive))
 997 {
 998     return (drive==1);
 999 }
1000
1001 bool sd_present(IF_MD_NONVOID(int drive))
1002 {
1003     return (drive == 0) ? true : card_detect_target();
1004 }
1005
1006 static int sd1_oneshot_callback(struct timeout *tmo)
1007 {
1008     (void)tmo;
1009
1010     /* This is called only if the state was stable for 300ms - check state
1011      * and post appropriate event. */
1012     if (card_detect_target())
1013     {
1014         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
1015     }
1016     else
1017         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
1018
1019     return 0;
1020 }
1021
1022 void sd_gpioa_isr(void)
1023 {
1024     static struct timeout sd1_oneshot;
1025     if (GPIOA_MIS & EXT_SD_BITS)
1026         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
1027     /* acknowledge interrupt */
1028     GPIOA_IC = EXT_SD_BITS;
1029 }
1030 #endif /* HAVE_HOTSWAP */
1031
1032 #ifdef CONFIG_STORAGE_MULTI
1033 int sd_num_drives(int first_drive)
1034 {
1035     /* We don't care which logical drive number(s) we have been assigned */
1036     (void)first_drive;
1037
1038     return NUM_DRIVES;
1039 }
1040 #endif /* CONFIG_STORAGE_MULTI */