firmware/target/arm/usb-drv-arc.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Driver for ARC USBOTG Device Controller
  11  *
  12  * Copyright (C) 2007 by Björn Stenberg
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23
  24 #include "system.h"
  25 #include "config.h"
  26 #include "string.h"
  27 #include "usb_ch9.h"
  28 #include "usb_core.h"
  29 #include "kernel.h"
  30 #include "panic.h"
  31 #include "usb_drv.h"
  32
  33 //#define LOGF_ENABLE
  34 #include "logf.h"
  35
  36 /* USB device mode registers (Little Endian) */
  37
  38 #define REG_ID               (*(volatile unsigned int *)(USB_BASE+0x000))
  39 #define REG_HWGENERAL        (*(volatile unsigned int *)(USB_BASE+0x004))
  40 #define REG_HWHOST           (*(volatile unsigned int *)(USB_BASE+0x008))
  41 #define REG_HWDEVICE         (*(volatile unsigned int *)(USB_BASE+0x00c))
  42 #define REG_TXBUF            (*(volatile unsigned int *)(USB_BASE+0x010))
  43 #define REG_RXBUF            (*(volatile unsigned int *)(USB_BASE+0x014))
  44 #define REG_CAPLENGTH        (*(volatile unsigned char*)(USB_BASE+0x100))
  45 #define REG_DCIVERSION       (*(volatile unsigned int *)(USB_BASE+0x120))
  46 #define REG_DCCPARAMS        (*(volatile unsigned int *)(USB_BASE+0x124))
  47 #define REG_USBCMD           (*(volatile unsigned int *)(USB_BASE+0x140))
  48 #define REG_USBSTS           (*(volatile unsigned int *)(USB_BASE+0x144))
  49 #define REG_USBINTR          (*(volatile unsigned int *)(USB_BASE+0x148))
  50 #define REG_FRINDEX          (*(volatile unsigned int *)(USB_BASE+0x14c))
  51 #define REG_DEVICEADDR       (*(volatile unsigned int *)(USB_BASE+0x154))
  52 #define REG_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158))
  53 #define REG_BURSTSIZE        (*(volatile unsigned int *)(USB_BASE+0x160))
  54 #define REG_ULPI             (*(volatile unsigned int *)(USB_BASE+0x170))
  55 #define REG_CONFIGFLAG       (*(volatile unsigned int *)(USB_BASE+0x180))
  56 #define REG_PORTSC1          (*(volatile unsigned int *)(USB_BASE+0x184))
  57 #define REG_OTGSC            (*(volatile unsigned int *)(USB_BASE+0x1a4))
  58 #define REG_USBMODE          (*(volatile unsigned int *)(USB_BASE+0x1a8))
  59 #define REG_ENDPTSETUPSTAT   (*(volatile unsigned int *)(USB_BASE+0x1ac))
  60 #define REG_ENDPTPRIME       (*(volatile unsigned int *)(USB_BASE+0x1b0))
  61 #define REG_ENDPTFLUSH       (*(volatile unsigned int *)(USB_BASE+0x1b4))
  62 #define REG_ENDPTSTATUS      (*(volatile unsigned int *)(USB_BASE+0x1b8))
  63 #define REG_ENDPTCOMPLETE    (*(volatile unsigned int *)(USB_BASE+0x1bc))
  64 #define REG_ENDPTCTRL0       (*(volatile unsigned int *)(USB_BASE+0x1c0))
  65 #define REG_ENDPTCTRL1       (*(volatile unsigned int *)(USB_BASE+0x1c4))
  66 #define REG_ENDPTCTRL2       (*(volatile unsigned int *)(USB_BASE+0x1c8))
  67 #define REG_ENDPTCTRL(_x_)   (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(_x_)))
  68
  69 /* Frame Index Register Bit Masks */
  70 #define USB_FRINDEX_MASKS                      (0x3fff)
  71
  72 /* USB CMD  Register Bit Masks */
  73 #define USBCMD_RUN                            (0x00000001)
  74 #define USBCMD_CTRL_RESET                     (0x00000002)
  75 #define USBCMD_PERIODIC_SCHEDULE_EN           (0x00000010)
  76 #define USBCMD_ASYNC_SCHEDULE_EN              (0x00000020)
  77 #define USBCMD_INT_AA_DOORBELL                (0x00000040)
  78 #define USBCMD_ASP                            (0x00000300)
  79 #define USBCMD_ASYNC_SCH_PARK_EN              (0x00000800)
  80 #define USBCMD_SUTW                           (0x00002000)
  81 #define USBCMD_ATDTW                          (0x00004000)
  82 #define USBCMD_ITC                            (0x00FF0000)
  83
  84 /* bit 15,3,2 are frame list size */
  85 #define USBCMD_FRAME_SIZE_1024                (0x00000000)
  86 #define USBCMD_FRAME_SIZE_512                 (0x00000004)
  87 #define USBCMD_FRAME_SIZE_256                 (0x00000008)
  88 #define USBCMD_FRAME_SIZE_128                 (0x0000000C)
  89 #define USBCMD_FRAME_SIZE_64                  (0x00008000)
  90 #define USBCMD_FRAME_SIZE_32                  (0x00008004)
  91 #define USBCMD_FRAME_SIZE_16                  (0x00008008)
  92 #define USBCMD_FRAME_SIZE_8                   (0x0000800C)
  93
  94 /* bit 9-8 are async schedule park mode count */
  95 #define USBCMD_ASP_00                         (0x00000000)
  96 #define USBCMD_ASP_01                         (0x00000100)
  97 #define USBCMD_ASP_10                         (0x00000200)
  98 #define USBCMD_ASP_11                         (0x00000300)
  99 #define USBCMD_ASP_BIT_POS                    (8)
 100
 101 /* bit 23-16 are interrupt threshold control */
 102 #define USBCMD_ITC_NO_THRESHOLD               (0x00000000)
 103 #define USBCMD_ITC_1_MICRO_FRM                (0x00010000)
 104 #define USBCMD_ITC_2_MICRO_FRM                (0x00020000)
 105 #define USBCMD_ITC_4_MICRO_FRM                (0x00040000)
 106 #define USBCMD_ITC_8_MICRO_FRM                (0x00080000)
 107 #define USBCMD_ITC_16_MICRO_FRM               (0x00100000)
 108 #define USBCMD_ITC_32_MICRO_FRM               (0x00200000)
 109 #define USBCMD_ITC_64_MICRO_FRM               (0x00400000)
 110 #define USBCMD_ITC_BIT_POS                    (16)
 111
 112 /* USB STS Register Bit Masks */
 113 #define USBSTS_INT                            (0x00000001)
 114 #define USBSTS_ERR                            (0x00000002)
 115 #define USBSTS_PORT_CHANGE                    (0x00000004)
 116 #define USBSTS_FRM_LST_ROLL                   (0x00000008)
 117 #define USBSTS_SYS_ERR                        (0x00000010) /* not used */
 118 #define USBSTS_IAA                            (0x00000020)
 119 #define USBSTS_RESET                          (0x00000040)
 120 #define USBSTS_SOF                            (0x00000080)
 121 #define USBSTS_SUSPEND                        (0x00000100)
 122 #define USBSTS_HC_HALTED                      (0x00001000)
 123 #define USBSTS_RCL                            (0x00002000)
 124 #define USBSTS_PERIODIC_SCHEDULE              (0x00004000)
 125 #define USBSTS_ASYNC_SCHEDULE                 (0x00008000)
 126
 127 /* USB INTR Register Bit Masks */
 128 #define USBINTR_INT_EN                        (0x00000001)
 129 #define USBINTR_ERR_INT_EN                    (0x00000002)
 130 #define USBINTR_PTC_DETECT_EN                 (0x00000004)
 131 #define USBINTR_FRM_LST_ROLL_EN               (0x00000008)
 132 #define USBINTR_SYS_ERR_EN                    (0x00000010)
 133 #define USBINTR_ASYN_ADV_EN                   (0x00000020)
 134 #define USBINTR_RESET_EN                      (0x00000040)
 135 #define USBINTR_SOF_EN                        (0x00000080)
 136 #define USBINTR_DEVICE_SUSPEND                (0x00000100)
 137
 138 /* ULPI Register Bit Masks */
 139 #define ULPI_ULPIWU                           (0x80000000)
 140 #define ULPI_ULPIRUN                          (0x40000000)
 141 #define ULPI_ULPIRW                           (0x20000000)
 142 #define ULPI_ULPISS                           (0x08000000)
 143 #define ULPI_ULPIPORT                         (0x07000000)
 144 #define ULPI_ULPIADDR                         (0x00FF0000)
 145 #define ULPI_ULPIDATRD                        (0x0000FF00)
 146 #define ULPI_ULPIDATWR                        (0x000000FF)
 147
 148 /* Device Address bit masks */
 149 #define USBDEVICEADDRESS_MASK                 (0xFE000000)
 150 #define USBDEVICEADDRESS_BIT_POS              (25)
 151
 152 /* endpoint list address bit masks */
 153 #define USB_EP_LIST_ADDRESS_MASK               (0xfffff800)
 154
 155 /* PORTSCX  Register Bit Masks */
 156 #define PORTSCX_CURRENT_CONNECT_STATUS         (0x00000001)
 157 #define PORTSCX_CONNECT_STATUS_CHANGE          (0x00000002)
 158 #define PORTSCX_PORT_ENABLE                    (0x00000004)
 159 #define PORTSCX_PORT_EN_DIS_CHANGE             (0x00000008)
 160 #define PORTSCX_OVER_CURRENT_ACT               (0x00000010)
 161 #define PORTSCX_OVER_CURRENT_CHG               (0x00000020)
 162 #define PORTSCX_PORT_FORCE_RESUME              (0x00000040)
 163 #define PORTSCX_PORT_SUSPEND                   (0x00000080)
 164 #define PORTSCX_PORT_RESET                     (0x00000100)
 165 #define PORTSCX_LINE_STATUS_BITS               (0x00000C00)
 166 #define PORTSCX_PORT_POWER                     (0x00001000)
 167 #define PORTSCX_PORT_INDICTOR_CTRL             (0x0000C000)
 168 #define PORTSCX_PORT_TEST_CTRL                 (0x000F0000)
 169 #define PORTSCX_WAKE_ON_CONNECT_EN             (0x00100000)
 170 #define PORTSCX_WAKE_ON_CONNECT_DIS            (0x00200000)
 171 #define PORTSCX_WAKE_ON_OVER_CURRENT           (0x00400000)
 172 #define PORTSCX_PHY_LOW_POWER_SPD              (0x00800000)
 173 #define PORTSCX_PORT_FORCE_FULL_SPEED          (0x01000000)
 174 #define PORTSCX_PORT_SPEED_MASK                (0x0C000000)
 175 #define PORTSCX_PORT_WIDTH                     (0x10000000)
 176 #define PORTSCX_PHY_TYPE_SEL                   (0xC0000000)
 177
 178 /* bit 11-10 are line status */
 179 #define PORTSCX_LINE_STATUS_SE0                (0x00000000)
 180 #define PORTSCX_LINE_STATUS_JSTATE             (0x00000400)
 181 #define PORTSCX_LINE_STATUS_KSTATE             (0x00000800)
 182 #define PORTSCX_LINE_STATUS_UNDEF              (0x00000C00)
 183 #define PORTSCX_LINE_STATUS_BIT_POS            (10)
 184
 185 /* bit 15-14 are port indicator control */
 186 #define PORTSCX_PIC_OFF                        (0x00000000)
 187 #define PORTSCX_PIC_AMBER                      (0x00004000)
 188 #define PORTSCX_PIC_GREEN                      (0x00008000)
 189 #define PORTSCX_PIC_UNDEF                      (0x0000C000)
 190 #define PORTSCX_PIC_BIT_POS                    (14)
 191
 192 /* bit 19-16 are port test control */
 193 #define PORTSCX_PTC_DISABLE                    (0x00000000)
 194 #define PORTSCX_PTC_JSTATE                     (0x00010000)
 195 #define PORTSCX_PTC_KSTATE                     (0x00020000)
 196 #define PORTSCX_PTC_SE0NAK                     (0x00030000)
 197 #define PORTSCX_PTC_PACKET                     (0x00040000)
 198 #define PORTSCX_PTC_FORCE_EN                   (0x00050000)
 199 #define PORTSCX_PTC_BIT_POS                    (16)
 200
 201 /* bit 27-26 are port speed */
 202 #define PORTSCX_PORT_SPEED_FULL                (0x00000000)
 203 #define PORTSCX_PORT_SPEED_LOW                 (0x04000000)
 204 #define PORTSCX_PORT_SPEED_HIGH                (0x08000000)
 205 #define PORTSCX_PORT_SPEED_UNDEF               (0x0C000000)
 206 #define PORTSCX_SPEED_BIT_POS                  (26)
 207
 208 /* bit 28 is parallel transceiver width for UTMI interface */
 209 #define PORTSCX_PTW                            (0x10000000)
 210 #define PORTSCX_PTW_8BIT                       (0x00000000)
 211 #define PORTSCX_PTW_16BIT                      (0x10000000)
 212
 213 /* bit 31-30 are port transceiver select */
 214 #define PORTSCX_PTS_UTMI                       (0x00000000)
 215 #define PORTSCX_PTS_CLASSIC                    (0x40000000)
 216 #define PORTSCX_PTS_ULPI                       (0x80000000)
 217 #define PORTSCX_PTS_FSLS                       (0xC0000000)
 218 #define PORTSCX_PTS_BIT_POS                    (30)
 219
 220 /* USB MODE Register Bit Masks */
 221 #define USBMODE_CTRL_MODE_IDLE                (0x00000000)
 222 #define USBMODE_CTRL_MODE_DEVICE              (0x00000002)
 223 #define USBMODE_CTRL_MODE_HOST                (0x00000003)
 224 #define USBMODE_CTRL_MODE_RSV                 (0x00000001)
 225 #define USBMODE_SETUP_LOCK_OFF                (0x00000008)
 226 #define USBMODE_STREAM_DISABLE                (0x00000010)
 227
 228 /* Endpoint Flush Register */
 229 #define EPFLUSH_TX_OFFSET                      (0x00010000)
 230 #define EPFLUSH_RX_OFFSET                      (0x00000000)
 231
 232 /* Endpoint Setup Status bit masks */
 233 #define EPSETUP_STATUS_MASK                   (0x0000003F)
 234 #define EPSETUP_STATUS_EP0                    (0x00000001)
 235
 236 /* ENDPOINTCTRLx  Register Bit Masks */
 237 #define EPCTRL_TX_ENABLE                       (0x00800000)
 238 #define EPCTRL_TX_DATA_TOGGLE_RST              (0x00400000)    /* Not EP0 */
 239 #define EPCTRL_TX_DATA_TOGGLE_INH              (0x00200000)    /* Not EP0 */
 240 #define EPCTRL_TX_TYPE                         (0x000C0000)
 241 #define EPCTRL_TX_DATA_SOURCE                  (0x00020000)    /* Not EP0 */
 242 #define EPCTRL_TX_EP_STALL                     (0x00010000)
 243 #define EPCTRL_RX_ENABLE                       (0x00000080)
 244 #define EPCTRL_RX_DATA_TOGGLE_RST              (0x00000040)    /* Not EP0 */
 245 #define EPCTRL_RX_DATA_TOGGLE_INH              (0x00000020)    /* Not EP0 */
 246 #define EPCTRL_RX_TYPE                         (0x0000000C)
 247 #define EPCTRL_RX_DATA_SINK                    (0x00000002)    /* Not EP0 */
 248 #define EPCTRL_RX_EP_STALL                     (0x00000001)
 249
 250 /* bit 19-18 and 3-2 are endpoint type */
 251 #define EPCTRL_EP_TYPE_CONTROL                 (0)
 252 #define EPCTRL_EP_TYPE_ISO                     (1)
 253 #define EPCTRL_EP_TYPE_BULK                    (2)
 254 #define EPCTRL_EP_TYPE_INTERRUPT               (3)
 255 #define EPCTRL_TX_EP_TYPE_SHIFT                (18)
 256 #define EPCTRL_RX_EP_TYPE_SHIFT                (2)
 257
 258 /* pri_ctrl Register Bit Masks */
 259 #define PRI_CTRL_PRI_LVL1                      (0x0000000C)
 260 #define PRI_CTRL_PRI_LVL0                      (0x00000003)
 261
 262 /* si_ctrl Register Bit Masks */
 263 #define SI_CTRL_ERR_DISABLE                    (0x00000010)
 264 #define SI_CTRL_IDRC_DISABLE                   (0x00000008)
 265 #define SI_CTRL_RD_SAFE_EN                     (0x00000004)
 266 #define SI_CTRL_RD_PREFETCH_DISABLE            (0x00000002)
 267 #define SI_CTRL_RD_PREFEFETCH_VAL              (0x00000001)
 268
 269 /* control Register Bit Masks */
 270 #define USB_CTRL_IOENB                         (0x00000004)
 271 #define USB_CTRL_ULPI_INT0EN                   (0x00000001)
 272
 273 /* OTGSC Register Bit Masks */
 274 #define OTGSC_B_SESSION_VALID                  (0x00000800)
 275 #define OTGSC_A_VBUS_VALID                     (0x00000200)
 276
 277 #define QH_MULT_POS                            (30)
 278 #define QH_ZLT_SEL                             (0x20000000)
 279 #define QH_MAX_PKT_LEN_POS                     (16)
 280 #define QH_IOS                                 (0x00008000)
 281 #define QH_NEXT_TERMINATE                      (0x00000001)
 282 #define QH_IOC                                 (0x00008000)
 283 #define QH_MULTO                               (0x00000C00)
 284 #define QH_STATUS_HALT                         (0x00000040)
 285 #define QH_STATUS_ACTIVE                       (0x00000080)
 286 #define EP_QUEUE_CURRENT_OFFSET_MASK         (0x00000FFF)
 287 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK      (0xFFFFFFE0)
 288 #define EP_QUEUE_FRINDEX_MASK                (0x000007FF)
 289 #define EP_MAX_LENGTH_TRANSFER               (0x4000)
 290
 291 #define DTD_NEXT_TERMINATE                   (0x00000001)
 292 #define DTD_IOC                              (0x00008000)
 293 #define DTD_STATUS_ACTIVE                    (0x00000080)
 294 #define DTD_STATUS_HALTED                    (0x00000040)
 295 #define DTD_STATUS_DATA_BUFF_ERR             (0x00000020)
 296 #define DTD_STATUS_TRANSACTION_ERR           (0x00000008)
 297 #define DTD_RESERVED_FIELDS                  (0x80007300)
 298 #define DTD_ADDR_MASK                        (0xFFFFFFE0)
 299 #define DTD_PACKET_SIZE                      (0x7FFF0000)
 300 #define DTD_LENGTH_BIT_POS                   (16)
 301 #define DTD_ERROR_MASK                       (DTD_STATUS_HALTED | \
 302                                                DTD_STATUS_DATA_BUFF_ERR | \
 303                                                DTD_STATUS_TRANSACTION_ERR)
 304
 305 #define DTD_RESERVED_LENGTH_MASK             0x0001ffff
 306 #define DTD_RESERVED_IN_USE                  0x80000000
 307 #define DTD_RESERVED_PIPE_MASK               0x0ff00000
 308 #define DTD_RESERVED_PIPE_OFFSET             20
 309 /*-------------------------------------------------------------------------*/
 310
 311 /* 4 transfer descriptors per endpoint allow 64k transfers, which is the usual MSC
 312    transfer size, so it seems like a good size */
 313 #define NUM_TDS_PER_EP 4
 314
 315 /* manual: 32.13.2 Endpoint Transfer Descriptor (dTD) */
 316 struct transfer_descriptor {
 317     unsigned int next_td_ptr;           /* Next TD pointer(31-5), T(0) set
 318                                            indicate invalid */
 319     unsigned int size_ioc_sts;          /* Total bytes (30-16), IOC (15),
 320                                            MultO(11-10), STS (7-0)  */
 321     unsigned int buff_ptr0;             /* Buffer pointer Page 0 */
 322     unsigned int buff_ptr1;             /* Buffer pointer Page 1 */
 323     unsigned int buff_ptr2;             /* Buffer pointer Page 2 */
 324     unsigned int buff_ptr3;             /* Buffer pointer Page 3 */
 325     unsigned int buff_ptr4;             /* Buffer pointer Page 4 */
 326     unsigned int reserved;
 327 } __attribute__ ((packed));
 328
 329 static struct transfer_descriptor td_array[USB_NUM_ENDPOINTS*2*NUM_TDS_PER_EP]
 330     USB_DEVBSS_ATTR __attribute__((aligned(32)));
 331
 332 /* manual: 32.13.1 Endpoint Queue Head (dQH) */
 333 struct queue_head {
 334     unsigned int max_pkt_length;    /* Mult(31-30) , Zlt(29) , Max Pkt len
 335                                        and IOS(15) */
 336     unsigned int curr_dtd_ptr;      /* Current dTD Pointer(31-5) */
 337     struct transfer_descriptor dtd; /* dTD overlay */
 338     unsigned int setup_buffer[2];   /* Setup data 8 bytes */
 339     unsigned int reserved;          /* for software use, pointer to the first TD */
 340     unsigned int status;            /* for software use, status of chain in progress */
 341     unsigned int length;            /* for software use, transfered bytes of chain in progress */
 342     unsigned int wait;              /* for softwate use, indicates if the transfer is blocking */
 343 } __attribute__((packed));
 344
 345 static struct queue_head qh_array[USB_NUM_ENDPOINTS*2]
 346     USB_QHARRAY_ATTR;
 347
 348 static struct wakeup transfer_completion_signal[USB_NUM_ENDPOINTS*2]
 349     SHAREDBSS_ATTR;
 350
 351 static const unsigned int pipe2mask[] = {
 352     0x01, 0x010000,
 353     0x02, 0x020000,
 354     0x04, 0x040000,
 355     0x08, 0x080000,
 356     0x10, 0x100000,
 357 };
 358
 359 static char ep_allocation[USB_NUM_ENDPOINTS];
 360
 361 /*-------------------------------------------------------------------------*/
 362 static void transfer_completed(void);
 363 static void control_received(void);
 364 static int prime_transfer(int endpoint, void* ptr,
 365                           int len, bool send, bool wait);
 366 static void prepare_td(struct transfer_descriptor* td,
 367                        struct transfer_descriptor* previous_td,
 368                        void *ptr, int len,int pipe);
 369 static void bus_reset(void);
 370 static void init_control_queue_heads(void);
 371 static void init_bulk_queue_heads(void);
 372 static void init_endpoints(void);
 373 /*-------------------------------------------------------------------------*/
 374 static void usb_drv_stop(void)
 375 {
 376     /* disable interrupts */
 377     REG_USBINTR = 0;
 378     /* stop usb controller (disconnect) */
 379     REG_USBCMD &= ~USBCMD_RUN;
 380 }
 381
 382 void usb_drv_reset(void)
 383 {
 384     int oldlevel = disable_irq_save();
 385     REG_USBCMD &= ~USBCMD_RUN;
 386     restore_irq(oldlevel);
 387
 388 #ifdef USB_PORTSCX_PHY_TYPE
 389     /* If a PHY type is specified, set it now */
 390     REG_PORTSC1 = (REG_PORTSC1 & ~PORTSCX_PHY_TYPE_SEL) | USB_PORTSCX_PHY_TYPE;
 391 #endif
 392     sleep(HZ/20);
 393     REG_USBCMD |= USBCMD_CTRL_RESET;
 394     while (REG_USBCMD & USBCMD_CTRL_RESET);
 395
 396 #if CONFIG_CPU == PP5022 || CONFIG_CPU == PP5024
 397     /* On a CPU which identifies as a PP5022, this
 398        initialization must be done after USB is reset.
 399      */
 400     outl(inl(0x70000060) | 0xF, 0x70000060);
 401     outl(inl(0x70000028) | 0x10000, 0x70000028);
 402     outl(inl(0x70000028) & ~0x10000, 0x70000028);
 403     outl(inl(0x70000060) & ~0x20, 0x70000060);
 404     udelay(10);
 405     outl(inl(0x70000060) | 0x20, 0x70000060);
 406     udelay(10);
 407     outl((inl(0x70000060) & ~0xF) | 4, 0x70000060);
 408     udelay(10);
 409     outl(inl(0x70000060) & ~0x20, 0x70000060);
 410     udelay(10);
 411     outl(inl(0x70000060) & ~0xF, 0x70000060);
 412     udelay(10);
 413     outl(inl(0x70000060) | 0x20, 0x70000060);
 414     udelay(10);
 415     outl(inl(0x70000028) | 0x800, 0x70000028);
 416     outl(inl(0x70000028) & ~0x800, 0x70000028);
 417     while ((inl(0x70000028) & 0x80) == 0);
 418 #endif
 419 }
 420
 421 /* One-time driver startup init */
 422 void usb_drv_startup(void)
 423 {
 424     /* Initialize all the signal objects once */
 425     int i;
 426     for(i=0;i<USB_NUM_ENDPOINTS*2;i++) {
 427         wakeup_init(&transfer_completion_signal[i]);
 428     }
 429 }
 430
 431 /* manual: 32.14.1 Device Controller Initialization */
 432 static void _usb_drv_init(bool attach)
 433 {
 434     usb_drv_reset();
 435
 436     REG_USBMODE = USBMODE_CTRL_MODE_DEVICE;
 437
 438 #ifdef USB_NO_HIGH_SPEED
 439     /* Force device to full speed */
 440     /* See 32.9.5.9.2 */
 441     REG_PORTSC1 |= PORTSCX_PORT_FORCE_FULL_SPEED;
 442 #endif
 443
 444     init_control_queue_heads();
 445     memset(td_array, 0, sizeof td_array);
 446
 447     REG_ENDPOINTLISTADDR = (unsigned int)qh_array;
 448     REG_DEVICEADDR = 0;
 449
 450     if (!attach) {
 451         /* enable RESET interrupt */
 452         REG_USBINTR = USBINTR_RESET_EN;
 453     }
 454     else
 455     {
 456         /* enable USB interrupts */
 457         REG_USBINTR =
 458             USBINTR_INT_EN |
 459             USBINTR_ERR_INT_EN |
 460             USBINTR_PTC_DETECT_EN |
 461             USBINTR_RESET_EN;
 462     }
 463
 464     usb_drv_int_enable(true);
 465
 466     /* go go go */
 467     REG_USBCMD |= USBCMD_RUN;
 468
 469     logf("usb_drv_init() finished");
 470     logf("usb id %x", REG_ID);
 471     logf("usb dciversion %x", REG_DCIVERSION);
 472     logf("usb dccparams %x", REG_DCCPARAMS);
 473
 474     /* now a bus reset will occur. see bus_reset() */
 475     (void)attach;
 476 }
 477
 478 void usb_drv_init(void)
 479 {
 480     _usb_drv_init(false);
 481 }
 482
 483 /* fully enable driver */
 484 void usb_drv_attach(void)
 485 {
 486     sleep(HZ/10);
 487     _usb_drv_init(true);
 488 }
 489
 490 void usb_drv_exit(void)
 491 {
 492     usb_drv_stop();
 493
 494     /* TODO : is one of these needed to save power ?
 495     REG_PORTSC1 |= PORTSCX_PHY_LOW_POWER_SPD;
 496     REG_USBCMD |= USBCMD_CTRL_RESET;
 497     */
 498
 499     usb_drv_int_enable(false);
 500 }
 501
 502 void usb_drv_int(void)
 503 {
 504     unsigned int usbintr = REG_USBINTR; /* Only watch enabled ints */
 505     unsigned int status = REG_USBSTS & usbintr;
 506
 507 #if 0
 508     if (status & USBSTS_INT) logf("int: usb ioc");
 509     if (status & USBSTS_ERR) logf("int: usb err");
 510     if (status & USBSTS_PORT_CHANGE) logf("int: portchange");
 511     if (status & USBSTS_RESET) logf("int: reset");
 512 #endif
 513
 514     /* usb transaction interrupt */
 515     if (status & USBSTS_INT) {
 516         REG_USBSTS = USBSTS_INT;
 517
 518         /* a control packet? */
 519         if (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0) {
 520             control_received();
 521         }
 522
 523         if (REG_ENDPTCOMPLETE)
 524             transfer_completed();
 525     }
 526
 527     /* error interrupt */
 528     if (status & USBSTS_ERR) {
 529         REG_USBSTS = USBSTS_ERR;
 530         logf("usb error int");
 531     }
 532
 533     /* reset interrupt */
 534     if (status & USBSTS_RESET) {
 535         REG_USBSTS = USBSTS_RESET;
 536
 537         if (UNLIKELY(usbintr == USBINTR_RESET_EN)) {
 538             /* USB detected - detach and inform */
 539             usb_drv_stop();
 540             usb_drv_usb_detect_event();
 541         }
 542         else
 543         {
 544             bus_reset();
 545             usb_core_bus_reset(); /* tell mom */
 546         }
 547     }
 548
 549     /* port change */
 550     if (status & USBSTS_PORT_CHANGE) {
 551         REG_USBSTS = USBSTS_PORT_CHANGE;
 552     }
 553 }
 554
 555 bool usb_drv_stalled(int endpoint,bool in)
 556 {
 557     if(in) {
 558         return ((REG_ENDPTCTRL(endpoint&0x7f) & EPCTRL_TX_EP_STALL)!=0);
 559     }
 560     else {
 561         return ((REG_ENDPTCTRL(endpoint&0x7f) & EPCTRL_RX_EP_STALL)!=0);
 562     }
 563
 564 }
 565 void usb_drv_stall(int endpoint, bool stall,bool in)
 566 {
 567     logf("%sstall %d", stall?"":"un", endpoint&0x7f);
 568
 569     if(in) {
 570         if (stall) {
 571             REG_ENDPTCTRL(endpoint&0x7f) |= EPCTRL_TX_EP_STALL;
 572         }
 573         else {
 574             REG_ENDPTCTRL(endpoint&0x7f) &= ~EPCTRL_TX_EP_STALL;
 575         }
 576     }
 577     else {
 578         if (stall) {
 579             REG_ENDPTCTRL(endpoint) |= EPCTRL_RX_EP_STALL;
 580         }
 581         else {
 582             REG_ENDPTCTRL(endpoint) &= ~EPCTRL_RX_EP_STALL;
 583         }
 584     }
 585 }
 586
 587 int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
 588 {
 589     return prime_transfer(endpoint&0x7f, ptr, length, true, false);
 590 }
 591
 592 int usb_drv_send(int endpoint, void* ptr, int length)
 593 {
 594     return prime_transfer(endpoint&0x7f, ptr, length, true, true);
 595 }
 596
 597 int usb_drv_recv(int endpoint, void* ptr, int length)
 598 {
 599     //logf("usbrecv(%x, %d)", ptr, length);
 600     return prime_transfer(endpoint&0x7f, ptr, length, false, false);
 601 }
 602
 603 int usb_drv_port_speed(void)
 604 {
 605     return (REG_PORTSC1 & 0x08000000) ? 1 : 0;
 606 }
 607
 608 bool usb_drv_connected(void)
 609 {
 610     return (REG_PORTSC1 &
 611         (PORTSCX_PORT_SUSPEND | PORTSCX_CURRENT_CONNECT_STATUS))
 612             == PORTSCX_CURRENT_CONNECT_STATUS;
 613 }
 614
 615 bool usb_drv_powered(void)
 616 {
 617     /* true = bus 4V4 ok */
 618     return (REG_OTGSC & OTGSC_A_VBUS_VALID) ? true : false;
 619 }
 620
 621 void usb_drv_set_address(int address)
 622 {
 623     REG_DEVICEADDR = address << USBDEVICEADDRESS_BIT_POS;
 624     init_bulk_queue_heads();
 625     init_endpoints();
 626 }
 627
 628 void usb_drv_reset_endpoint(int endpoint, bool send)
 629 {
 630     int pipe = (endpoint&0x7f) * 2 + (send ? 1 : 0);
 631     unsigned int mask = pipe2mask[pipe];
 632     REG_ENDPTFLUSH = mask;
 633     while (REG_ENDPTFLUSH & mask);
 634 }
 635
 636 void usb_drv_set_test_mode(int mode)
 637 {
 638     switch(mode){
 639         case 0:
 640             REG_PORTSC1 &= ~PORTSCX_PORT_TEST_CTRL;
 641             break;
 642         case 1:
 643             REG_PORTSC1 |= PORTSCX_PTC_JSTATE;
 644             break;
 645         case 2:
 646             REG_PORTSC1 |= PORTSCX_PTC_KSTATE;
 647             break;
 648         case 3:
 649             REG_PORTSC1 |= PORTSCX_PTC_SE0NAK;
 650             break;
 651         case 4:
 652             REG_PORTSC1 |= PORTSCX_PTC_PACKET;
 653             break;
 654         case 5:
 655             REG_PORTSC1 |= PORTSCX_PTC_FORCE_EN;
 656             break;
 657     }
 658     usb_drv_reset();
 659     REG_USBCMD |= USBCMD_RUN;
 660 }
 661
 662 /*-------------------------------------------------------------------------*/
 663
 664 /* manual: 32.14.5.2 */
 665 static int prime_transfer(int endpoint, void* ptr, int len, bool send, bool wait)
 666 {
 667     int rc = 0;
 668     int pipe = endpoint * 2 + (send ? 1 : 0);
 669     unsigned int mask = pipe2mask[pipe];
 670     struct queue_head* qh = &qh_array[pipe];
 671     static long last_tick;
 672     struct transfer_descriptor* new_td,*cur_td,*prev_td;
 673
 674     int oldlevel = disable_irq_save();
 675 /*
 676     if (send && endpoint > EP_CONTROL) {
 677         logf("usb: sent %d bytes", len);
 678     }
 679 */
 680     qh->status = 0;
 681     qh->wait   = wait;
 682
 683     new_td=&td_array[pipe*NUM_TDS_PER_EP];
 684     cur_td=new_td;
 685     prev_td=0;
 686     int tdlen;
 687
 688     do
 689     {
 690         tdlen=MIN(len,16384);
 691         prepare_td(cur_td, prev_td, ptr, tdlen,pipe);
 692         ptr+=tdlen;
 693         prev_td=cur_td;
 694         cur_td++;
 695         len-=tdlen;
 696     }
 697     while(len>0 );
 698     //logf("starting ep %d %s",endpoint,send?"send":"receive");
 699
 700     qh->dtd.next_td_ptr = (unsigned int)new_td;
 701     qh->dtd.size_ioc_sts &= ~(QH_STATUS_HALT | QH_STATUS_ACTIVE);
 702
 703     REG_ENDPTPRIME |= mask;
 704
 705     if(endpoint == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
 706         /* 32.14.3.2.2 */
 707         logf("new setup arrived");
 708         rc = -4;
 709         goto pt_error;
 710     }
 711
 712     last_tick = current_tick;
 713     while ((REG_ENDPTPRIME & mask)) {
 714         if (REG_USBSTS & USBSTS_RESET) {
 715             rc = -1;
 716             goto pt_error;
 717         }
 718
 719         if (TIME_AFTER(current_tick, last_tick + HZ/4)) {
 720             logf("prime timeout");
 721             rc = -2;
 722             goto pt_error;
 723         }
 724     }
 725
 726     if (!(REG_ENDPTSTATUS & mask)) {
 727         logf("no prime! %d %d %x", endpoint, pipe, qh->dtd.size_ioc_sts & 0xff );
 728         rc = -3;
 729         goto pt_error;
 730     }
 731     if(endpoint == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
 732         /* 32.14.3.2.2 */
 733         logf("new setup arrived");
 734         rc = -4;
 735         goto pt_error;
 736     }
 737
 738     restore_irq(oldlevel);
 739
 740     if (wait) {
 741         /* wait for transfer to finish */
 742         wakeup_wait(&transfer_completion_signal[pipe], TIMEOUT_BLOCK);
 743         if(qh->status!=0) {
 744             /* No need to cancel wait here since it was done and the signal
 745              * came. */
 746             return -5;
 747         }
 748         //logf("all tds done");
 749     }
 750
 751 pt_error:
 752     if(rc<0)
 753         restore_irq(oldlevel);
 754
 755     /* Error status must make sure an abandoned wakeup signal isn't left */
 756     if (rc < 0 && wait) {
 757         /* Cancel wait */
 758         qh->wait = 0;
 759         /* Make sure to remove any signal if interrupt fired before we zeroed
 760          * qh->wait. Could happen during a bus reset for example. */
 761         wakeup_wait(&transfer_completion_signal[pipe], TIMEOUT_NOBLOCK);
 762     }
 763
 764     return rc;
 765 }
 766
 767 void usb_drv_cancel_all_transfers(void)
 768 {
 769     int i;
 770     REG_ENDPTFLUSH = ~0;
 771     while (REG_ENDPTFLUSH);
 772
 773     memset(td_array, 0, sizeof td_array);
 774     for(i=0;i<USB_NUM_ENDPOINTS*2;i++) {
 775         if(qh_array[i].wait) {
 776             qh_array[i].wait=0;
 777             qh_array[i].status=DTD_STATUS_HALTED;
 778             wakeup_signal(&transfer_completion_signal[i]);
 779         }
 780     }
 781 }
 782
 783 int usb_drv_request_endpoint(int dir)
 784 {
 785     int i, bit;
 786
 787     bit=(dir & USB_DIR_IN)? 2:1;
 788
 789     for (i=1; i < USB_NUM_ENDPOINTS; i++) {
 790         if((ep_allocation[i] & bit)!=0)
 791             continue;
 792         ep_allocation[i] |= bit;
 793         return i | dir;
 794     }
 795
 796     return -1;
 797 }
 798
 799 void usb_drv_release_endpoint(int ep)
 800 {
 801     int mask = (ep & USB_DIR_IN)? ~2:~1;
 802     ep_allocation[ep & 0x7f] &= mask;
 803 }
 804
 805
 806 static void prepare_td(struct transfer_descriptor* td,
 807                        struct transfer_descriptor* previous_td,
 808                        void *ptr, int len,int pipe)
 809 {
 810     //logf("adding a td : %d",len);
 811     memset(td, 0, sizeof(struct transfer_descriptor));
 812     td->next_td_ptr = DTD_NEXT_TERMINATE;
 813     td->size_ioc_sts = (len<< DTD_LENGTH_BIT_POS) |
 814         DTD_STATUS_ACTIVE | DTD_IOC;
 815     td->buff_ptr0 = (unsigned int)ptr;
 816     td->buff_ptr1 = ((unsigned int)ptr & 0xfffff000) + 0x1000;
 817     td->buff_ptr2 = ((unsigned int)ptr & 0xfffff000) + 0x2000;
 818     td->buff_ptr3 = ((unsigned int)ptr & 0xfffff000) + 0x3000;
 819     td->buff_ptr4 = ((unsigned int)ptr & 0xfffff000) + 0x4000;
 820     td->reserved |= DTD_RESERVED_LENGTH_MASK & len;
 821     td->reserved |= DTD_RESERVED_IN_USE;
 822     td->reserved |= (pipe << DTD_RESERVED_PIPE_OFFSET);
 823
 824     if (previous_td != 0) {
 825         previous_td->next_td_ptr=(unsigned int)td;
 826         previous_td->size_ioc_sts&=~DTD_IOC;
 827     }
 828 }
 829
 830 static void control_received(void)
 831 {
 832     int i;
 833     /* copy setup data from packet */
 834     static unsigned int tmp[2];
 835     tmp[0] = qh_array[0].setup_buffer[0];
 836     tmp[1] = qh_array[0].setup_buffer[1];
 837
 838     /* acknowledge packet recieved */
 839     REG_ENDPTSETUPSTAT = EPSETUP_STATUS_EP0;
 840
 841     /* Stop pending control transfers */
 842     for(i=0;i<2;i++) {
 843         if(qh_array[i].wait) {
 844             qh_array[i].wait=0;
 845             qh_array[i].status=DTD_STATUS_HALTED;
 846             wakeup_signal(&transfer_completion_signal[i]);
 847         }
 848     }
 849
 850     usb_core_control_request((struct usb_ctrlrequest*)tmp);
 851 }
 852
 853 static void transfer_completed(void)
 854 {
 855     int ep;
 856     unsigned int mask = REG_ENDPTCOMPLETE;
 857     REG_ENDPTCOMPLETE = mask;
 858
 859     for (ep=0; ep<USB_NUM_ENDPOINTS; ep++) {
 860         int dir;
 861         for (dir=0; dir<2; dir++) {
 862             int pipe = ep * 2 + dir;
 863             if (mask & pipe2mask[pipe]) {
 864                 struct queue_head* qh = &qh_array[pipe];
 865                 if(qh->wait) {
 866                     qh->wait=0;
 867                     wakeup_signal(&transfer_completion_signal[pipe]);
 868                 }
 869                 int length=0;
 870                 struct transfer_descriptor* td=&td_array[pipe*NUM_TDS_PER_EP];
 871                 while(td!=(struct transfer_descriptor*)DTD_NEXT_TERMINATE && td!=0)
 872                 {
 873                     length += ((td->reserved & DTD_RESERVED_LENGTH_MASK) -
 874                         ((td->size_ioc_sts & DTD_PACKET_SIZE) >> DTD_LENGTH_BIT_POS));
 875                     td=(struct transfer_descriptor*) td->next_td_ptr;
 876                 }
 877                 usb_core_transfer_complete(ep, dir?USB_DIR_IN:USB_DIR_OUT, qh->status, length);
 878             }
 879         }
 880     }
 881 }
 882
 883 /* manual: 32.14.2.1 Bus Reset */
 884 static void bus_reset(void)
 885 {
 886     int i;
 887     logf("usb bus_reset");
 888
 889     REG_DEVICEADDR = 0;
 890     REG_ENDPTSETUPSTAT = REG_ENDPTSETUPSTAT;
 891     REG_ENDPTCOMPLETE  = REG_ENDPTCOMPLETE;
 892
 893     for (i=0; i<100; i++) {
 894         if (!REG_ENDPTPRIME)
 895             break;
 896
 897         if (REG_USBSTS & USBSTS_RESET) {
 898             logf("usb: double reset");
 899             return;
 900         }
 901
 902         udelay(100);
 903     }
 904     if (REG_ENDPTPRIME) {
 905         logf("usb: short reset timeout");
 906     }
 907
 908     usb_drv_cancel_all_transfers();
 909
 910     if (!(REG_PORTSC1 & PORTSCX_PORT_RESET)) {
 911         logf("usb: slow reset!");
 912     }
 913 }
 914
 915 /* manual: 32.14.4.1 Queue Head Initialization */
 916 static void init_control_queue_heads(void)
 917 {
 918     memset(qh_array, 0, sizeof qh_array);
 919
 920     /*** control ***/
 921     qh_array[EP_CONTROL].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS | QH_IOS;
 922     qh_array[EP_CONTROL].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 923     qh_array[EP_CONTROL+1].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS;
 924     qh_array[EP_CONTROL+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 925 }
 926 /* manual: 32.14.4.1 Queue Head Initialization */
 927 static void init_bulk_queue_heads(void)
 928 {
 929     int tx_packetsize;
 930     int rx_packetsize;
 931     int i;
 932
 933     if (usb_drv_port_speed()) {
 934         rx_packetsize = 512;
 935         tx_packetsize = 512;
 936     }
 937     else {
 938         rx_packetsize = 64;
 939         tx_packetsize = 64;
 940     }
 941     /* TODO: this should take ep_allocation into account */
 942
 943     /*** bulk ***/
 944     for(i=1;i<USB_NUM_ENDPOINTS;i++) {
 945         qh_array[i*2].max_pkt_length = rx_packetsize << QH_MAX_PKT_LEN_POS | QH_ZLT_SEL;
 946         qh_array[i*2].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 947         qh_array[i*2+1].max_pkt_length = tx_packetsize << QH_MAX_PKT_LEN_POS | QH_ZLT_SEL;
 948         qh_array[i*2+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 949     }
 950 }
 951
 952 static void init_endpoints(void)
 953 {
 954     int i;
 955     /* TODO: this should take ep_allocation into account */
 956     /* bulk */
 957     for(i=1;i<USB_NUM_ENDPOINTS;i++) {
 958         REG_ENDPTCTRL(i) =
 959             EPCTRL_RX_DATA_TOGGLE_RST | EPCTRL_RX_ENABLE |
 960             EPCTRL_TX_DATA_TOGGLE_RST | EPCTRL_TX_ENABLE |
 961             (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT) |
 962             (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT);
 963     }
 964 }