firmware/target/coldfire/system-target.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Alan Korr
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef SYSTEM_TARGET_H
  22 #define SYSTEM_TARGET_H
  23
  24 #define nop \
  25     asm volatile ("trapf")
  26
  27 #define or_l(mask, address) \
  28   asm                       \
  29     ("or.l %0,(%1)"         \
  30      :                      \
  31      : /* %0 */ "d"(mask),  \
  32        /* %1 */ "a"(address))
  33
  34 #define and_l(mask, address) \
  35   asm                        \
  36     ("and.l %0,(%1)"         \
  37      :                       \
  38      : /* %0 */ "d"(mask),   \
  39        /* %1 */ "a"(address))
  40
  41 #define eor_l(mask, address) \
  42   asm                        \
  43     ("eor.l %0,(%1)"         \
  44      :                       \
  45      : /* %0 */ "d"(mask),   \
  46        /* %1 */ "a"(address))
  47
  48 #define add_l(addend, address) \
  49   asm                          \
  50     ("add.l %0, (%1)"          \
  51      :                         \
  52      : /* %0 */ "r"(addend),   \
  53        /* %1 */ "a"(address))
  54
  55 #define EMAC_ROUND      0x10
  56 #define EMAC_FRACTIONAL 0x20
  57 #define EMAC_UNSIGNED   0x40
  58 #define EMAC_SATURATE   0x80
  59
  60 static inline void coldfire_set_macsr(unsigned long flags)
  61 {
  62     asm volatile ("move.l %0, %%macsr" : : "i,r" (flags));
  63 }
  64
  65 static inline unsigned long coldfire_get_macsr(void)
  66 {
  67     unsigned long m;
  68
  69     asm volatile ("move.l %%macsr, %0" : "=r" (m));
  70     return m;
  71 }
  72
  73 /* ColdFire IRQ Levels/Priorities in Rockbox summary:
  74  * DMA0   - level 6, priority 0 (playback)
  75  * DMA1   - level 6, priority 1 (recording)
  76  * TIMER1 - level 4, priority 0 (timers)
  77  * TIMER0 - level 3, priority 0 (ticks)
  78  * GPI0   - level 3, priority 0 (pcf50606 PMU, secondary controller)
  79  */
  80 #define HIGHEST_IRQ_LEVEL   (5<<8) /* Disable all but DMA and higher */
  81 #define DMA_IRQ_LEVEL       (6<<8) /* Disable DMA and lower */
  82 #define DISABLE_INTERRUPTS  (7<<8) /* Disable all but NMIs */
  83 static inline int set_irq_level(int level)
  84 {
  85     int oldlevel;
  86     /* Read the old level and set the new one */
  87
  88     /* Not volatile - can be removed if oldlevel isn't used */
  89     asm          ("move.w %%sr, %0" : "=d"(oldlevel));
  90     /* Keep supervisor state set */
  91     asm volatile ("move.w %0, %%sr \n" : : "d"(level | 0x2000));
  92     return oldlevel;
  93 }
  94
  95 /* Enable all interrupts */
  96 static inline void enable_irq(void)
  97 {
  98     int tmp;
  99     /* Using move.w over the compiler's move.l saves 2 bytes per instance */
 100     asm volatile ("move.w %1, %0   \n"
 101                   "move.w %0, %%sr \n"
 102                   : "=&d"(tmp) : "i"(0x2000));
 103 }
 104
 105 /* Disable interrupts up to HIGHEST_IRQ_LEVEL */
 106 static inline void disable_irq(void)
 107 {
 108     int tmp;
 109     /* Using move.w over the compiler's move.l saves 2 bytes per instance */
 110     asm volatile ("move.w %1, %0   \n"
 111                   "move.w %0, %%sr \n"
 112                   : "=&d"(tmp)
 113                   : "i"(0x2000 | HIGHEST_IRQ_LEVEL));
 114 }
 115
 116 static inline int disable_irq_save(void)
 117 {
 118     int oldlevel, tmp;
 119     /* Using move.w over the compiler's move.l saves 2 bytes per instance */
 120     asm volatile ("move.w %%sr, %1 \n"
 121                   "move.w %2, %0   \n"
 122                   "move.w %0, %%sr \n"
 123                   : "=&d"(tmp), "=d"(oldlevel)
 124                   : "i"(0x2000 | HIGHEST_IRQ_LEVEL));
 125     return oldlevel;
 126 }
 127
 128 static inline void restore_irq(int oldlevel)
 129 {
 130     /* Restore the sr value returned by disable_irq_save or
 131      * set_irq_level */
 132     asm volatile ("move.w %0, %%sr" : : "d"(oldlevel));
 133 }
 134
 135 static inline uint16_t swap16(uint16_t value)
 136   /*
 137     result[15..8] = value[ 7..0];
 138     result[ 7..0] = value[15..8];
 139   */
 140 {
 141     return (value >> 8) | (value << 8);
 142 }
 143
 144 static inline uint32_t SWAW32(uint32_t value)
 145   /*
 146     result[31..16] = value[15.. 0];
 147     result[15.. 0] = value[31..16];
 148   */
 149 {
 150     asm ("swap    %%0" : "+r"(value));
 151     return value;
 152 }
 153
 154 static inline uint32_t swap32(uint32_t value)
 155   /*
 156     result[31..24] = value[ 7.. 0];
 157     result[23..16] = value[15.. 8];
 158     result[15.. 8] = value[23..16];
 159     result[ 7.. 0] = value[31..24];
 160   */
 161 {
 162     uint32_t mask = 0x00FF00FF;
 163     asm (                             /* val  = ABCD */
 164         "and.l   %[val],%[mask]  \n"  /* mask = .B.D */
 165         "eor.l   %[mask],%[val]  \n"  /* val  = A.C. */
 166         "lsl.l   #8,%[mask]      \n"  /* mask = B.D. */
 167         "lsr.l   #8,%[val]       \n"  /* val  = .A.C */
 168         "or.l    %[mask],%[val]  \n"  /* val  = BADC */
 169         "swap    %[val]          \n"  /* val  = DCBA */
 170         : /* outputs */
 171         [val] "+d"(value),
 172         [mask]"+d"(mask)
 173     );
 174     return value;
 175 }
 176
 177 static inline uint32_t swap_odd_even32(uint32_t value)
 178 {
 179     /*
 180       result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
 181       result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
 182     */
 183     uint32_t mask = 0x00FF00FF;
 184     asm (                             /* val  = ABCD */
 185         "and.l   %[val],%[mask]  \n"  /* mask = .B.D */
 186         "eor.l   %[mask],%[val]  \n"  /* val  = A.C. */
 187         "lsl.l   #8,%[mask]      \n"  /* mask = B.D. */
 188         "lsr.l   #8,%[val]       \n"  /* val  = .A.C */
 189         "or.l    %[mask],%[val]  \n"  /* val  = BADC */
 190         : /* outputs */
 191         [val] "+d"(value),
 192         [mask]"+d"(mask)
 193     );
 194     return value;
 195 }
 196
 197 #define HAVE_CPUCACHE_INVALIDATE
 198
 199 #define DEFAULT_PLLCR_AUDIO_BITS 0x10400000
 200 void coldfire_set_pllcr_audio_bits(long bits);
 201
 202 /* Set DATAINCONTROL without disturbing FIFO reset state */
 203 void coldfire_set_dataincontrol(unsigned long value);
 204
 205 #ifndef HAVE_ADJUSTABLE_CPU_FREQ
 206 extern void cf_set_cpu_frequency(long frequency);
 207 #endif
 208
 209 /* 11.2896 MHz */
 210 #define CPUFREQ_DEFAULT_MULT 1
 211 #define CPUFREQ_DEFAULT      (CPUFREQ_DEFAULT_MULT * CPU_FREQ)
 212 /* 45.1584 MHz */
 213 #define CPUFREQ_NORMAL_MULT  4
 214 #define CPUFREQ_NORMAL       (CPUFREQ_NORMAL_MULT * CPU_FREQ)
 215 /* 124.1856 MHz */
 216 #define CPUFREQ_MAX_MULT     11
 217 #define CPUFREQ_MAX          (CPUFREQ_MAX_MULT * CPU_FREQ)
 218
 219 #endif /* SYSTEM_TARGET_H */