firmware/target/coldfire/pcm-coldfire.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 by Michael Sevakis
  11  * Copyright (C) 2005 by Linus Nielsen Feltzing
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22 #include <stdlib.h>
  23 #include "system.h"
  24 #include "kernel.h"
  25 #include "logf.h"
  26 #include "audio.h"
  27 #include "sound.h"
  28 #if defined(HAVE_SPDIF_REC) || defined(HAVE_SPDIF_OUT)
  29 #include "spdif.h"
  30 #endif
  31
  32 #define IIS_PLAY_DEFPARM ( (freq_ent[FPARM_CLOCKSEL] << 12) | \
  33                            (IIS_PLAY & (7 << 8)) | \
  34                            (4 << 2) )  /* 64 bit clocks / word clock */
  35 #define IIS_FIFO_RESET   (1 << 11)
  36 #define PDIR2_FIFO_RESET (1 << 9)
  37
  38 #if defined(IAUDIO_X5) || defined(IAUDIO_M5) || defined(IAUDIO_M3)
  39 #define IIS_PLAY         IIS1CONFIG
  40 #else
  41 #define IIS_PLAY         IIS2CONFIG
  42 #endif
  43
  44 #ifdef HAVE_SPDIF_OUT
  45 /* EBU TX auto sync, PDIR2 fifo auto sync, IIS1 fifo auto sync */
  46 #define AUDIOGLOB_DEFPARM   ((1 << 10) | (1 << 8) | (1 << 7))
  47 #else
  48 /* PDIR2 fifo auto sync, IIS1 fifo auto sync */
  49 #define AUDIOGLOB_DEFPARM   ((1 << 8) | (1 << 7))
  50 #endif
  51
  52 /** Sample rates **/
  53 #define PLLCR_SET_AUDIO_BITS_DEFPARM \
  54             ((freq_ent[FPARM_CLSEL] << 28) | (1 << 22))
  55
  56 #define FPARM_CLOCKSEL       0
  57 #define FPARM_CLSEL          1
  58
  59 /* SCLK = Fs * bit clocks per word
  60  * so SCLK should be Fs * 64
  61  *
  62  * CLOCKSEL sets SCLK freq based on Audio CLK
  63  * 0x0c SCLK = Audio CLK/2   88200 * 64 = 5644800 Hz
  64  * 0x06 SCLK = Audio CLK/4   44100 * 64 = 2822400 Hz
  65  * 0x04 SCLK = Audio CLK/8   22050 * 64 = 1411200 Hz
  66  * 0x02 SCLK = Audio CLK/16  11025 * 64 = 705600 Hz
  67  *
  68  * CLSEL sets MCLK1/2 DAC freq based on XTAL freq
  69  * 0x01 MCLK1/2 = XTAL freq
  70  * 0x02 MCLK1/2 = XTAL/2 freq
  71  *
  72  * Audio CLK can be XTAL freq or XTAL/2 freq  (bit22 in PLLCR)
  73  * we always set bit22 so Audio CLK is always XTAL freq
  74  */
  75
  76 #if CONFIG_CPU == MCF5249 && defined(HAVE_UDA1380)
  77 static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
  78 {
  79     [HW_FREQ_88] = { 0x0c, 0x01 },
  80     [HW_FREQ_44] = { 0x06, 0x01 },
  81     [HW_FREQ_22] = { 0x04, 0x02 },
  82     [HW_FREQ_11] = { 0x02, 0x02 },
  83 };
  84 #endif
  85
  86 #if CONFIG_CPU == MCF5249 && defined(HAVE_WM8750)
  87 static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
  88 {
  89     [HW_FREQ_88] = { 0x0c, 0x01 },
  90     [HW_FREQ_44] = { 0x06, 0x01 },
  91     [HW_FREQ_22] = { 0x04, 0x01 },
  92     [HW_FREQ_11] = { 0x02, 0x01 },
  93 };
  94 #endif
  95
  96 #if (CONFIG_CPU == MCF5250 || CONFIG_CPU == MCF5249) && defined(HAVE_TLV320)
  97 static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
  98 {
  99     [HW_FREQ_88] = { 0x0c, 0x01 },
 100     [HW_FREQ_44] = { 0x06, 0x01 },
 101     [HW_FREQ_22] = { 0x04, 0x01 },
 102     [HW_FREQ_11] = { 0x02, 0x02 },
 103 };
 104 #endif
 105
 106 static const unsigned char *freq_ent;
 107
 108 /* Lock status struct for playback and recording */
 109 struct dma_lock
 110 {
 111     int locked;
 112     unsigned long state;
 113 };
 114
 115 static void iis_play_reset(void)
 116 {
 117     or_l(IIS_FIFO_RESET, &IIS_PLAY);
 118     and_l(~IIS_FIFO_RESET, &IIS_PLAY);
 119     PDOR3 = 0;
 120 }
 121
 122 static bool is_playback_monitoring(void)
 123 {
 124     return (IIS_PLAY & (7 << 8)) == (3 << 8);
 125 }
 126
 127 static void iis_play_reset_if_playback(bool if_playback)
 128 {
 129     int level = set_irq_level(DMA_IRQ_LEVEL);
 130     if (is_playback_monitoring() == if_playback)
 131         iis_play_reset();
 132     restore_irq(level);
 133 }
 134
 135 /* apply audio settings */
 136 /* This clears the reset bit to enable monitoring immediately if monitoring
 137    recording sources or always if playback is in progress - we might be
 138    switching samplerates on the fly */
 139 void pcm_dma_apply_settings(void)
 140 {
 141     int level = set_irq_level(DMA_IRQ_LEVEL);
 142
 143     /* remember table entry */
 144     freq_ent = pcm_freq_parms[pcm_fsel];
 145
 146     /* Reprogramming bits 15-12 requires FIFO to be in a reset
 147        condition - Users Manual 17-8, Note 11 */
 148     or_l(IIS_FIFO_RESET, &IIS_PLAY);
 149     /* Important for TLV320 - this must happen in the correct order
 150        or starting recording will sound absolutely awful once in
 151        awhile - audiohw_set_frequency then coldfire_set_pllcr_audio_bits
 152      */
 153     IIS_PLAY = IIS_PLAY_DEFPARM | IIS_FIFO_RESET;
 154     restore_irq(level);
 155
 156     audiohw_set_frequency(pcm_fsel);
 157     coldfire_set_pllcr_audio_bits(PLLCR_SET_AUDIO_BITS_DEFPARM);
 158
 159     level = set_irq_level(DMA_IRQ_LEVEL);
 160
 161     IIS_PLAY = IIS_PLAY_DEFPARM;
 162
 163     if ((DCR0 & DMA_EEXT) != 0 && is_playback_monitoring())
 164         PDOR3 = 0; /* Kick FIFO out of reset by writing to it */
 165
 166     restore_irq(level);
 167 } /* pcm_dma_apply_settings */
 168
 169 void pcm_play_dma_init(void)
 170 {
 171     freq_ent = pcm_freq_parms[pcm_fsel];
 172
 173     AUDIOGLOB = AUDIOGLOB_DEFPARM;
 174     DIVR0     = 54; /* DMA0 is mapped into vector 54 in system.c */
 175     and_l(0xffffff00, &DMAROUTE);
 176     or_l(DMA0_REQ_AUDIO_1, &DMAROUTE);
 177     DMACONFIG = 1;  /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
 178     BCR0 = 0; /* No bytes waiting */
 179     ICR6 = (6 << 2); /* Enable interrupt at level 6, priority 0 */
 180
 181     /* Setup Coldfire I2S before initializing hardware or changing
 182        other settings. */
 183     or_l(IIS_FIFO_RESET, &IIS_PLAY);
 184     IIS_PLAY = IIS_PLAY_DEFPARM | IIS_FIFO_RESET;
 185     audio_set_output_source(AUDIO_SRC_PLAYBACK);
 186
 187     /* Initialize default register values. */
 188     audiohw_init();
 189
 190     audio_input_mux(AUDIO_SRC_PLAYBACK, SRCF_PLAYBACK);
 191
 192     audiohw_set_frequency(pcm_fsel);
 193     coldfire_set_pllcr_audio_bits(PLLCR_SET_AUDIO_BITS_DEFPARM);
 194
 195 #if defined(HAVE_SPDIF_REC) || defined(HAVE_SPDIF_OUT)
 196     spdif_init();
 197 #endif
 198 } /* pcm_play_dma_init */
 199
 200 void pcm_postinit(void)
 201 {
 202     audiohw_postinit();
 203     iis_play_reset();
 204 }
 205
 206 /** DMA **/
 207
 208 /****************************************************************************
 209  ** Playback DMA transfer
 210  **/
 211 /* For the locks, DMA interrupt must be disabled when manipulating the lock
 212    if the handler ever calls these - right now things are arranged so it
 213    doesn't */
 214 static struct dma_lock dma_play_lock =
 215 {
 216     .locked = 0,
 217     .state = (0 << 14)  /* bit 14 is DMA0 */
 218 };
 219
 220 void pcm_play_lock(void)
 221 {
 222     if (++dma_play_lock.locked == 1)
 223         or_l((1 << 14), &IMR);
 224 }
 225
 226 void pcm_play_unlock(void)
 227 {
 228     if (--dma_play_lock.locked == 0)
 229         and_l(~dma_play_lock.state, &IMR);
 230 }
 231
 232 /* Set up the DMA transfer that kicks in when the audio FIFO gets empty */
 233 void pcm_play_dma_start(const void *addr, size_t size)
 234 {
 235     /* Stop any DMA in progress */
 236     pcm_play_dma_stop();
 237
 238     /* Set up DMA transfer  */
 239     SAR0 = (unsigned long)addr;   /* Source address      */
 240     DAR0 = (unsigned long)&PDOR3; /* Destination address */
 241     BCR0 = (unsigned long)size;   /* Bytes to transfer   */
 242
 243     DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | DMA_SINC |
 244            DMA_SSIZE(DMA_SIZE_LINE) | DMA_START;
 245
 246     dma_play_lock.state = (1 << 14);
 247 } /* pcm_play_dma_start */
 248
 249 /* Stops the DMA transfer and interrupt */
 250 void pcm_play_dma_stop(void)
 251 {
 252     and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
 253     BCR0 = 0; /* No bytes remaining */
 254     DSR0 = 1; /* Clear interrupt, errors, stop transfer */
 255
 256     iis_play_reset_if_playback(true);
 257
 258     dma_play_lock.state = (0 << 14);
 259 } /* pcm_play_dma_stop */
 260
 261 void pcm_play_dma_pause(bool pause)
 262 {
 263     if (pause)
 264     {
 265         /* pause playback on current buffer */
 266         and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
 267         DSR0 = 1;                            /* stop channel */
 268         iis_play_reset_if_playback(true);
 269         dma_play_lock.state = (0 << 14);
 270     }
 271     else
 272     {
 273         /* restart playback on current buffer */
 274         iis_play_reset_if_playback(true);
 275         or_l(DMA_INT | DMA_EEXT | DMA_START, &DCR0); /* everything ON */
 276         dma_play_lock.state = (1 << 14);
 277     }
 278 } /* pcm_play_dma_pause */
 279
 280 size_t pcm_get_bytes_waiting(void)
 281 {
 282     return BCR0 & 0xffffff;
 283 } /* pcm_get_bytes_waiting */
 284
 285 /* DMA0 Interrupt is called when the DMA has finished transfering a chunk
 286    from the caller's buffer */
 287 void DMA0(void) __attribute__ ((interrupt_handler, section(".icode")));
 288 void DMA0(void)
 289 {
 290     unsigned long res = DSR0;
 291     void *start;
 292     size_t size;
 293
 294     and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
 295     DSR0 = 1; /* Clear interrupt and errors */
 296
 297     if (res & 0x70)
 298     {
 299         logf("DMA0 err: %02x", res);
 300 #if 0
 301         logf("  SAR0: %08x", SAR0);
 302         logf("  DAR0: %08x", DAR0);
 303         logf("  BCR0: %08x", BCR0);
 304         logf("  DCR0: %08x", DCR0);
 305 #endif
 306     }
 307
 308     /* Force stop on error */
 309     pcm_play_get_more_callback((res & 0x70) ? NULL : &start, &size);
 310
 311     if (size != 0)
 312     {
 313         SAR0 = (unsigned long)start;     /* Source address */
 314         BCR0 = size;                     /* Bytes to transfer */
 315         or_l(DMA_EEXT | DMA_INT, &DCR0); /* per request and int ON */
 316     }
 317     /* else inished playing */
 318 } /* DMA0 */
 319
 320 const void * pcm_play_dma_get_peak_buffer(int *count)
 321 {
 322     unsigned long addr, cnt;
 323
 324     /* Make sure interrupt doesn't change the second value after we read the
 325      * first value. */
 326     int level = set_irq_level(DMA_IRQ_LEVEL);
 327     addr = SAR0;
 328     cnt = BCR0;
 329     restore_irq(level);
 330
 331     *count = (cnt & 0xffffff) >> 2;
 332     return (void *)((addr + 2) & ~3);
 333 } /* pcm_play_dma_get_peak_buffer */
 334
 335 #ifdef HAVE_RECORDING
 336 /****************************************************************************
 337  ** Recording DMA transfer
 338  **/
 339 static struct dma_lock dma_rec_lock =
 340 {
 341     .locked = 0,
 342     .state = (0 << 15)  /* bit 15 is DMA1 */
 343 };
 344
 345 /* For the locks, DMA interrupt must be disabled when manipulating the lock
 346    if the handler ever calls these - right now things are arranged so it
 347    doesn't */
 348 void pcm_rec_lock(void)
 349 {
 350     if (++dma_rec_lock.locked == 1)
 351         or_l((1 << 15), &IMR);
 352 }
 353
 354 void pcm_rec_unlock(void)
 355 {
 356     if (--dma_rec_lock.locked == 0)
 357         and_l(~dma_rec_lock.state, &IMR);
 358 }
 359
 360 void pcm_rec_dma_start(void *addr, size_t size)
 361 {
 362     /* stop any DMA in progress */
 363     pcm_rec_dma_stop();
 364
 365     and_l(~PDIR2_FIFO_RESET, &DATAINCONTROL);
 366
 367     /* Start the DMA transfer.. */
 368 #ifdef HAVE_SPDIF_REC
 369     /* clear: ebu1cnew, valnogood, symbolerr, parityerr */
 370     INTERRUPTCLEAR = (1 << 25) | (1 << 24) | (1 << 23) | (1 << 22);
 371 #endif
 372
 373     SAR1 = (unsigned long)&PDIR2; /* Source address      */
 374     DAR1 = (unsigned long)addr;   /* Destination address */
 375     BCR1 = (unsigned long)size;   /* Bytes to transfer   */
 376
 377     DCR1 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | DMA_DINC |
 378            DMA_DSIZE(DMA_SIZE_LINE) | DMA_START;
 379
 380     dma_rec_lock.state = (1 << 15);
 381 } /* pcm_rec_dma_start */
 382
 383 void pcm_rec_dma_stop(void)
 384 {
 385     and_l(~(DMA_EEXT | DMA_INT), &DCR1); /* per request and int OFF */
 386     DSR1 = 1; /* Clear interrupt, errors, stop transfer */
 387     BCR1 = 0; /* No bytes received */
 388
 389     or_l(PDIR2_FIFO_RESET, &DATAINCONTROL);
 390
 391     iis_play_reset_if_playback(false);
 392
 393     dma_rec_lock.state = (0 << 15);
 394 } /* pcm_rec_dma_stop */
 395
 396 void pcm_rec_dma_init(void)
 397 {
 398     DIVR1     = 55; /* DMA1 is mapped into vector 55 in system.c */
 399     DMACONFIG = 1;  /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
 400     and_l(0xffff00ff, &DMAROUTE);
 401     or_l(DMA1_REQ_AUDIO_2, &DMAROUTE);
 402
 403     pcm_rec_dma_stop();
 404
 405     /* Enable interrupt at level 6, priority 1 */
 406     ICR7 = (6 << 2) | (1 << 0);
 407 } /* pcm_init_recording */
 408
 409 void pcm_rec_dma_close(void)
 410 {
 411     pcm_rec_dma_stop();
 412
 413     and_l(0xffff00ff, &DMAROUTE);
 414     ICR7 = 0x00;     /* Disable interrupt */
 415     dma_rec_lock.state = (0 << 15);
 416 } /* pcm_rec_dma_close */
 417
 418 /* DMA1 Interrupt is called when the DMA has finished transfering a chunk
 419    into the caller's buffer */
 420 void DMA1(void) __attribute__ ((interrupt_handler, section(".icode")));
 421 void DMA1(void)
 422 {
 423     unsigned long res = DSR1;
 424     int status = 0;
 425     void *start;
 426     size_t size;
 427
 428     and_l(~(DMA_EEXT | DMA_INT), &DCR1); /* per request and int OFF */
 429     DSR1 = 1;                            /* Clear interrupt and errors */
 430
 431     if (res & 0x70)
 432     {
 433         status = DMA_REC_ERROR_DMA;
 434         logf("DMA1 err: %02x", res);
 435 #if 0
 436         logf("  SAR1: %08x", SAR1);
 437         logf("  DAR1: %08x", DAR1);
 438         logf("  BCR1: %08x", BCR1);
 439         logf("  DCR1: %08x", DCR1);
 440 #endif
 441     }
 442 #ifdef HAVE_SPDIF_REC
 443     else if (DATAINCONTROL == 0xc038 &&
 444         (INTERRUPTSTAT & ((1 << 23) | (1 << 22))))
 445     {
 446         /* reason: symbolerr, parityerr.
 447          * Ignore valnogood since several sources don't set it properly. */
 448         /* clear: ebu1cnew, symbolerr, parityerr */
 449         INTERRUPTCLEAR = (1 << 25) | (1 << 23) | (1 << 22);
 450         status = DMA_REC_ERROR_SPDIF;
 451         logf("spdif err");
 452     }
 453 #endif
 454
 455     /* Inform PCM we have more data (or error) */
 456     pcm_rec_more_ready_callback(status, &start, &size);
 457
 458     if (size != 0)
 459     {
 460         DAR1 = (unsigned long)start;     /* Destination address */
 461         BCR1 = (unsigned long)size;      /* Bytes to transfer */
 462         or_l(DMA_EEXT | DMA_INT, &DCR1); /* per request and int ON */
 463     }
 464 } /* DMA1 */
 465
 466 const void * pcm_rec_dma_get_peak_buffer(void)
 467 {
 468     return (void *)(DAR1 & ~3);
 469 } /* pcm_rec_dma_get_peak_buffer */
 470 #endif