firmware/export/isp1583.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 by Maurus Cuelenaere
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef ISP1583_H
  22 #define ISP1583_H
  23
  24 #include "usb-target.h"
  25
  26 #ifndef ISP1583_H_OVERRIDE
  27 /* Initialization registers */
  28 #define ISP1583_INIT_ADDRESS        (*((volatile unsigned char*)(ISP1583_IOBASE+0x0)))
  29 #define ISP1583_INIT_MODE           (*((volatile unsigned short*)(ISP1583_IOBASE+0xC)))
  30 #define ISP1583_INIT_INTCONF        (*((volatile unsigned char*)(ISP1583_IOBASE+0x10)))
  31 #define ISP1583_INIT_OTG            (*((volatile unsigned char*)(ISP1583_IOBASE+0x12)))
  32 #define ISP1583_INIT_INTEN_A        (*((volatile unsigned long*)(ISP1583_IOBASE+0x14)))
  33 #define ISP1583_INIT_INTEN_B
  34 #define ISP1583_INIT_INTEN_READ     ISP1583_INIT_INTEN_A
  35 /* Data Flow registers */
  36 #define ISP1583_DFLOW_EPINDEX       (*((volatile unsigned char*)(ISP1583_IOBASE+0xC2)))
  37 #define ISP1583_DFLOW_CTRLFUN       (*((volatile unsigned char*)(ISP1583_IOBASE+0x28)))
  38 #define ISP1583_DFLOW_DATA          (*((volatile unsigned short*)(ISP1583_IOBASE+0x20)))
  39 #define ISP1583_DFLOW_BUFLEN        (*((volatile unsigned short*)(ISP1583_IOBASE+0x1C)))
  40 #define ISP1583_DFLOW_BUFSTAT       (*((volatile unsigned char*)(ISP1583_IOBASE+0x1E)))
  41 #define ISP1583_DFLOW_MAXPKSZ       (*((volatile unsigned short*)(ISP1583_IOBASE+0x04)))
  42 #define ISP1583_DFLOW_EPTYPE        (*((volatile unsigned short*)(ISP1583_IOBASE+0x08)))
  43 /* DMA registers */
  44 #define ISP1583_DMA_ENDPOINT        (*((volatile unsigned char*)(ISP1583_IOBASE+0x58)))
  45 /* General registers */
  46 #define ISP1583_GEN_INT_A           (*((volatile unsigned long*)(ISP1583_IOBASE+0x18)))
  47 #define ISP1583_GEN_INT_B
  48 #define ISP1583_GEN_INT_READ        ISP1583_GEN_INT_A
  49 #define ISP1583_GEN_CHIPID          (*((volatile unsigned long*)(ISP1583_IOBASE+0x70))) /* Size=3 bytes */
  50 #define ISP1583_GEN_FRAMEN0         (*((volatile unsigned short*)(ISP1583_IOBASE+0x74)))
  51 #define ISP1583_GEN_SCRATCH         (*((volatile unsigned short*)(ISP1583_IOBASE+0x78)))
  52 #define ISP1583_GEN_UNLCKDEV        (*((volatile unsigned short*)(ISP1583_IOBASE+0x7C)))
  53 #define ISP1583_GEN_TSTMOD          (*((volatile unsigned char*)(ISP1583_IOBASE+0x84)))
  54
  55 #define set_int_value(a,b,value)    (a) = (value);
  56 #endif
  57
  58 #define ISP1583_UNLOCK_CODE         ((unsigned short)0xAA37)
  59
  60 /* Initialization registers' bits */
  61
  62 /* Initialization OTG register bits */
  63 #define INIT_OTG_BSESS_VALID        (1 << 4)
  64
  65 /* Initialization Mode register bits */
  66 #define INIT_MODE_TEST2             (1 << 15)
  67 #define INIT_MODE_TEST1             (1 << 14)
  68 #define INIT_MODE_TEST0             (1 << 13)
  69 #define INIT_MODE_DMA_CLKON         (1 << 9)
  70 #define INIT_MODE_VBUSSTAT          (1 << 8)
  71 #define INIT_MODE_CLKAON            (1 << 7)
  72 #define INIT_MODE_SNDRSU            (1 << 6)
  73 #define INIT_MODE_GOSUSP            (1 << 5)
  74 #define INIT_MODE_SFRESET           (1 << 4)
  75 #define INIT_MODE_GLINTENA          (1 << 3)
  76 #define INIT_MODE_WKUPCS            (1 << 2)
  77 #define INIT_MODE_PWRON             (1 << 1)
  78 #define INIT_MODE_SOFTCT            (1 << 0)
  79
  80 /* Initialization Interrupt Enable register bits */
  81 #define INIT_INTEN_IEP7TX           (1 << 25)
  82 #define INIT_INTEN_IEP7RX           (1 << 24)
  83 #define INIT_INTEN_IEP6TX           (1 << 23)
  84 #define INIT_INTEN_IEP6RX           (1 << 22)
  85 #define INIT_INTEN_IEP5TX           (1 << 21)
  86 #define INIT_INTEN_IEP5RX           (1 << 20)
  87 #define INIT_INTEN_IEP4TX           (1 << 19)
  88 #define INIT_INTEN_IEP4RX           (1 << 18)
  89 #define INIT_INTEN_IEP3TX           (1 << 17)
  90 #define INIT_INTEN_IEP3RX           (1 << 16)
  91 #define INIT_INTEN_IEP2TX           (1 << 15)
  92 #define INIT_INTEN_IEP2RX           (1 << 14)
  93 #define INIT_INTEN_IEP1TX           (1 << 13)
  94 #define INIT_INTEN_IEP1RX           (1 << 12)
  95 #define INIT_INTEN_IEP0TX           (1 << 11)
  96 #define INIT_INTEN_IEP0RX           (1 << 10)
  97 #define INIT_INTEN_IEP0SETUP        (1 << 8)
  98 #define INIT_INTEN_IEVBUS           (1 << 7)
  99 #define INIT_INTEN_IEDMA            (1 << 6)
 100 #define INIT_INTEN_IEHS_STA         (1 << 5)
 101 #define INIT_INTEN_IERESM           (1 << 4)
 102 #define INIT_INTEN_IESUSP           (1 << 3)
 103 #define INIT_INTEN_IEPSOF           (1 << 2)
 104 #define INIT_INTEN_IESOF            (1 << 1)
 105 #define INIT_INTEN_IEBRST           (1 << 0)
 106
 107 /* Initialization Interrupt Configuration register bits */
 108 #define INIT_INTCONF_INTLVL         (1 << 1)
 109 #define INIT_INTCONF_INTPOL         (1 << 0)
 110
 111 /* Initialization Address register bits */
 112 #define INIT_ADDRESS_DEVEN          (1 << 7)
 113
 114 /* Data Flow registers' bits */
 115
 116 /* Data Flow Endpoint Index register bits */
 117 #define DFLOW_EPINDEX_EP0SETUP      (1 << 5)
 118
 119 /* Data Flow Control Function register bits */
 120 #define DFLOW_CTRLFUN_CLBUF         (1 << 4)
 121 #define DFLOW_CTRLFUN_VENDP         (1 << 3)
 122 #define DFLOW_CTRLFUN_DSEN          (1 << 2)
 123 #define DFLOW_CTRLFUN_STATUS        (1 << 1)
 124 #define DFLOW_CTRLFUN_STALL         (1 << 0)
 125
 126 /* Data Flow Endpoint Type register bits */
 127 #define DFLOW_EPTYPE_NOEMPKT        (1 << 4)
 128 #define DFLOW_EPTYPE_ENABLE         (1 << 3)
 129 #define DFLOW_EPTYPE_DBLBUF         (1 << 2)
 130
 131 /* General registers' bits */
 132
 133 /* General Test Mode register bits */
 134 #define GEN_TSTMOD_FORCEHS          (1 << 7)
 135 #define GEN_TSTMOD_FORCEFS          (1 << 4)
 136 #define GEN_TSTMOD_PRBS             (1 << 3)
 137 #define GEN_TSTMOD_KSTATE           (1 << 2)
 138 #define GEN_TSTMOD_JSTATE           (1 << 1)
 139 #define GEN_TSTMOD_SE0_NAK          (1 << 0)
 140
 141 /* Interrupts */
 142 #define INT_IEP7TX                  (1 << 25)
 143 #define INT_IEP7RX                  (1 << 24)
 144 #define INT_IEP6TX                  (1 << 23)
 145 #define INT_IEP6RX                  (1 << 22)
 146 #define INT_IEP5TX                  (1 << 21)
 147 #define INT_IEP5RX                  (1 << 20)
 148 #define INT_IEP4TX                  (1 << 19)
 149 #define INT_IEP4RX                  (1 << 18)
 150 #define INT_IEP3TX                  (1 << 17)
 151 #define INT_IEP3RX                  (1 << 16)
 152 #define INT_IEP2TX                  (1 << 15)
 153 #define INT_IEP2RX                  (1 << 14)
 154 #define INT_IEP1TX                  (1 << 13)
 155 #define INT_IEP1RX                  (1 << 12)
 156 #define INT_IEP0TX                  (1 << 11)
 157 #define INT_IEP0RX                  (1 << 10)
 158 #define INT_IEP0SETUP               (1 << 8)
 159 #define INT_IEVBUS                  (1 << 7)
 160 #define INT_IEDMA                   (1 << 6)
 161 #define INT_IEHS_STA                (1 << 5)
 162 #define INT_IERESM                  (1 << 4)
 163 #define INT_IESUSP                  (1 << 3)
 164 #define INT_IEPSOF                  (1 << 2)
 165 #define INT_IESOF                   (1 << 1)
 166 #define INT_IEBRST                  (1 << 0)
 167
 168 #define INT_EP_MASK                 ( INT_IEP0RX | INT_IEP0TX | INT_IEP1RX | INT_IEP1TX | INT_IEP2RX | INT_IEP2TX | INT_IEP3RX | INT_IEP3TX | INT_IEP4RX | INT_IEP4TX | INT_IEP5RX | INT_IEP5TX | INT_IEP6RX | INT_IEP6TX | INT_IEP7RX | INT_IEP7TX )
 169
 170 #define STANDARD_INTEN              ( INIT_INTEN_IEBRST | INIT_INTEN_IEHS_STA | INT_IESUSP | INT_IERESM | INIT_INTEN_IEVBUS | INIT_INTEN_IEP0SETUP | INIT_INTEN_IEP0RX | INIT_INTEN_IEP0TX )
 171 #define STANDARD_INIT_MODE          ( INIT_MODE_CLKAON | INIT_MODE_GLINTENA )
 172
 173 #ifdef USE_IRAM
 174  #define IRAM_ATTR __attribute__ ((section(".icode")))
 175 #else
 176  #define IRAM_ATTR
 177 #endif
 178
 179 #include "usb_drv.h"
 180
 181 #endif