firmware/export/i2c-coldfire.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Linus Nielsen Feltzing
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 /*
  23  *  Driver for MCF52xx's I2C interface
  24  *  2005-02-17 hubble@mochine.com
  25  *
  26  */
  27
  28 #ifndef _I2C_COLDFIRE_H
  29 #define _I2C_COLDFIRE_H
  30
  31 #include "cpu.h"
  32
  33 void i2c_init(void);
  34 int i2c_read (volatile unsigned char *iface, unsigned char addr,
  35               unsigned char *buf, int count);
  36 int i2c_write(volatile unsigned char *iface, unsigned char addr,
  37               const unsigned char *buf, int count);
  38 void i2c_close(void);
  39 void i2c_adjust_prescale(int multiplier);
  40
  41 #define I2C_IFACE_0  ((volatile unsigned char *)&MADR)
  42 #define I2C_IFACE_1  ((volatile unsigned char *)&MADR2)
  43
  44 #define MAX_LOOP    0x100     /* TODO: select a better value */
  45
  46 /* PLLCR control */
  47 #define QSPISEL (1 << 11)       /* Selects QSPI or I2C interface */
  48
  49 /* Offsets to I2C registers from base address */
  50 #define O_MADR  0x00            /* Slave Address        */
  51 #define O_MFDR  0x04            /* Frequency divider    */
  52 #define O_MBCR  0x08            /* Control register     */
  53 #define O_MBSR  0x0c            /* Status register      */
  54 #define O_MBDR  0x10            /* Data register        */
  55
  56 /* MBSR - Status register */
  57 #define ICF     (1 << 7)        /* Transfer Complete    */
  58 #define IAAS    (1 << 6)        /* Addressed As Alave   */
  59 #define IBB     (1 << 5)        /* Bus Busy             */
  60 #define IAL     (1 << 4)        /* Arbitration Lost     */
  61 #define SRW     (1 << 2)        /* Slave R/W            */
  62 #define IIF     (1 << 1)        /* I2C Interrupt        */
  63 #define RXAK    (1 << 0)        /* No Ack bit           */
  64
  65 /* MBCR - Control register */
  66 #define IEN     (1 << 7)        /* I2C Enable           */
  67 #define IIEN    (1 << 6)        /* Interrupt Enable     */
  68 #define MSTA    (1 << 5)        /* Master/Slave select  */
  69 #define MTX     (1 << 4)        /* Transmit/Receive     */
  70 #define TXAK    (1 << 3)        /* Transfer ACK         */
  71 #define RSTA    (1 << 2)        /* Restart..            */
  72
  73
  74 #endif