firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "hotswap.h"
  27 #include "system.h"
  28 #include "kernel.h"
  29 #include "cpu.h"
  30 #include <stdio.h>
  31 #include <stdlib.h>
  32 #include <string.h>
  33 #include "as3525v2.h"
  34 #include "pl081.h"  /* DMA controller */
  35 #include "dma-target.h" /* DMA request lines */
  36 #include "clock-target.h"
  37 #include "panic.h"
  38 #include "stdbool.h"
  39 #include "ata_idle_notify.h"
  40 #include "sd.h"
  41
  42 #include "lcd.h"
  43 #include <stdarg.h>
  44 #include "sysfont.h"
  45
  46 /* debug helper */
  47 static int line = 0;
  48 static void printf(const char *format, ...)
  49 {
  50     char buf[50];
  51     int len;
  52     va_list ap;
  53     va_start(ap, format);
  54
  55     len = vsnprintf(buf, sizeof(buf), format, ap);
  56     va_end(ap);
  57
  58     lcd_puts(0, line++, buf);
  59     lcd_update();
  60     if(line >= LCD_HEIGHT/SYSFONT_HEIGHT)
  61         line = 0;
  62 }
  63
  64 /* command flags */
  65 #define MCI_NO_RESP     (0<<0)
  66 #define MCI_RESP        (1<<0)
  67 #define MCI_LONG_RESP   (1<<1)
  68
  69 /* controller registers */
  70 #define SD_BASE 0xC6070000
  71
  72 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  73
  74 #define MCI_CTRL        SD_REG(0x00)
  75
  76 /* control bits */
  77 #define CTRL_RESET      (1<<0)
  78 #define FIFO_RESET      (1<<1)
  79 #define DMA_RESET       (1<<2)
  80 #define INT_ENABLE      (1<<4)
  81 #define DMA_ENABLE      (1<<5)
  82 #define READ_WAIT       (1<<6)
  83 #define SEND_IRQ_RESP   (1<<7)
  84 #define ABRT_READ_DATA  (1<<8)
  85 #define SEND_CCSD       (1<<9)
  86 #define SEND_AS_CCSD    (1<<10)
  87 #define EN_OD_PULLUP    (1<<24)
  88
  89
  90 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  91 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  92 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
  93 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
  94 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
  95
  96 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
  97                                         /* 1 bit per card, set = wide bus */
  98
  99 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size */
 100 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count */
 101 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
 102
 103 #define MCI_ARGUMENT    SD_REG(0x28)
 104 #define MCI_COMMAND     SD_REG(0x2C)
 105
 106 /* command bits (bits 5:0 are the command index) */
 107 #define CMD_RESP_EXP_BIT        (1<<6)
 108 #define CMD_RESP_LENGTH_BIT     (1<<7)
 109 #define CMD_CHECK_CRC_BIT       (1<<8)
 110 #define CMD_DATA_EXP_BIT        (1<<9)
 111 #define CMD_RW_BIT              (1<<10)
 112 #define CMD_TRANSMODE_BIT       (1<<11)
 113 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
 114 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
 115 #define CMD_ABRT_CMD_BIT        (1<<14)
 116 #define CMD_SEND_INIT_BIT       (1<<15)
 117 #define CMD_SEND_CLK_ONLY       (1<<21)
 118 #define CMD_READ_CEATA          (1<<22)
 119 #define CMD_CCS_EXPECTED        (1<<23)
 120 #define CMD_DONE_BIT            (1<<31)
 121
 122
 123 #define MCI_RESP0       SD_REG(0x30)
 124 #define MCI_RESP1       SD_REG(0x34)
 125 #define MCI_RESP2       SD_REG(0x38)
 126 #define MCI_RESP3       SD_REG(0x3C)
 127
 128 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 129 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 130                                          * status clear */
 131 #define MCI_STATUS      SD_REG(0x48)
 132
 133 /*
 134  *  STATUS register
 135  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 136  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 137  *  & 8         = MCI_INT_DTO
 138  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 139  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 140  */
 141
 142 /* interrupt bits */
 143 #define MCI_INT_CRDDET  (1<<0)      /* card detect */
 144 #define MCI_INT_RE      (1<<1)      /* response error */
 145 #define MCI_INT_CD      (1<<2)      /* command done */
 146 #define MCI_INT_DTO     (1<<3)      /* data transfer over */
 147 #define MCI_INT_TXDR    (1<<4)      /* tx fifo data request */
 148 #define MCI_INT_RXDR    (1<<5)      /* rx fifo data request */
 149 #define MCI_INT_RCRC    (1<<6)      /* response crc error */
 150 #define MCI_INT_DCRC    (1<<7)      /* data crc error */
 151 #define MCI_INT_RTO     (1<<8)      /* response timeout */
 152 #define MCI_INT_DRTO    (1<<9)      /* data read timeout */
 153 #define MCI_INT_HTO     (1<<10)     /* data starv timeout */
 154 #define MCI_INT_FRUN    (1<<11)     /* fifo over/underrun */
 155 #define MCI_INT_HLE     (1<<12)     /* hw locked while error */
 156 #define MCI_INT_SBE     (1<<13)     /* start bit error */
 157 #define MCI_INT_ACD     (1<<14)     /* auto command done */
 158 #define MCI_INT_EBE     (1<<15)     /* end bit error */
 159 #define MCI_INT_SDIO    (0xf<<16)
 160
 161 #define MCI_ERROR   (MCI_INT_RE | MCI_INT_RCRC | MCI_INT_DCRC | MCI_INT_RTO \
 162                    | MCI_INT_DRTO | MCI_INT_HTO | MCI_INT_FRUN | MCI_INT_HLE \
 163                    | MCI_INT_SBE | MCI_INT_EBE)
 164
 165 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 166 /* TX watermark :    bits 11:0
 167  * RX watermark :    bits 27:16
 168  * DMA MTRANS SIZE : bits 30:28
 169  * bits 31, 15:12 : unused
 170  */
 171 #define MCI_FIFOTH_MASK 0x8000f000
 172
 173 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 174 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 175 #define MCI_GPIO        SD_REG(0x58)
 176 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count */
 177 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes */
 178 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce */
 179 #define MCI_USRID       SD_REG(0x68)    /* user id */
 180 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 181
 182 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 183 /* bit 0 : card type
 184  * bits 5:1 : maximum card index */
 185
 186 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 187 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 188 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 189 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 190 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 191 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 192 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 193
 194 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 195
 196 static int sd_init_card(void);
 197 static void init_controller(void);
 198
 199 static tCardInfo card_info;
 200
 201 /* for compatibility */
 202 static long last_disk_activity = -1;
 203
 204 #define MIN_YIELD_PERIOD 5  /* ticks */
 205 static long next_yield = 0;
 206
 207 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 208 static const char         sd_thread_name[] = "ata/sd";
 209 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 210 static struct event_queue sd_queue;
 211 #ifndef BOOTLOADER
 212 static bool sd_enabled = false;
 213 #endif
 214
 215 static struct wakeup transfer_completion_signal;
 216 static volatile bool retry;
 217
 218 static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
 219
 220 void INT_NAND(void)
 221 {
 222     MCI_CTRL &= ~INT_ENABLE;
 223     const int status = MCI_MASK_STATUS;
 224
 225     MCI_RAW_STATUS = status;    /* clear status */
 226
 227     if(status & MCI_ERROR)
 228         retry = true;
 229     else if(status & MCI_INT_DTO)
 230         wakeup_signal(&transfer_completion_signal);
 231
 232     MCI_CTRL |= INT_ENABLE;
 233 }
 234
 235 static bool send_cmd(const int cmd, const int arg, const int flags,
 236         unsigned long *response)
 237 {
 238     int val;
 239     val = cmd | CMD_DONE_BIT;
 240     if(flags & MCI_RESP)
 241     {
 242         val |= CMD_RESP_EXP_BIT;
 243         if(flags & MCI_LONG_RESP)
 244             val |= CMD_RESP_LENGTH_BIT;
 245     }
 246
 247     if(cmd == SD_READ_MULTIPLE_BLOCK || cmd == SD_WRITE_MULTIPLE_BLOCK)
 248     {
 249         val |= CMD_WAIT_PRV_DAT_BIT | CMD_DATA_EXP_BIT;
 250         if(cmd == SD_WRITE_MULTIPLE_BLOCK)
 251             val |= CMD_RW_BIT | CMD_CHECK_CRC_BIT;
 252     }
 253
 254     int tmp = MCI_CLKENA;
 255     MCI_CLKENA = 0;
 256
 257     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 258     MCI_ARGUMENT = 0;
 259     int max = 10;
 260     while(max-- && MCI_COMMAND & CMD_DONE_BIT);
 261
 262     MCI_CLKDIV &= ~0xff;
 263     MCI_CLKDIV |= 0;
 264
 265     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 266     MCI_ARGUMENT = 0;
 267     max = 10;
 268     while(max-- && MCI_COMMAND & CMD_DONE_BIT);
 269
 270     MCI_CLKENA = tmp;
 271
 272     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 273     MCI_ARGUMENT = 0;
 274     max = 10;
 275     while(max-- && MCI_COMMAND & CMD_DONE_BIT);
 276
 277     mci_delay();
 278
 279     MCI_ARGUMENT = arg;
 280     MCI_COMMAND = val;
 281
 282     MCI_CTRL |= INT_ENABLE;
 283
 284     max = 1000;
 285     while(max-- && MCI_COMMAND & CMD_DONE_BIT); /* wait for cmd completion */
 286     if(!max)
 287         return false;
 288
 289     if(flags & MCI_RESP)
 290     {
 291         if(flags & MCI_LONG_RESP)
 292         {
 293             /* store the response in little endian order for the words */
 294             response[0] = MCI_RESP3;
 295             response[1] = MCI_RESP2;
 296             response[2] = MCI_RESP1;
 297             response[3] = MCI_RESP0;
 298         }
 299         else
 300             response[0] = MCI_RESP0;
 301     }
 302     return true;
 303 }
 304
 305 static int sd_init_card(void)
 306 {
 307     unsigned long response;
 308     unsigned long temp_reg[4];
 309     int max_tries = 100; /* max acmd41 attemps */
 310     bool sdhc;
 311     int i;
 312
 313     if(!send_cmd(SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 314         return -1;
 315
 316     mci_delay();
 317
 318     sdhc = false;
 319     if(send_cmd(SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 320         if((response & 0xFFF) == 0x1AA)
 321             sdhc = true;
 322
 323     do {
 324         /* some MicroSD cards seems to need more delays, so play safe */
 325         mci_delay();
 326         mci_delay();
 327         mci_delay();
 328
 329         /* app_cmd */
 330         if( !send_cmd(SD_APP_CMD, 0, MCI_RESP, &response) /*||
 331             !(response & (1<<5))*/ )
 332         {
 333             return -2;
 334         }
 335
 336         /* acmd41 */
 337         if(!send_cmd(SD_APP_OP_COND, (sdhc ? 0x40FF8000 : (1<<23)),
 338                         MCI_RESP, &card_info.ocr))
 339             return -3;
 340     } while(!(card_info.ocr & (1<<31)) && max_tries--);
 341
 342     if(max_tries < 0)
 343         return -4;
 344
 345     mci_delay();
 346     mci_delay();
 347     mci_delay();
 348
 349     /* send CID */
 350     if(!send_cmd(SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info.cid))
 351         return -5;
 352
 353     /* send RCA */
 354     if(!send_cmd(SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info.rca))
 355         return -6;
 356
 357     /* send CSD */
 358     if(!send_cmd(SD_SEND_CSD, card_info.rca,
 359                  MCI_RESP|MCI_LONG_RESP, temp_reg))
 360         return -7;
 361
 362     for(i=0; i<4; i++)
 363         card_info.csd[3-i] = temp_reg[i];
 364
 365     sd_parse_csd(&card_info);
 366
 367     if(!send_cmd(SD_APP_CMD, 0, MCI_RESP, &response) ||
 368        !send_cmd(42, 0, MCI_NO_RESP, NULL)) /* disconnect the 50 KOhm pull-up
 369                                                resistor on CD/DAT3 */
 370         return -13;
 371
 372     if(!send_cmd(SD_APP_CMD, card_info.rca, MCI_NO_RESP, NULL))
 373         return -10;
 374
 375     if(!send_cmd(SD_SET_BUS_WIDTH, card_info.rca | 2, MCI_NO_RESP, NULL))
 376         return -11;
 377
 378     MCI_CTYPE = (1<<0); /* Bus width = 4 */
 379
 380     if(!send_cmd(SD_SELECT_CARD, card_info.rca, MCI_NO_RESP, NULL))
 381         return -9;
 382
 383     /* not sent in init_card() by OF */
 384     if(!send_cmd(SD_SET_BLOCKLEN, card_info.blocksize, MCI_NO_RESP,
 385                  NULL))
 386         return -12;
 387
 388     card_info.initialized = 1;
 389
 390     return 0;
 391 }
 392
 393 static void sd_thread(void) __attribute__((noreturn));
 394 static void sd_thread(void)
 395 {
 396     struct queue_event ev;
 397     bool idle_notified = false;
 398
 399     while (1)
 400     {
 401         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 402
 403         switch ( ev.id )
 404         {
 405         case SYS_TIMEOUT:
 406             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 407             {
 408                 idle_notified = false;
 409             }
 410             else
 411             {
 412                 /* never let a timer wrap confuse us */
 413                 next_yield = current_tick;
 414
 415                 if (!idle_notified)
 416                 {
 417                     call_storage_idle_notifys(false);
 418                     idle_notified = true;
 419                 }
 420             }
 421             break;
 422 #if 0
 423         case SYS_USB_CONNECTED:
 424             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 425             /* Wait until the USB cable is extracted again */
 426             usb_wait_for_disconnect(&sd_queue);
 427
 428             break;
 429         case SYS_USB_DISCONNECTED:
 430             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 431             break;
 432 #endif
 433         }
 434     }
 435 }
 436
 437 static void init_controller(void)
 438 {
 439     int idx = (MCI_HCON >> 1) & 31;
 440     int idx_bits = (1 << idx) -1;
 441
 442     MCI_PWREN &= ~idx_bits;
 443     MCI_PWREN = idx_bits;
 444
 445     mci_delay();
 446
 447     MCI_CTRL |= CTRL_RESET;     /* FIXME: FIFO & DMA reset? */
 448     while(MCI_CTRL & CTRL_RESET)
 449         ;
 450
 451     MCI_RAW_STATUS = 0xffffffff;
 452
 453     MCI_CTRL |= INT_ENABLE;
 454     MCI_TMOUT = 0xffffffff;
 455
 456     MCI_CTYPE = 0;
 457
 458     MCI_CLKENA = idx_bits;
 459
 460     MCI_ARGUMENT = 0;
 461     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 462     int max = 10;
 463     while(max-- && (MCI_COMMAND & CMD_DONE_BIT)) ;
 464
 465     MCI_DEBNCE = 0xfffff;   /* default value */
 466
 467     MCI_FIFOTH &= MCI_FIFOTH_MASK;
 468     MCI_FIFOTH |= 0x503f0080;
 469
 470     MCI_MASK = 0xffffffff & ~(MCI_INT_ACD|MCI_INT_CRDDET);
 471 }
 472
 473 int sd_init(void)
 474 {
 475     int ret;
 476     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 477
 478     CGU_IDE =   (1<<7)  /* AHB interface enable */  |
 479                 (1<<6)  /* interface enable */      |
 480                 ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) << 2) |
 481                 1;       /* clock source = PLLA */
 482
 483     CGU_MEMSTICK = (1<<8) | (1<<7) |
 484         (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) | 1;
 485
 486     /* ?? */
 487     *(volatile int*)(CGU_BASE+0x3C) = (1<<7) |
 488         (CLK_DIV(AS3525_PLLA_FREQ, 24000000) -1) | 1;
 489
 490     wakeup_init(&transfer_completion_signal);
 491
 492     VIC_INT_ENABLE |= INTERRUPT_NAND;
 493
 494     init_controller();
 495     ret = sd_init_card();
 496     if(ret < 0)
 497         return ret;
 498
 499     /* init mutex */
 500     mutex_init(&sd_mtx);
 501
 502     queue_init(&sd_queue, true);
 503     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 504             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 505
 506 #ifndef BOOTLOADER
 507     sd_enabled = true;
 508     sd_enable(false);
 509 #endif
 510     return 0;
 511 }
 512
 513 #ifdef STORAGE_GET_INFO
 514 void sd_get_info(struct storage_info *info)
 515 {
 516     info->sector_size=card_info.blocksize;
 517     info->num_sectors=card_info.numblocks;
 518     info->vendor="Rockbox";
 519     info->product = "Internal Storage";
 520     info->revision="0.00";
 521 }
 522 #endif
 523
 524 static int sd_wait_for_state(unsigned int state)
 525 {
 526     unsigned long response;
 527     unsigned int timeout = 100; /* ticks */
 528     long t = current_tick;
 529
 530     while (1)
 531     {
 532         long tick;
 533
 534         if(!send_cmd(SD_SEND_STATUS, card_info.rca,
 535                     MCI_RESP, &response))
 536             return -1;
 537
 538         if (((response >> 9) & 0xf) == state)
 539             return 0;
 540
 541         if(TIME_AFTER(current_tick, t + timeout))
 542             return -10 * ((response >> 9) & 0xf);
 543
 544         if (TIME_AFTER((tick = current_tick), next_yield))
 545         {
 546             yield();
 547             timeout += current_tick - tick;
 548             next_yield = tick + MIN_YIELD_PERIOD;
 549         }
 550     }
 551 }
 552
 553 static int sd_transfer_sectors(unsigned long start, int count, void* buf, bool write)
 554 {
 555 #if 1
 556     /* This is debug code, not functional yet */
 557     line = 0;
 558     lcd_clear_display();
 559     printf("Entering SD transfer");
 560     printf("THIS IS DEBUG CODE !");
 561     printf("");
 562     printf("All your controllers");
 563     printf("are belong to us.");
 564     volatile int delay = 0x500000;
 565     while(delay--) ;
 566     line = 0;
 567     lcd_clear_display();
 568 #endif /* debug warning */
 569
 570     int ret = 0;
 571
 572     if((int)buf & 3)
 573         panicf("unaligned transfer");
 574
 575     /* skip SanDisk OF */
 576     start += 0xf000;
 577
 578     mutex_lock(&sd_mtx);
 579 #ifndef BOOTLOADER
 580     sd_enable(true);
 581 #endif
 582
 583     if (card_info.initialized <= 0)
 584     {
 585         ret = sd_init_card();
 586         if (!(card_info.initialized))
 587         {
 588             panicf("card not initialised (%d)", ret);
 589             goto sd_transfer_error;
 590         }
 591     }
 592
 593     last_disk_activity = current_tick;
 594     ret = sd_wait_for_state(SD_TRAN);
 595     if (ret < 0)
 596     {
 597         static const char *st[9] = {
 598             "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV", "PRG", "DIS"
 599         };
 600         if(ret <= -10)
 601             panicf("wait for state failed (%s)", st[(-ret / 10) % 9]);
 602         else
 603             panicf("wait for state failed");
 604         goto sd_transfer_error;
 605     }
 606
 607     dma_retain();
 608
 609     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 610
 611     /* Interrupt handler might set this to true during transfer */
 612     retry = false;
 613
 614     do
 615     {
 616         MCI_BLKSIZ = 512;
 617         MCI_BYTCNT = count * 512;
 618
 619         MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 620         while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 621             ;
 622
 623         MCI_CTRL |= DMA_ENABLE;
 624         MCI_MASK = MCI_INT_CD|MCI_INT_DTO|MCI_INT_DCRC|MCI_INT_DRTO| \
 625             MCI_INT_HTO|MCI_INT_FRUN|MCI_INT_HLE|MCI_INT_SBE|MCI_INT_EBE;
 626
 627         MCI_FIFOTH &= MCI_FIFOTH_MASK;
 628         MCI_FIFOTH |= 0x503f0080;
 629
 630
 631         if(card_info.ocr & (1<<30) ) /* SDHC */
 632             ret = send_cmd(cmd, start, MCI_NO_RESP, NULL);
 633         else
 634             ret = send_cmd(cmd, start * SD_BLOCK_SIZE,
 635                     MCI_NO_RESP, NULL);
 636
 637         if (ret < 0)
 638             panicf("transfer multiple blocks failed (%d)", ret);
 639
 640         if(write)
 641             dma_enable_channel(0, buf, MCI_FIFO, DMA_PERI_SD,
 642                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 643         else
 644             dma_enable_channel(0, MCI_FIFO, buf, DMA_PERI_SD,
 645                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 646
 647         line = 0;
 648         lcd_clear_display();
 649         printf("dma ->");
 650
 651         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 652
 653         printf("dma <-");
 654         int delay = 0x1000000; while(delay--) ;
 655
 656         last_disk_activity = current_tick;
 657
 658         if(!send_cmd(SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
 659         {
 660             ret = -666;
 661             panicf("STOP TRANSMISSION failed");
 662             goto sd_transfer_error;
 663         }
 664
 665         ret = sd_wait_for_state(SD_TRAN);
 666         if (ret < 0)
 667         {
 668             panicf(" wait for state TRAN failed (%d)", ret);
 669             goto sd_transfer_error;
 670         }
 671     } while(retry);
 672
 673     dma_release();
 674
 675 #ifndef BOOTLOADER
 676     sd_enable(false);
 677 #endif
 678     mutex_unlock(&sd_mtx);
 679     return 0;
 680
 681 sd_transfer_error:
 682     panicf("transfer error : %d",ret);
 683     card_info.initialized = 0;
 684     return ret;
 685 }
 686
 687 int sd_read_sectors(unsigned long start, int count, void* buf)
 688 {
 689     return sd_transfer_sectors(start, count, buf, false);
 690 }
 691
 692 int sd_write_sectors(unsigned long start, int count, const void* buf)
 693 {
 694 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
 695     (void) start;
 696     (void) count;
 697     (void) buf;
 698     return -1;
 699 #else
 700     return sd_transfer_sectors(start, count, (void*)buf, true);
 701 #endif
 702 }
 703
 704 #ifndef BOOTLOADER
 705 long sd_last_disk_activity(void)
 706 {
 707     return last_disk_activity;
 708 }
 709
 710 void sd_enable(bool on)
 711 {
 712     /* TODO */
 713     (void)on;
 714     return;
 715 }
 716
 717 tCardInfo *card_get_info_target(int card_no)
 718 {
 719     (void)card_no;
 720     return &card_info;
 721 }
 722
 723 #endif /* BOOTLOADER */