firmware/target/arm/system-pp502x.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Alan Korr
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "system.h"
  22 #include "thread.h"
  23 #include "i2s.h"
  24 #include "i2c-pp.h"
  25 #include "as3514.h"
  26 #include "ata-sd-target.h"
  27 #include "button-target.h"
  28 #include "usb-target.h"
  29 #include "usb_drv.h"
  30
  31 #ifndef BOOTLOADER
  32 extern void TIMER1(void);
  33 extern void TIMER2(void);
  34 extern void SERIAL0(void);
  35 extern void ipod_mini_button_int(void); /* iPod Mini 1st gen only */
  36 extern void ipod_4g_button_int(void);   /* iPod 4th gen and higher only */
  37
  38 #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
  39 static struct corelock cpufreq_cl SHAREDBSS_ATTR;
  40 #endif
  41
  42 void __attribute__((interrupt("IRQ"))) irq_handler(void)
  43 {
  44     if(CURRENT_CORE == CPU)
  45     {
  46         if (CPU_INT_STAT & TIMER1_MASK) {
  47             TIMER1();
  48         }
  49         else if (CPU_INT_STAT & TIMER2_MASK) {
  50             TIMER2();
  51         }
  52 #ifdef HAVE_USBSTACK
  53         /* Rather high priority - place near front */
  54         else if (CPU_INT_STAT & USB_MASK) {
  55             usb_drv_int();
  56         }
  57 #endif
  58 #if defined(IPOD_MINI) /* Mini 1st gen only, mini 2nd gen uses iPod 4G code */
  59         else if (CPU_HI_INT_STAT & GPIO0_MASK) {
  60             if ((GPIOA_INT_STAT & 0x3f) || (GPIOB_INT_STAT & 0x30))
  61                 ipod_mini_button_int();
  62             if (GPIOC_INT_STAT & 0x02)
  63                 firewire_insert_int();
  64             if (GPIOD_INT_STAT & 0x08)
  65                 usb_insert_int();
  66         }
  67 /* end IPOD_MINI */
  68 #elif CONFIG_KEYPAD == IPOD_4G_PAD /* except Mini 1st gen, handled above */
  69         else if (CPU_HI_INT_STAT & I2C_MASK) {
  70             ipod_4g_button_int();
  71         }
  72 #if defined(IPOD_COLOR) || defined(IPOD_MINI2G) || defined(IPOD_4G)
  73         else if (CPU_HI_INT_STAT & GPIO0_MASK) {
  74             if (GPIOC_INT_STAT & 0x02)
  75                 firewire_insert_int();
  76             if (GPIOD_INT_STAT & 0x08)
  77                 usb_insert_int();
  78         }
  79 #elif defined(IPOD_NANO) || defined(IPOD_VIDEO)
  80         else if (CPU_HI_INT_STAT & GPIO2_MASK) {
  81             if (GPIOL_INT_STAT & 0x10)
  82                 usb_insert_int();
  83         }
  84 #endif
  85 /* end CONFIG_KEYPAD == IPOD_4G_PAD */
  86 #elif defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
  87         else if (CPU_HI_INT_STAT & GPIO2_MASK) {
  88             if (GPIOL_INT_STAT & 0x04)
  89                 usb_insert_int();
  90         }
  91 /* end IRIVER_H10 || IRIVER_H10_5GB */
  92 #elif defined(SANSA_E200)
  93         else if (CPU_HI_INT_STAT & GPIO0_MASK) {
  94 #ifdef HAVE_HOTSWAP
  95             if (GPIOA_INT_STAT & 0x80)
  96                 microsd_int();
  97 #endif
  98             if (GPIOB_INT_STAT & 0x10)
  99                 usb_insert_int();
 100         }
 101         else if (CPU_HI_INT_STAT & GPIO1_MASK) {
 102             if (GPIOF_INT_STAT & 0xff)
 103                 button_int();
 104             if (GPIOH_INT_STAT & 0xc0)
 105                 clickwheel_int();
 106         }
 107 /* end SANSA_E200 */
 108 #elif defined(SANSA_C200)
 109         else if (CPU_HI_INT_STAT & GPIO1_MASK) {
 110             if (GPIOH_INT_STAT & 0x02)
 111                 usb_insert_int();
 112         }
 113 #ifdef HAVE_HOTSWAP
 114         else if (CPU_HI_INT_STAT & GPIO2_MASK) {
 115             if (GPIOL_INT_STAT & 0x08)
 116                 microsd_int();
 117         }
 118 #endif
 119 /* end SANSA_C200 */
 120 #elif defined(MROBE_100)
 121         else if (CPU_HI_INT_STAT & GPIO0_MASK) {
 122             if (GPIOD_INT_STAT & 0x02)
 123                 button_int();
 124         }
 125         else if (CPU_HI_INT_STAT & GPIO2_MASK) {
 126             if (GPIOL_INT_STAT & 0x04)
 127                 usb_insert_int();
 128         }
 129 /* end MROBE_100 */
 130 #elif defined(PHILIPS_SA9200)
 131         else if (CPU_HI_INT_STAT & GPIO1_MASK) {
 132             if (GPIOF_INT_STAT & 0x80)
 133                 usb_insert_int();
 134         }
 135 /* end PHILIPS_SA9200 */
 136 #elif defined(PHILIPS_HDD1630)
 137         else if (CPU_HI_INT_STAT & GPIO0_MASK) {
 138             if (GPIOA_INT_STAT & 0x20)
 139                 button_int();
 140         }
 141         else if (CPU_HI_INT_STAT & GPIO1_MASK) {
 142             if (GPIOE_INT_STAT & 0x04)
 143                 usb_insert_int();
 144         }
 145 /* end PHILIPS_HDD1630 */
 146 #endif
 147 #ifdef IPOD_ACCESSORY_PROTOCOL
 148         else if (CPU_HI_INT_STAT & SER0_MASK) {
 149             SERIAL0();
 150         }
 151 #endif
 152     } else {
 153         if (COP_INT_STAT & TIMER2_MASK)
 154             TIMER2();
 155     }
 156 }
 157 #endif /* BOOTLOADER */
 158
 159 /* TODO: The following function has been lifted straight from IPL, and
 160    hence has a lot of numeric addresses used straight. I'd like to use
 161    #defines for these, but don't know what most of them are for or even what
 162    they should be named. Because of this I also have no way of knowing how
 163    to extend the funtions to do alternate cache configurations. */
 164
 165 #ifndef BOOTLOADER
 166 void ICODE_ATTR cpucache_flush(void)
 167 {
 168     if (CACHE_CTL & CACHE_CTL_ENABLE)
 169     {
 170         CACHE_OPERATION |= CACHE_OP_FLUSH;
 171         while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
 172         nop; nop; nop; nop;
 173     }
 174 }
 175
 176 void ICODE_ATTR cpucache_invalidate(void)
 177 {
 178     if (CACHE_CTL & CACHE_CTL_ENABLE)
 179     {
 180         CACHE_OPERATION |= CACHE_OP_FLUSH | CACHE_OP_INVALIDATE;
 181         while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
 182         nop; nop; nop; nop;
 183     }
 184 }
 185
 186 static void init_cache(void)
 187 {
 188 /* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
 189
 190     /* cache init mode */
 191     CACHE_CTL |= CACHE_CTL_INIT;
 192
 193     /* what's this do? */
 194     CACHE_PRIORITY |= CURRENT_CORE == CPU ? 0x10 : 0x20;
 195
 196     /* Cache if (addr & mask) >> 16 == (mask & match) >> 16:
 197      * yes: 0x00000000 - 0x03ffffff
 198      *  no: 0x04000000 - 0x1fffffff
 199      * yes: 0x20000000 - 0x23ffffff
 200      *  no: 0x24000000 - 0x3fffffff
 201      */
 202     CACHE_MASK = 0x00001c00;
 203     CACHE_OPERATION = 0xfc0;
 204
 205     /* enable cache */
 206     CACHE_CTL |= CACHE_CTL_INIT | CACHE_CTL_ENABLE | CACHE_CTL_RUN;
 207     nop; nop; nop; nop;
 208 }
 209 #endif /* !BOOTLOADER */
 210
 211 /* We need this for Sansas since we boost the cpu in their bootloader */
 212 #if !defined(BOOTLOADER) || defined(SANSA_E200) || defined(SANSA_C200)
 213 void scale_suspend_core(bool suspend) ICODE_ATTR;
 214 void scale_suspend_core(bool suspend)
 215 {
 216     unsigned int core = CURRENT_CORE;
 217     IF_COP( unsigned int othercore = 1 - core; )
 218     static int oldstatus IBSS_ATTR;
 219
 220     if (suspend)
 221     {
 222         oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
 223         IF_COP( PROC_CTL(othercore) = 0x40000000; nop; )
 224         PROC_CTL(core) = 0x48000003; nop;
 225     }
 226     else
 227     {
 228         PROC_CTL(core) = 0x4800001f; nop;
 229         IF_COP( PROC_CTL(othercore) = 0x00000000; nop; )
 230         restore_interrupt(oldstatus);
 231     }
 232 }
 233
 234 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 235 void set_cpu_frequency(long frequency) ICODE_ATTR;
 236 void set_cpu_frequency(long frequency)
 237 #else
 238 static void pp_set_cpu_frequency(long frequency)
 239 #endif
 240 {
 241 #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
 242     corelock_lock(&cpufreq_cl);
 243 #endif
 244
 245     switch (frequency)
 246     {
 247       /* Note1: The PP5022 PLL must be run at >= 96MHz
 248        * Bits 20..21 select the post divider (1/2/4/8).
 249        * PP5026 is similar to PP5022 except it doesn't
 250        * have this limitation (and the post divider?)
 251        * Note2: CLOCK_SOURCE is set via 0=32kHz, 1=16MHz,
 252        * 2=24MHz, 3=33MHz, 4=48MHz, 5=SLOW, 6=FAST, 7=PLL.
 253        * SLOW = 24MHz / (DIV_SLOW + 1), DIV = Bits 16-19
 254        * FAST = PLL   / (DIV_FAST + 1), DIV = Bits 20-23 */
 255       case CPUFREQ_SLEEP:
 256         cpu_frequency =  CPUFREQ_SLEEP;
 257         PLL_CONTROL  |=  0x0c000000;
 258         scale_suspend_core(true);
 259         CLOCK_SOURCE  =  0x20000000; /* source #1, #2, #3, #4: 32kHz (#2 active) */
 260         scale_suspend_core(false);
 261         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
 262         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
 263         break;
 264
 265       case CPUFREQ_MAX:
 266         cpu_frequency = CPUFREQ_MAX;
 267         DEV_INIT2    |= INIT_PLL;   /* enable PLL power */
 268         PLL_CONTROL  |= 0x88000000; /* enable PLL */
 269         scale_suspend_core(true);
 270         CLOCK_SOURCE  = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 271         DEV_TIMING1   = 0x00000303;
 272         scale_suspend_core(false);
 273 #if   defined(IPOD_MINI2G)
 274         MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
 275 #elif defined(IPOD_NANO)
 276         IDE0_CFG     |= 0x10000000; /* set ">65MHz" bit */
 277 #endif
 278 #if CONFIG_CPU == PP5020
 279         PLL_CONTROL   = 0x8a020a03; /* 80 MHz = 10/3 * 24MHz */
 280         PLL_STATUS    = 0xd19b;     /* unlock frequencies > 66MHz */
 281         PLL_CONTROL   = 0x8a020a03; /* repeat setup */
 282         udelay(500);                /* wait for relock */
 283 #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
 284         PLL_CONTROL   = 0x8a121403; /*  80 MHz = (20/3 * 24MHz) / 2 */
 285         while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
 286 #endif
 287         scale_suspend_core(true);
 288         DEV_TIMING1   = 0x00000808;
 289         CLOCK_SOURCE  = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */
 290         scale_suspend_core(false);
 291         break;
 292 #if 0 /******** CPUFREQ_NORMAL = 24MHz without PLL ********/
 293       case CPUFREQ_NORMAL:
 294         cpu_frequency =  CPUFREQ_NORMAL;
 295         PLL_CONTROL  |=  0x08000000;
 296         scale_suspend_core(true);
 297         CLOCK_SOURCE  =  0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 298         DEV_TIMING1   =  0x00000303;
 299 #if   defined(IPOD_MINI2G)
 300         MLCD_SCLK_DIV =  0x00000000; /* Mono LCD bridge serial clock divider */
 301 #elif defined(IPOD_NANO)
 302         IDE0_CFG     &= ~0x10000000; /* clear ">65MHz" bit */
 303 #endif
 304         scale_suspend_core(false);
 305         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
 306         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
 307         break;
 308 #else /******** CPUFREQ_NORMAL = 30MHz with PLL ********/
 309     case CPUFREQ_NORMAL:
 310         cpu_frequency = CPUFREQ_NORMAL;
 311         DEV_INIT2    |= INIT_PLL;   /* enable PLL power */
 312         PLL_CONTROL  |= 0x88000000; /* enable PLL */
 313         scale_suspend_core(true);
 314         CLOCK_SOURCE  = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 315         DEV_TIMING1   = 0x00000303;
 316         scale_suspend_core(false);
 317 #if   defined(IPOD_MINI2G)
 318         MLCD_SCLK_DIV =  0x00000000; /* Mono LCD bridge serial clock divider */
 319 #elif defined(IPOD_NANO)
 320         IDE0_CFG     &= ~0x10000000; /* clear ">65MHz" bit */
 321 #endif
 322 #if CONFIG_CPU == PP5020
 323         PLL_CONTROL   = 0x8a020504; /* 30 MHz = 5/4 * 24MHz */
 324         udelay(500);                /* wait for relock */
 325 #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
 326         PLL_CONTROL   = 0x8a220501; /* 30 MHz = (5/1 * 24MHz) / 4 */
 327         while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
 328 #endif
 329         scale_suspend_core(true);
 330         DEV_TIMING1   = 0x00000303;
 331         CLOCK_SOURCE  = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */
 332         scale_suspend_core(false);
 333         break;
 334 #endif /******** CPUFREQ_NORMAL end ********/
 335       default:
 336         cpu_frequency =  CPUFREQ_DEFAULT;
 337         PLL_CONTROL  |=  0x08000000;
 338         scale_suspend_core(true);
 339         CLOCK_SOURCE  =  0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 340         DEV_TIMING1   =  0x00000303;
 341 #if   defined(IPOD_MINI2G)
 342         MLCD_SCLK_DIV =  0x00000000; /* Mono LCD bridge serial clock divider */
 343 #elif defined(IPOD_NANO)
 344         IDE0_CFG     &= ~0x10000000; /* clear ">65MHz" bit */
 345 #endif
 346         scale_suspend_core(false);
 347         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
 348         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
 349         break;
 350     }
 351
 352 #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
 353     corelock_unlock(&cpufreq_cl);
 354 #endif
 355 }
 356 #endif /* !BOOTLOADER || SANSA_E200 || SANSA_C200 */
 357
 358 void system_init(void)
 359 {
 360 #ifndef BOOTLOADER
 361     if (CURRENT_CORE == CPU)
 362     {
 363 #if defined (IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_COLOR)
 364         /* set minimum startup configuration */
 365         DEV_EN         = 0xc2000124;
 366         DEV_EN2        = 0x00002000;
 367         CACHE_PRIORITY = 0x0000003f;
 368         GPO32_VAL      = 0x20000000;
 369         DEV_INIT1      = 0xdc000000;
 370         DEV_INIT2      = 0x40000000;
 371
 372         /* reset all allowed devices */
 373         DEV_RS         = 0x3dfffef8;
 374         DEV_RS2        = 0xffffdfff;
 375         DEV_RS         = 0x00000000;
 376         DEV_RS2        = 0x00000000;
 377 #elif defined (IPOD_VIDEO)
 378         /* set minimum startup configuration */
 379         DEV_EN         = 0xc2000124;
 380         DEV_EN2        = 0x00000000;
 381         CACHE_PRIORITY = 0x0000003f;
 382         GPO32_VAL      = 0x00004000;
 383         DEV_INIT1      = 0x00000000;
 384         DEV_INIT2      = 0x40000000;
 385
 386         /* reset all allowed devices */
 387         DEV_RS         = 0x3dfffef8;
 388         DEV_RS2        = 0xffffffff;
 389         DEV_RS         = 0x00000000;
 390         DEV_RS2        = 0x00000000;
 391 #elif defined (IPOD_NANO)
 392         /* set minimum startup configuration */
 393         DEV_EN         = 0xc2000124;
 394         DEV_EN2        = 0x00002000;
 395         CACHE_PRIORITY = 0x0000003f;
 396         GPO32_VAL      = 0x50000000;
 397         DEV_INIT1      = 0xa8000000;
 398         DEV_INIT2      = 0x40000000;
 399
 400         /* reset all allowed devices */
 401         DEV_RS         = 0x3ffffef8;
 402         DEV_RS2        = 0xffffdfff;
 403         DEV_RS         = 0x00000000;
 404         DEV_RS2        = 0x00000000;
 405 #elif defined(SANSA_C200) || defined (SANSA_E200)
 406         /* set minimum startup configuration */
 407         DEV_EN         = 0xc4000124;
 408         DEV_EN2        = 0x00000000;
 409         CACHE_PRIORITY = 0x0000003f;
 410         GPO32_VAL      = 0x10000000;
 411         DEV_INIT1      = 0x54000000;
 412         DEV_INIT2      = 0x40000000;
 413
 414         /* reset all allowed devices */
 415         DEV_RS         = 0x3bfffef8;
 416         DEV_RS2        = 0xffffffff;
 417         DEV_RS         = 0x00000000;
 418         DEV_RS2        = 0x00000000;
 419 #elif defined(IPOD_4G)
 420         /* set minimum startup configuration */
 421         DEV_EN         = 0xc2020124;
 422         DEV_EN2        = 0x00000000;
 423         CACHE_PRIORITY = 0x0000003f;
 424         GPO32_VAL      = 0x02000000;
 425         DEV_INIT1      = 0x00000000;
 426         DEV_INIT2      = 0x40000000;
 427
 428         /* reset all allowed devices */
 429         DEV_RS         = 0x3dfdfef8;
 430         DEV_RS2        = 0xffffffff;
 431         DEV_RS         = 0x00000000;
 432         DEV_RS2        = 0x00000000;
 433 #elif defined (IPOD_MINI)
 434         /* to be done */
 435 #elif defined (IPOD_MINI2G)
 436         /* to be done */
 437 #elif defined (MROBE_100)
 438         /* to be done */
 439 #elif defined (ELIO_TPJ1022)
 440         /* to be done */
 441 #endif
 442
 443 #if !defined(SANSA_E200) && !defined(SANSA_C200) && !defined(PHILIPS_SA9200)
 444         /* Remap the flash ROM on CPU, keep hidden from COP:
 445          * 0x00000000-0x3fffffff = 0x20000000-0x23ffffff */
 446         MMAP1_LOGICAL  = 0x20003c00;
 447         MMAP1_PHYSICAL = 0x00003084 |
 448             MMAP_PHYS_READ_MASK | MMAP_PHYS_WRITE_MASK |
 449             MMAP_PHYS_DATA_MASK | MMAP_PHYS_CODE_MASK;
 450 #endif
 451
 452         /* disable all irqs */
 453         COP_HI_INT_DIS      = -1;
 454         CPU_HI_INT_DIS      = -1;
 455         HI_INT_FORCED_CLR   = -1;
 456
 457         COP_INT_DIS         = -1;
 458         CPU_INT_DIS         = -1;
 459         INT_FORCED_CLR      = -1;
 460
 461         GPIOA_INT_EN        = 0;
 462         GPIOB_INT_EN        = 0;
 463         GPIOC_INT_EN        = 0;
 464         GPIOD_INT_EN        = 0;
 465         GPIOE_INT_EN        = 0;
 466         GPIOF_INT_EN        = 0;
 467         GPIOG_INT_EN        = 0;
 468         GPIOH_INT_EN        = 0;
 469         GPIOI_INT_EN        = 0;
 470         GPIOJ_INT_EN        = 0;
 471         GPIOK_INT_EN        = 0;
 472         GPIOL_INT_EN        = 0;
 473
 474 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 475 #if NUM_CORES > 1
 476         corelock_init(&cpufreq_cl);
 477         cpu_boost_init();
 478 #endif
 479 #else
 480         pp_set_cpu_frequency(CPUFREQ_MAX);
 481 #endif
 482     }
 483
 484     init_cache();
 485 #else /* BOOTLOADER */
 486     if (CURRENT_CORE == CPU)
 487     {
 488 #if defined(SANSA_C200) || defined (SANSA_E200)
 489         pp_set_cpu_frequency(CPUFREQ_MAX);
 490 #endif
 491     }
 492 #endif /* BOOTLOADER */
 493 }
 494
 495 void ICODE_ATTR system_reboot(void)
 496 {
 497     disable_interrupt(IRQ_FIQ_STATUS);
 498     CPU_INT_DIS = -1;
 499     COP_INT_DIS = -1;
 500
 501     /* Reboot */
 502 #if defined(SANSA_E200) || defined(SANSA_C200) || defined(PHILIPS_SA9200)
 503     CACHE_CTL &= ~CACHE_CTL_VECT_REMAP;
 504
 505     /* Magic used by the c200 OF: 0x23066000
 506        Magic used by the c200 BL: 0x23066b7b
 507        In both cases, the OF executes these 2 commands from iram. */
 508     STRAP_OPT_A = 0x23066b7b;
 509     DEV_RS = DEV_SYSTEM;
 510 #else
 511     DEV_RS |= DEV_SYSTEM;
 512 #endif
 513     /* wait until reboot kicks in */
 514     while (1);
 515 }
 516
 517 void system_exception_wait(void)
 518 {
 519     /* FIXME: we just need the right buttons */
 520     CPU_INT_DIS = -1;
 521     COP_INT_DIS = -1;
 522
 523     /* Halt */
 524     PROC_CTL(CURRENT_CORE) = 0x40000000;
 525     while (1);
 526 }
 527
 528 int system_memory_guard(int newmode)
 529 {
 530     (void)newmode;
 531     return 0;
 532 }