firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2009 by Michael Sparmann
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22
  23 #include "config.h"
  24 #include "panic.h"
  25 #include "system.h"
  26 #include "kernel.h"
  27 #include "cpu.h"
  28 #include "inttypes.h"
  29 #include "nand-target.h"
  30 #include <pmu-target.h>
  31 #include <mmu-target.h>
  32 #include <string.h>
  33 #include "led.h"
  34
  35
  36 #define NAND_CMD_READ       0x00
  37 #define NAND_CMD_PROGCNFRM  0x10
  38 #define NAND_CMD_READ2      0x30
  39 #define NAND_CMD_BLOCKERASE 0x60
  40 #define NAND_CMD_GET_STATUS 0x70
  41 #define NAND_CMD_PROGRAM    0x80
  42 #define NAND_CMD_ERASECNFRM 0xD0
  43 #define NAND_CMD_RESET      0xFF
  44
  45 #define NAND_STATUS_READY   0x40
  46
  47 #define NAND_DEVICEINFOTABLE_ENTRIES 33
  48
  49 static const struct nand_device_info_type nand_deviceinfotable[] =
  50 {
  51     {0x1580F1EC, 1024, 968, 0x40, 6, 2, 1, 2, 1},
  52     {0x1580DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
  53     {0x15C1DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
  54     {0x1510DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  55     {0x95C1DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  56     {0x2514DCEC, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
  57     {0x2514D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
  58     {0x2555D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
  59     {0x2555D5EC, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
  60     {0x2585D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
  61     {0x9580DCAD, 4096, 3872, 0x40, 6, 3, 2, 3, 2},
  62     {0xA514D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
  63     {0xA550D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
  64     {0xA560D5AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
  65     {0xA555D5AD, 8192, 7744, 0x80, 7, 3, 2, 3, 2},
  66     {0xA585D598, 8320, 7744, 0x80, 7, 3, 1, 2, 1},
  67     {0xA584D398, 4160, 3872, 0x80, 7, 3, 1, 2, 1},
  68     {0x95D1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
  69     {0x1580DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  70     {0x15C1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
  71     {0x9590DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  72     {0xA594D32C, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
  73     {0x2584DC2C, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
  74     {0xA5D5D52C, 8192, 7744, 0x80, 7, 3, 2, 2, 1},
  75     {0x95D1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
  76     {0x1580DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  77     {0x15C1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
  78     {0x9590DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  79     {0xA594D389, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
  80     {0x2584DC89, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
  81     {0xA5D5D589, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
  82     {0xA514D320, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
  83     {0xA555D520, 8192, 3872, 0x80, 7, 2, 1, 2, 1}
  84 };
  85
  86 uint8_t nand_tunk1[4];
  87 uint8_t nand_twp[4];
  88 uint8_t nand_tunk2[4];
  89 uint8_t nand_tunk3[4];
  90 uint32_t nand_type[4];
  91 int nand_powered = 0;
  92 long nand_last_activity_value = -1;
  93 static long nand_stack[32];
  94
  95 static struct mutex nand_mtx;
  96 static struct wakeup nand_wakeup;
  97 static struct mutex ecc_mtx;
  98 static struct wakeup ecc_wakeup;
  99
 100 static uint8_t nand_data[0x800] __attribute__((aligned(16)));
 101 static uint8_t nand_ctrl[0x200] __attribute__((aligned(16)));
 102 static uint8_t nand_spare[0x40] __attribute__((aligned(16)));
 103 static uint8_t nand_ecc[0x30] __attribute__((aligned(16)));
 104
 105
 106 uint32_t nand_unlock(uint32_t rc)
 107 {
 108     led(false);
 109     mutex_unlock(&nand_mtx);
 110     return rc;
 111 }
 112
 113 uint32_t ecc_unlock(uint32_t rc)
 114 {
 115     mutex_unlock(&ecc_mtx);
 116     return rc;
 117 }
 118
 119 uint32_t nand_timeout(long timeout)
 120 {
 121     if (TIME_AFTER(current_tick, timeout)) return 1;
 122     else
 123     {
 124         yield();
 125         return 0;
 126     }
 127 }
 128
 129 uint32_t nand_wait_rbbdone(void)
 130 {
 131     long timeout = current_tick + HZ / 50;
 132     while (!(FMCSTAT & FMCSTAT_RBBDONE))
 133         if (nand_timeout(timeout)) return 1;
 134     FMCSTAT = FMCSTAT_RBBDONE;
 135     return 0;
 136 }
 137
 138 uint32_t nand_wait_cmddone(void)
 139 {
 140     long timeout = current_tick + HZ / 50;
 141     while (!(FMCSTAT & FMCSTAT_CMDDONE))
 142         if (nand_timeout(timeout)) return 1;
 143     FMCSTAT = FMCSTAT_CMDDONE;
 144     return 0;
 145 }
 146
 147 uint32_t nand_wait_addrdone(void)
 148 {
 149     long timeout = current_tick + HZ / 50;
 150     while (!(FMCSTAT & FMCSTAT_ADDRDONE))
 151         if (nand_timeout(timeout)) return 1;
 152     FMCSTAT = FMCSTAT_ADDRDONE;
 153     return 0;
 154 }
 155
 156 uint32_t nand_wait_chip_ready(uint32_t bank)
 157 {
 158     long timeout = current_tick + HZ / 50;
 159     while (!(FMCSTAT & (FMCSTAT_BANK0READY << bank)))
 160         if (nand_timeout(timeout)) return 1;
 161     FMCSTAT = (FMCSTAT_BANK0READY << bank);
 162     return 0;
 163 }
 164
 165 void nand_set_fmctrl0(uint32_t bank, uint32_t flags)
 166 {
 167     FMCTRL0 = (nand_tunk1[bank] << 16) | (nand_twp[bank] << 12)
 168             | (1 << 11) | 1 | (1 << (bank + 1)) | flags;
 169 }
 170
 171 uint32_t nand_send_cmd(uint32_t cmd)
 172 {
 173     FMCMD = cmd;
 174     return nand_wait_rbbdone();
 175 }
 176
 177 uint32_t nand_send_address(uint32_t page, uint32_t offset)
 178 {
 179     FMANUM = 4;
 180     FMADDR0 = (page << 16) | offset;
 181     FMADDR1 = (page >> 16) & 0xFF;
 182     FMCTRL1 = FMCTRL1_DOTRANSADDR;
 183     return nand_wait_cmddone();
 184 }
 185
 186 uint32_t nand_reset(uint32_t bank)
 187 {
 188     nand_set_fmctrl0(bank, 0);
 189     if (nand_send_cmd(NAND_CMD_RESET)) return 1;
 190     if (nand_wait_chip_ready(bank)) return 1;
 191     FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
 192     sleep(0);
 193     return 0;
 194 }
 195
 196 uint32_t nand_wait_status_ready(uint32_t bank)
 197 {
 198     long timeout = current_tick + HZ / 50;
 199     nand_set_fmctrl0(bank, 0);
 200     if ((FMCSTAT & (FMCSTAT_BANK0READY << bank)))
 201         FMCSTAT = (FMCSTAT_BANK0READY << bank);
 202     FMCTRL1 = FMCTRL1_CLEARRFIFO;
 203     if (nand_send_cmd(NAND_CMD_GET_STATUS)) return 1;
 204     while (1)
 205     {
 206         if (nand_timeout(timeout)) return 1;
 207         FMDNUM = 0;
 208         FMCTRL1 = FMCTRL1_DOREADDATA;
 209         if (nand_wait_addrdone()) return 1;
 210         if ((FMFIFO & NAND_STATUS_READY)) break;
 211         FMCTRL1 = FMCTRL1_CLEARRFIFO;
 212     }
 213     FMCTRL1 = FMCTRL1_CLEARRFIFO;
 214     return nand_send_cmd(NAND_CMD_READ);
 215 }
 216
 217 uint32_t nand_transfer_data(uint32_t bank, uint32_t direction,
 218                             void* buffer, uint32_t size)
 219 {
 220     long timeout = current_tick + HZ / 50;
 221     nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
 222     FMDNUM = size - 1;
 223     FMCTRL1 = FMCTRL1_DOREADDATA << direction;
 224     DMACON3 = (2 << DMACON_DEVICE_SHIFT)
 225             | (direction << DMACON_DIRECTION_SHIFT)
 226             | (2 << DMACON_DATA_SIZE_SHIFT)
 227             | (3 << DMACON_BURST_LEN_SHIFT);
 228     while ((DMAALLST & DMAALLST_CHAN3_MASK))
 229         DMACOM3 = DMACOM_CLEARBOTHDONE;
 230     DMABASE3 = (uint32_t)buffer;
 231     DMATCNT3 = (size >> 4) - 1;
 232     clean_dcache();
 233     DMACOM3 = 4;
 234     while ((DMAALLST & DMAALLST_DMABUSY3))
 235         if (nand_timeout(timeout)) return 1;
 236     if (!direction) invalidate_dcache();
 237     if (nand_wait_addrdone()) return 1;
 238     if (!direction) FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
 239     else FMCTRL1 = FMCTRL1_CLEARRFIFO;
 240     return 0;
 241 }
 242
 243 uint32_t ecc_decode(uint32_t size, void* databuffer, void* sparebuffer)
 244 {
 245     mutex_lock(&ecc_mtx);
 246     long timeout = current_tick + HZ / 50;
 247     ECC_INT_CLR = 1;
 248     SRCPND = INTMSK_ECC;
 249     ECC_UNK1 = size;
 250     ECC_DATA_PTR = (uint32_t)databuffer;
 251     ECC_SPARE_PTR = (uint32_t)sparebuffer;
 252     clean_dcache();
 253     ECC_CTRL = ECCCTRL_STARTDECODING;
 254     while (!(SRCPND & INTMSK_ECC))
 255         if (nand_timeout(timeout)) return ecc_unlock(1);
 256     invalidate_dcache();
 257     ECC_INT_CLR = 1;
 258     SRCPND = INTMSK_ECC;
 259     return ecc_unlock(ECC_RESULT);
 260 }
 261
 262 uint32_t ecc_encode(uint32_t size, void* databuffer, void* sparebuffer)
 263 {
 264     mutex_lock(&ecc_mtx);
 265     long timeout = current_tick + HZ / 50;
 266     ECC_INT_CLR = 1;
 267     SRCPND = INTMSK_ECC;
 268     ECC_UNK1 = size;
 269     ECC_DATA_PTR = (uint32_t)databuffer;
 270     ECC_SPARE_PTR = (uint32_t)sparebuffer;
 271     clean_dcache();
 272     ECC_CTRL = ECCCTRL_STARTENCODING;
 273     while (!(SRCPND & INTMSK_ECC))
 274         if (nand_timeout(timeout)) return ecc_unlock(1);
 275     invalidate_dcache();
 276     ECC_INT_CLR = 1;
 277     SRCPND = INTMSK_ECC;
 278     return ecc_unlock(0);
 279 }
 280
 281 uint32_t nand_check_empty(uint8_t* buffer)
 282 {
 283     uint32_t i, count;
 284     count = 0;
 285     for (i = 0; i < 0x40; i++) if (buffer[i] != 0xFF) count++;
 286     if (count < 2) return 1;
 287     return 0;
 288 }
 289
 290 uint32_t nand_get_chip_type(uint32_t bank)
 291 {
 292     mutex_lock(&nand_mtx);
 293     uint32_t result;
 294     if (nand_reset(bank)) return nand_unlock(0xFFFFFFFF);
 295     if (nand_send_cmd(0x90)) return nand_unlock(0xFFFFFFFF);
 296     FMANUM = 0;
 297     FMADDR0 = 0;
 298     FMCTRL1 = FMCTRL1_DOTRANSADDR;
 299     if (nand_wait_cmddone()) return nand_unlock(0xFFFFFFFF);
 300     FMDNUM = 4;
 301     FMCTRL1 = FMCTRL1_DOREADDATA;
 302     if (nand_wait_addrdone()) return nand_unlock(0xFFFFFFFF);
 303     result = FMFIFO;
 304     FMCTRL1 = FMCTRL1_CLEARRFIFO;
 305     return nand_unlock(result);
 306 }
 307
 308 void nand_set_active(void)
 309 {
 310     nand_last_activity_value = current_tick;
 311 }
 312
 313 long nand_last_activity(void)
 314 {
 315     return nand_last_activity_value;
 316 }
 317
 318 void nand_power_up(void)
 319 {
 320     uint32_t i;
 321     mutex_lock(&nand_mtx);
 322     nand_last_activity_value = current_tick;
 323     PWRCONEXT &= ~0x40;
 324     PWRCON &= ~0x100000;
 325     PCON2 = 0x33333333;
 326     PDAT2 = 0;
 327     PCON3 = 0x11113333;
 328     PDAT3 = 0;
 329     PCON4 = 0x33333333;
 330     PDAT4 = 0;
 331     PCON5 = (PCON5 & ~0xF) | 3;
 332     PUNK5 = 1;
 333     pmu_ldo_set_voltage(4, 0x15);
 334     pmu_ldo_power_on(4);
 335     sleep(HZ / 20);
 336     nand_last_activity_value = current_tick;
 337     for (i = 0; i < 4; i++)
 338     {
 339         if(nand_type[i] != 0xFFFFFFFF)
 340         {
 341             if(nand_reset(i))
 342                 panicf("nand_power_up: nand_reset(bank=%d) failed.",(unsigned int)i);
 343         }
 344     }
 345     nand_powered = 1;
 346     nand_last_activity_value = current_tick;
 347     mutex_unlock(&nand_mtx);
 348 }
 349
 350 void nand_power_down(void)
 351 {
 352     if (!nand_powered) return;
 353     mutex_lock(&nand_mtx);
 354     pmu_ldo_power_off(4);
 355     PCON2 = 0x11111111;
 356     PDAT2 = 0;
 357     PCON3 = 0x11111111;
 358     PDAT3 = 0;
 359     PCON4 = 0x11111111;
 360     PDAT4 = 0;
 361     PCON5 = (PCON5 & ~0xF) | 1;
 362     PUNK5 = 1;
 363     PWRCONEXT |= 0x40;
 364     PWRCON |= 0x100000;
 365     nand_powered = 0;
 366     mutex_unlock(&nand_mtx);
 367 }
 368
 369 uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
 370                         void* sparebuffer, uint32_t doecc,
 371                         uint32_t checkempty)
 372 {
 373     uint8_t* data = nand_data;
 374     uint8_t* spare = nand_spare;
 375     if (databuffer && !((uint32_t)databuffer & 0xf))
 376         data = (uint8_t*)databuffer;
 377     if (sparebuffer && !((uint32_t)sparebuffer & 0xf))
 378         spare = (uint8_t*)sparebuffer;
 379     mutex_lock(&nand_mtx);
 380     nand_last_activity_value = current_tick;
 381     led(true);
 382     if (!nand_powered) nand_power_up();
 383     uint32_t rc, eccresult;
 384     nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
 385     if (nand_send_cmd(NAND_CMD_READ)) return nand_unlock(1);
 386     if (nand_send_address(page, databuffer ? 0 : 0x800))
 387         return nand_unlock(1);
 388     if (nand_send_cmd(NAND_CMD_READ2)) return nand_unlock(1);
 389     if (nand_wait_status_ready(bank)) return nand_unlock(1);
 390     if (databuffer)
 391         if (nand_transfer_data(bank, 0, data, 0x800))
 392             return nand_unlock(1);
 393     rc = 0;
 394     if (!doecc)
 395     {
 396         if (databuffer && data != databuffer) memcpy(databuffer, data, 0x800);
 397         if (sparebuffer)
 398         {
 399             if (nand_transfer_data(bank, 0, spare, 0x40))
 400                 return nand_unlock(1);
 401             if (sparebuffer && spare != sparebuffer)
 402                 memcpy(sparebuffer, spare, 0x800);
 403             if (checkempty)
 404                 rc = nand_check_empty((uint8_t*)sparebuffer) << 1;
 405         }
 406         return nand_unlock(rc);
 407     }
 408     if (nand_transfer_data(bank, 0, spare, 0x40)) return nand_unlock(1);
 409     if (databuffer)
 410     {
 411         memcpy(nand_ecc, &spare[0xC], 0x28);
 412         rc |= (ecc_decode(3, data, nand_ecc) & 0xF) << 4;
 413         if (data != databuffer) memcpy(databuffer, data, 0x800);
 414     }
 415     memset(nand_ctrl, 0xFF, 0x200);
 416     memcpy(nand_ctrl, spare, 0xC);
 417     memcpy(nand_ecc, &spare[0x34], 0xC);
 418     eccresult = ecc_decode(0, nand_ctrl, nand_ecc);
 419     rc |= (eccresult & 0xF) << 8;
 420     if (sparebuffer)
 421     {
 422         if (spare != sparebuffer) memcpy(sparebuffer, spare, 0x40);
 423         if (eccresult & 1) memset(sparebuffer, 0xFF, 0xC);
 424         else memcpy(sparebuffer, nand_ctrl, 0xC);
 425     }
 426     if (checkempty) rc |= nand_check_empty(spare) << 1;
 427
 428     return nand_unlock(rc);
 429 }
 430
 431 uint32_t nand_write_page(uint32_t bank, uint32_t page, void* databuffer,
 432                          void* sparebuffer, uint32_t doecc)
 433 {
 434     uint8_t* data = nand_data;
 435     uint8_t* spare = nand_spare;
 436     if (databuffer && !((uint32_t)databuffer & 0xf))
 437         data = (uint8_t*)databuffer;
 438     if (sparebuffer && !((uint32_t)sparebuffer & 0xf))
 439         spare = (uint8_t*)sparebuffer;
 440     mutex_lock(&nand_mtx);
 441     nand_last_activity_value = current_tick;
 442     led(true);
 443     if (!nand_powered) nand_power_up();
 444     if (sparebuffer)
 445     {
 446         if (spare != sparebuffer) memcpy(spare, sparebuffer, 0x40);
 447     }
 448     else memset(spare, 0xFF, 0x40);
 449     if (doecc)
 450     {
 451         if (databuffer && data != databuffer) memcpy(data, databuffer, 0x800);
 452         if (ecc_encode(3, data, nand_ecc)) return nand_unlock(1);
 453         memcpy(&spare[0xC], nand_ecc, 0x28);
 454         memset(nand_ctrl, 0xFF, 0x200);
 455         memcpy(nand_ctrl, spare, 0xC);
 456         if (ecc_encode(0, nand_ctrl, nand_ecc)) return nand_unlock(1);
 457         memcpy(&spare[0x34], nand_ecc, 0xC);
 458     }
 459     nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
 460     if (nand_send_cmd(NAND_CMD_PROGRAM)) return nand_unlock(1);
 461     if (nand_send_address(page, databuffer ? 0 : 0x800))
 462         return nand_unlock(1);
 463     if (databuffer)
 464         if (nand_transfer_data(bank, 1, data, 0x800))
 465             return nand_unlock(1);
 466     if (sparebuffer || doecc)
 467         if (nand_transfer_data(bank, 1, spare, 0x40))
 468             return nand_unlock(1);
 469     if (nand_send_cmd(NAND_CMD_PROGCNFRM)) return nand_unlock(1);
 470     return nand_unlock(nand_wait_status_ready(bank));
 471 }
 472
 473 uint32_t nand_block_erase(uint32_t bank, uint32_t page)
 474 {
 475     mutex_lock(&nand_mtx);
 476     nand_last_activity_value = current_tick;
 477     led(true);
 478     if (!nand_powered) nand_power_up();
 479     nand_set_fmctrl0(bank, 0);
 480     if (nand_send_cmd(NAND_CMD_BLOCKERASE)) return nand_unlock(1);
 481     FMANUM = 2;
 482     FMADDR0 = page;
 483     FMCTRL1 = FMCTRL1_DOTRANSADDR;
 484     if (nand_wait_cmddone()) return nand_unlock(1);
 485     if (nand_send_cmd(NAND_CMD_ERASECNFRM)) return nand_unlock(1);
 486     if (nand_wait_status_ready(bank)) return nand_unlock(1);
 487     return nand_unlock(0);
 488 }
 489
 490 const struct nand_device_info_type* nand_get_device_type(uint32_t bank)
 491 {
 492     if (nand_type[bank] == 0xFFFFFFFF)
 493         return (struct nand_device_info_type*)0;
 494     return &nand_deviceinfotable[nand_type[bank]];
 495 }
 496
 497 static void nand_thread(void)
 498 {
 499     while (1)
 500     {
 501         if (TIME_AFTER(current_tick, nand_last_activity_value + HZ / 5)
 502          && nand_powered)
 503             nand_power_down();
 504         sleep(HZ / 10);
 505     }
 506 }
 507
 508 uint32_t nand_device_init(void)
 509 {
 510     mutex_init(&nand_mtx);
 511     wakeup_init(&nand_wakeup);
 512     mutex_init(&ecc_mtx);
 513     wakeup_init(&ecc_wakeup);
 514
 515     uint32_t type;
 516     uint32_t i, j;
 517
 518     /* Assume there are 0 banks, to prevent
 519        nand_power_up from talking with them yet. */
 520     for(i = 0; i < 4; i++) nand_type[i] = 0xFFFFFFFF;
 521     nand_power_up();
 522
 523     /* Now that the flash is powered on, detect how
 524        many banks we really have and initialize them. */
 525     for (i = 0; i < 4; i++)
 526     {
 527         nand_tunk1[i] = 7;
 528         nand_twp[i] = 7;
 529         nand_tunk2[i] = 7;
 530         nand_tunk3[i] = 7;
 531         type = nand_get_chip_type(i);
 532         if (type == 0xFFFFFFFF) continue;
 533         for (j = 0; ; j++)
 534         {
 535             if (j == ARRAYLEN(nand_deviceinfotable)) break;
 536             else if (nand_deviceinfotable[j].id == type)
 537             {
 538                 nand_type[i] = j;
 539                 break;
 540             }
 541         }
 542         nand_tunk1[i] = nand_deviceinfotable[nand_type[i]].tunk1;
 543         nand_twp[i] = nand_deviceinfotable[nand_type[i]].twp;
 544         nand_tunk2[i] = nand_deviceinfotable[nand_type[i]].tunk2;
 545         nand_tunk3[i] = nand_deviceinfotable[nand_type[i]].tunk3;
 546     }
 547     if (nand_type[0] == 0xFFFFFFFF) return 1;
 548
 549     nand_last_activity_value = current_tick;
 550     create_thread(nand_thread, nand_stack,
 551                   sizeof(nand_stack), 0, "nand"
 552                   IF_PRIO(, PRIORITY_USER_INTERFACE)
 553                   IF_COP(, CPU));
 554
 555     return 0;
 556 }