1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2002 by Alan Korr
11 * Copyright (C) 2007 by Michael Sevakis
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
21 ****************************************************************************/
22 #ifndef SYSTEM_TARGET_H
23 #define SYSTEM_TARGET_H
26 #include "system-arm.h"
29 /* TODO: This header is actually portalplayer specific, and should be
30 * moved into an appropriate subdir (or even split in 2). */
32 #if CONFIG_CPU == PP5002
33 #define CPUFREQ_SLEEP 32768
34 #define CPUFREQ_DEFAULT 24000000
35 #define CPUFREQ_NORMAL 30000000
36 #define CPUFREQ_MAX 80000000
38 #else /* PP5022, PP5024 */
39 #define CPUFREQ_SLEEP 32768
40 #define CPUFREQ_DEFAULT 24000000
41 #define CPUFREQ_NORMAL 30000000
42 #define CPUFREQ_MAX 80000000
45 #define inl(a) (*(volatile unsigned long *) (a))
46 #define outl(a,b) (*(volatile unsigned long *) (b) = (a))
47 #define inb(a) (*(volatile unsigned char *) (a))
48 #define outb(a,b) (*(volatile unsigned char *) (b) = (a))
49 #define inw(a) (*(volatile unsigned short *) (a))
50 #define outw(a,b) (*(volatile unsigned short *) (b) = (a))
52 static inline void udelay(unsigned usecs
)
54 unsigned stop
= USEC_TIMER
+ usecs
;
55 while (TIME_BEFORE(USEC_TIMER
, stop
));
58 static inline unsigned int current_core(void)
61 * PROCESSOR_ID seems to be 32-bits:
62 * CPU = 0x55555555 = |01010101|01010101|01010101|01010101|
63 * COP = 0xaaaaaaaa = |10101010|10101010|10101010|10101010|
68 "ldrb %0, [%1] \n" /* Just load the LSB */
69 "mov %0, %0, lsr #7 \n" /* Bit 7 => index */
70 : "=r"(core
) /* CPU=0, COP=1 */
76 /* Return the actual ID instead of core index */
77 static inline unsigned int processor_id(void)
90 #if CONFIG_CPU == PP5002
91 static inline void sleep_core(int core
)
94 /* Sleep: PP5002 crashes if the instruction that puts it to sleep is
95 * located at 0xNNNNNNN0. 4/8/C works. This sequence makes sure
96 * that the correct alternative is executed. Don't change the order
97 * of the next 4 instructions! */
100 "strne r0, [%[ctl]] \n"
101 "streq r0, [%[ctl]] \n"
102 "nop \n" /* nop's needed because of pipeline */
106 : [ctl
]"r"(&PROC_CTL(core
))
110 static inline void wake_core(int core
)
114 "str r0, [%[ctl]] \n"
116 : [ctl
]"r"(&PROC_CTL(core
))
121 static inline void sleep_core(int core
)
124 "mov r0, #0x80000000 \n"
125 "str r0, [%[ctl]] \n"
128 : [ctl
]"r"(&PROC_CTL(core
))
132 static inline void wake_core(int core
)
136 "str r0, [%[ctl]] \n"
138 : [ctl
]"r"(&PROC_CTL(core
))
145 /* All addresses within rockbox are in IRAM in the bootloader so
146 are therefore uncached */
147 #define UNCACHED_ADDR(a) (a)
149 #else /* !BOOTLOADER */
151 #if CONFIG_CPU == PP5002
152 #define UNCACHED_BASE_ADDR 0x28000000
154 #define UNCACHED_BASE_ADDR 0x10000000
157 #define UNCACHED_ADDR(a) \
158 ((typeof (a))((uintptr_t)(a) | UNCACHED_BASE_ADDR))
159 #endif /* BOOTLOADER */
161 /* Certain data needs to be out of the way of cache line interference
162 * such as data for COP use or for use with UNCACHED_ADDR */
163 #define PROC_NEEDS_CACHEALIGN
165 #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA)
166 #define STORAGE_WANTS_ALIGN
169 /** cache functions **/
171 #define HAVE_CPUCACHE_INVALIDATE
172 #define HAVE_CPUCACHE_FLUSH
177 #endif /* SYSTEM_TARGET_H */