firmware/target/arm/as3525/mmci.h

   1 /*
   2  *  linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 //#define MMCIPOWER             0x000
  11 #define MCI_PWR_OFF             0x00
  12 #define MCI_PWR_UP              0x02
  13 #define MCI_PWR_ON              0x03
  14 #define MCI_OD                  (1 << 6)
  15 #define MCI_ROD                 (1 << 7)
  16
  17 //#define MMCICLOCK             0x004
  18 #define MCI_CLK_ENABLE          (1 << 8)
  19 #define MCI_CLK_PWRSAVE         (1 << 9)
  20 #define MCI_CLK_BYPASS          (1 << 10)
  21 #define MCI_WIDEBUS         (1 << 11)
  22
  23 //#define MMCIARGUMENT          0x008
  24 //#define MMCICOMMAND           0x00c
  25 #define MCI_CPSM_RESPONSE       (1 << 6)
  26 #define MCI_CPSM_LONGRSP        (1 << 7)
  27 #define MCI_CPSM_INTERRUPT      (1 << 8)
  28 #define MCI_CPSM_PENDING        (1 << 9)
  29 #define MCI_CPSM_ENABLE         (1 << 10)
  30
  31 #if 0
  32 #define MMCIRESPCMD             0x010
  33 #define MMCIRESPONSE0           0x014
  34 #define MMCIRESPONSE1           0x018
  35 #define MMCIRESPONSE2           0x01c
  36 #define MMCIRESPONSE3           0x020
  37 #define MMCIDATATIMER           0x024
  38 #define MMCIDATALENGTH          0x028
  39 #define MMCIDATACTRL            0x02c
  40 #endif
  41 #define MCI_DPSM_ENABLE         (1 << 0)
  42 #define MCI_DPSM_DIRECTION      (1 << 1)
  43 #define MCI_DPSM_MODE           (1 << 2)
  44 #define MCI_DPSM_DMAENABLE      (1 << 3)
  45
  46 //#define MMCIDATACNT           0x030
  47 //#define MMCISTATUS            0x034
  48 #define MCI_CMDCRCFAIL          (1 << 0)
  49 #define MCI_DATACRCFAIL         (1 << 1)
  50 #define MCI_CMDTIMEOUT          (1 << 2)
  51 #define MCI_DATATIMEOUT         (1 << 3)
  52 #define MCI_TXUNDERRUN          (1 << 4)
  53 #define MCI_RXOVERRUN           (1 << 5)
  54 #define MCI_CMDRESPEND          (1 << 6)
  55 #define MCI_CMDSENT             (1 << 7)
  56 #define MCI_DATAEND             (1 << 8)
  57 #define MCI_DATABLOCKEND        (1 << 10)
  58 #define MCI_CMDACTIVE           (1 << 11)
  59 #define MCI_TXACTIVE            (1 << 12)
  60 #define MCI_RXACTIVE            (1 << 13)
  61 #define MCI_TXFIFOHALFEMPTY     (1 << 14)
  62 #define MCI_RXFIFOHALFFULL      (1 << 15)
  63 #define MCI_TXFIFOFULL          (1 << 16)
  64 #define MCI_RXFIFOFULL          (1 << 17)
  65 #define MCI_TXFIFOEMPTY         (1 << 18)
  66 #define MCI_RXFIFOEMPTY         (1 << 19)
  67 #define MCI_TXDATAAVLBL         (1 << 20)
  68 #define MCI_RXDATAAVLBL         (1 << 21)
  69
  70 //#define MMCICLEAR             0x038
  71 #define MCI_CMDCRCFAILCLR       (1 << 0)
  72 #define MCI_DATACRCFAILCLR      (1 << 1)
  73 #define MCI_CMDTIMEOUTCLR       (1 << 2)
  74 #define MCI_DATATIMEOUTCLR      (1 << 3)
  75 #define MCI_TXUNDERRUNCLR       (1 << 4)
  76 #define MCI_RXOVERRUNCLR        (1 << 5)
  77 #define MCI_CMDRESPENDCLR       (1 << 6)
  78 #define MCI_CMDSENTCLR          (1 << 7)
  79 #define MCI_DATAENDCLR          (1 << 8)
  80 #define MCI_DATABLOCKENDCLR     (1 << 10)
  81
  82 //#define MMCIMASK0             0x03c
  83 #define MCI_CMDCRCFAILMASK      (1 << 0)
  84 #define MCI_DATACRCFAILMASK     (1 << 1)
  85 #define MCI_CMDTIMEOUTMASK      (1 << 2)
  86 #define MCI_DATATIMEOUTMASK     (1 << 3)
  87 #define MCI_TXUNDERRUNMASK      (1 << 4)
  88 #define MCI_RXOVERRUNMASK       (1 << 5)
  89 #define MCI_CMDRESPENDMASK      (1 << 6)
  90 #define MCI_CMDSENTMASK         (1 << 7)
  91 #define MCI_DATAENDMASK         (1 << 8)
  92 #define MCI_DATABLOCKENDMASK    (1 << 10)
  93 #define MCI_CMDACTIVEMASK       (1 << 11)
  94 #define MCI_TXACTIVEMASK        (1 << 12)
  95 #define MCI_RXACTIVEMASK        (1 << 13)
  96 #define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
  97 #define MCI_RXFIFOHALFFULLMASK  (1 << 15)
  98 #define MCI_TXFIFOFULLMASK      (1 << 16)
  99 #define MCI_RXFIFOFULLMASK      (1 << 17)
 100 #define MCI_TXFIFOEMPTYMASK     (1 << 18)
 101 #define MCI_RXFIFOEMPTYMASK     (1 << 19)
 102 #define MCI_TXDATAAVLBLMASK     (1 << 20)
 103 #define MCI_RXDATAAVLBLMASK     (1 << 21)
 104
 105 #if 0
 106 #define MMCIMASK1               0x040
 107 #define MMCIFIFOCNT             0x048
 108 #define MMCIFIFO                0x080 /* to 0x0bc */
 109 #endif
 110
 111 #define MCI_IRQENABLE   \
 112         (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK|     \
 113         MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK|       \
 114         MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK)
 115
 116 /*
 117  * The size of the FIFO in bytes.
 118  */
 119 #define MCI_FIFOSIZE    (16*4)
 120
 121 #define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
 122
 123 #define NR_SG           16