firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "hotswap.h"
  27 #include "system.h"
  28 #include "kernel.h"
  29 #include "cpu.h"
  30 #include <stdio.h>
  31 #include <stdlib.h>
  32 #include <string.h>
  33 #include "as3525v2.h"
  34 #include "pl081.h"  /* DMA controller */
  35 #include "dma-target.h" /* DMA request lines */
  36 #include "clock-target.h"
  37 #include "panic.h"
  38 #include "stdbool.h"
  39 #include "ata_idle_notify.h"
  40 #include "sd.h"
  41
  42 #include "lcd.h"
  43 #include <stdarg.h>
  44 #include "sysfont.h"
  45
  46 /* command flags */
  47 #define MCI_NO_RESP     (0<<0)
  48 #define MCI_RESP        (1<<0)
  49 #define MCI_LONG_RESP   (1<<1)
  50
  51 /* controller registers */
  52 #define SD_BASE 0xC6070000
  53
  54 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  55
  56 #define MCI_CTRL        SD_REG(0x00)
  57
  58 /* control bits */
  59 #define CTRL_RESET      (1<<0)
  60 #define FIFO_RESET      (1<<1)
  61 #define DMA_RESET       (1<<2)
  62 #define INT_ENABLE      (1<<4)
  63 #define DMA_ENABLE      (1<<5)
  64 #define READ_WAIT       (1<<6)
  65 #define SEND_IRQ_RESP   (1<<7)
  66 #define ABRT_READ_DATA  (1<<8)
  67 #define SEND_CCSD       (1<<9)
  68 #define SEND_AS_CCSD    (1<<10)
  69 #define EN_OD_PULLUP    (1<<24)
  70
  71
  72 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  73
  74 #define PWR_CRD_0       (1<<0)
  75 #define PWR_CRD_1       (1<<1)
  76 #define PWR_CRD_2       (1<<2)
  77 #define PWR_CRD_3       (1<<3)
  78
  79 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  80 /* CLK_DIV_0 :    bits 7:0
  81  * CLK_DIV_1 :    bits 15:8
  82  * CLK_DIV_2 :    bits 23:16
  83  * CLK_DIV_3 :    bits 31:24
  84  */
  85
  86 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
  87 /* CLK_SRC_CRD0:  bits 1:0
  88  * CLK_SRC_CRD1:  bits 3:2
  89  * CLK_SRC_CRD2:  bits 5:4
  90  * CLK_SRC_CRD3:  bits 7:6
  91  */
  92
  93 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
  94
  95 #define CCLK_ENA_CRD0   (1<<0)
  96 #define CCLK_ENA_CRD1   (1<<1)
  97 #define CCLK_ENA_CRD2   (1<<2)
  98 #define CCLK_ENA_CRD3   (1<<3)
  99 #define CCLK_LP_CRD0    (1<<16)         /* LP --> Low Power Mode? */
 100 #define CCLK_LP_CRD1    (1<<17)
 101 #define CCLK_LP_CRD2    (1<<18)
 102 #define CCLK_LP_CRD3    (1<<19)
 103
 104 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
 105 /* response timeout bits 0:7
 106  * data timeout bits     8:31
 107  */
 108
 109 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
 110                                         /* 1 bit per card, set = wide bus */
 111 #define WIDTH4_CRD0     (1<<0)
 112 #define WIDTH4_CRD1     (1<<1)
 113 #define WIDTH4_CRD2     (1<<2)
 114 #define WIDTH4_CRD3     (1<<3)
 115
 116 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size  bits 0:15*/
 117 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count  bits 0:31*/
 118 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
 119
 120
 121
 122 #define MCI_ARGUMENT    SD_REG(0x28)
 123 #define MCI_COMMAND     SD_REG(0x2C)
 124
 125 /* command bits (bits 5:0 are the command index) */
 126 #define CMD_RESP_EXP_BIT        (1<<6)
 127 #define CMD_RESP_LENGTH_BIT     (1<<7)
 128 #define CMD_CHECK_CRC_BIT       (1<<8)
 129 #define CMD_DATA_EXP_BIT        (1<<9)
 130 #define CMD_RW_BIT              (1<<10)
 131 #define CMD_TRANSMODE_BIT       (1<<11)
 132 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
 133 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
 134 #define CMD_ABRT_CMD_BIT        (1<<14)
 135 #define CMD_SEND_INIT_BIT       (1<<15)
 136 #define CMD_SEND_CLK_ONLY       (1<<21)
 137 #define CMD_READ_CEATA          (1<<22)
 138 #define CMD_CCS_EXPECTED        (1<<23)
 139 #define CMD_DONE_BIT            (1<<31)
 140
 141
 142 #define MCI_RESP0       SD_REG(0x30)
 143 #define MCI_RESP1       SD_REG(0x34)
 144 #define MCI_RESP2       SD_REG(0x38)
 145 #define MCI_RESP3       SD_REG(0x3C)
 146
 147 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 148 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 149                                          * status clear */
 150
 151 /* interrupt bits */
 152 #define MCI_INT_CRDDET  (1<<0)      /* card detect */
 153 #define MCI_INT_RE      (1<<1)      /* response error */
 154 #define MCI_INT_CD      (1<<2)      /* command done */
 155 #define MCI_INT_DTO     (1<<3)      /* data transfer over */
 156 #define MCI_INT_TXDR    (1<<4)      /* tx fifo data request */
 157 #define MCI_INT_RXDR    (1<<5)      /* rx fifo data request */
 158 #define MCI_INT_RCRC    (1<<6)      /* response crc error */
 159 #define MCI_INT_DCRC    (1<<7)      /* data crc error */
 160 #define MCI_INT_RTO     (1<<8)      /* response timeout */
 161 #define MCI_INT_DRTO    (1<<9)      /* data read timeout */
 162 #define MCI_INT_HTO     (1<<10)     /* data starv timeout */
 163 #define MCI_INT_FRUN    (1<<11)     /* fifo over/underrun */
 164 #define MCI_INT_HLE     (1<<12)     /* hw locked while error */
 165 #define MCI_INT_SBE     (1<<13)     /* start bit error */
 166 #define MCI_INT_ACD     (1<<14)     /* auto command done */
 167 #define MCI_INT_EBE     (1<<15)     /* end bit error */
 168 #define MCI_INT_SDIO    (0xf<<16)
 169
 170 /*
 171  *  STATUS register
 172  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 173  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 174  *  & 8         = MCI_INT_DTO
 175  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 176  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 177  */
 178
 179 #define MCI_ERROR   (MCI_INT_RE | MCI_INT_RCRC | MCI_INT_DCRC /*| MCI_INT_RTO*/ \
 180                    | MCI_INT_DRTO | MCI_INT_HTO | MCI_INT_FRUN | MCI_INT_HLE \
 181                    | MCI_INT_SBE | MCI_INT_EBE)
 182
 183 #define MCI_STATUS      SD_REG(0x48)
 184
 185 #define FIFO_RX_WM              (1<<0)
 186 #define FIFO_TX_WM              (1<<1)
 187 #define FIFO_EMPTY              (1<<2)
 188 #define FIFO_FULL               (1<<3)
 189 #define CMD_FSM_STATE_B0        (1<<4)
 190 #define CMD_FSM_STATE_B1        (1<<5)
 191 #define CMD_FSM_STATE_B2        (1<<6)
 192 #define CMD_FSM_STATE_B3        (1<<7)
 193 #define DATA_3_STAT             (1<<8)
 194 #define DATA_BUSY               (1<<9)
 195 #define DATA_STAT_MC_BUSY       (1<<10)
 196 #define RESP_IDX_B0             (1<<11)
 197 #define RESP_IDX_B1             (1<<12)
 198 #define RESP_IDX_B2             (1<<13)
 199 #define RESP_IDX_B3             (1<<14)
 200 #define RESP_IDX_B4             (1<<15)
 201 #define RESP_IDX_B5             (1<<16)
 202 #define FIFO_CNT_B00            (1<<17)
 203 #define FIFO_CNT_B01            (1<<18)
 204 #define FIFO_CNT_B02            (1<<19)
 205 #define FIFO_CNT_B03            (1<<20)
 206 #define FIFO_CNT_B04            (1<<21)
 207 #define FIFO_CNT_B05            (1<<22)
 208 #define FIFO_CNT_B06            (1<<23)
 209 #define FIFO_CNT_B07            (1<<24)
 210 #define FIFO_CNT_B08            (1<<25)
 211 #define FIFO_CNT_B09            (1<<26)
 212 #define FIFO_CNT_B10            (1<<27)
 213 #define FIFO_CNT_B11            (1<<28)
 214 #define FIFO_CNT_B12            (1<<29)
 215 #define DMA_ACK                 (1<<30)
 216 #define START_CMD               (1<<31)
 217
 218 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 219 /* TX watermark :    bits 11:0
 220  * RX watermark :    bits 27:16
 221  * DMA MTRANS SIZE : bits 30:28
 222  * bits 31, 15:12 : unused
 223  */
 224 #define MCI_FIFOTH_MASK 0x8000f000
 225
 226 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 227
 228 #define CDETECT_CRD_0   (1<<0)
 229 #define CDETECT_CRD_1   (1<<1)
 230 #define CDETECT_CRD_2   (1<<2)
 231 #define CDETECT_CRD_3   (1<<3)
 232
 233 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 234 #define MCI_GPIO        SD_REG(0x58)
 235 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count (card)*/
 236 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes (FIFO)*/
 237 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce  bits 23:0*/
 238 #define MCI_USRID       SD_REG(0x68)    /* user id */
 239 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 240
 241 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 242 /* bit  0       : card type
 243  * bits 5:1     : maximum card index
 244  * bit  6       : BUS TYPE
 245  * bits 9:7     : DATA WIDTH
 246  * bits 15:10   : ADDR WIDTH
 247  * bits 17:16   : DMA IF
 248  * bits 20:18   : DMA WIDTH
 249  * bit  21      : FIFO RAM INSIDE
 250  * bit  22      : IMPL HOLD REG
 251  * bit  23      : SET CLK FALSE
 252  * bits 25:24   : MAX CLK DIV IDX
 253  * bit  26      : AREA OPTIM
 254  */
 255
 256 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 257 /* bit  0       : SWR
 258  * bit  1       : FB
 259  * bits 6:2     : DSL
 260  * bit  7       : DE
 261  * bit  10:8    : PBL
 262  */
 263
 264 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 265 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 266 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 267 /* bit  0       : TI
 268  * bit  1       : RI
 269  * bit  2       : FBE
 270  * bit  3       : unused
 271  * bit  4       : DU
 272  * bit  5       : CES
 273  * bits 7:6     : unused
 274  * bits 8       : NIS
 275  * bit  9       : AIS
 276  * bits 12:10   : EB
 277  * bits 16:13   : FSM
 278  */
 279
 280 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 281 /* bit  0       : TI
 282  * bit  1       : RI
 283  * bit  2       : FBE
 284  * bit  3       : unused
 285  * bit  4       : DU
 286  * bit  5       : CES
 287  * bits 7:6     : unused
 288  * bits 8       : NI
 289  * bit  9       : AI
 290  */
 291 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 292 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 293
 294 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 295
 296 #define UNALIGNED_NUM_SECTORS 10
 297 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 298 static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 299
 300 static int sd_init_card(void);
 301 static void init_controller(void);
 302
 303 static tCardInfo card_info;
 304
 305 /* for compatibility */
 306 static long last_disk_activity = -1;
 307
 308 #define MIN_YIELD_PERIOD 5  /* ticks */
 309 static long next_yield = 0;
 310
 311 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 312 static const char         sd_thread_name[] = "ata/sd";
 313 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 314 static struct event_queue sd_queue;
 315 #ifndef BOOTLOADER
 316 bool sd_enabled = false;
 317 #endif
 318
 319 static struct wakeup transfer_completion_signal;
 320 static volatile bool retry;
 321 static volatile bool data_transfer = false;
 322
 323 static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
 324
 325 void INT_NAND(void)
 326 {
 327     MCI_CTRL &= ~INT_ENABLE;
 328     const int status = MCI_MASK_STATUS;
 329
 330     MCI_RAW_STATUS = status;    /* clear status */
 331
 332     if(status & MCI_ERROR)
 333         retry = true;
 334
 335     if(data_transfer && status & (MCI_INT_DTO|MCI_ERROR))
 336         wakeup_signal(&transfer_completion_signal);
 337
 338     MCI_CTRL |= INT_ENABLE;
 339 }
 340
 341 static bool send_cmd(const int cmd, const int arg, const int flags,
 342         unsigned long *response)
 343 {
 344     MCI_COMMAND = cmd;
 345
 346     if(flags & MCI_RESP)
 347     {
 348         MCI_COMMAND |= CMD_RESP_EXP_BIT;
 349         if(flags & MCI_LONG_RESP)
 350             MCI_COMMAND |= CMD_RESP_LENGTH_BIT;
 351     }
 352
 353     if(cmd == SD_READ_MULTIPLE_BLOCK || cmd == SD_WRITE_MULTIPLE_BLOCK)
 354     {
 355         MCI_COMMAND |= CMD_WAIT_PRV_DAT_BIT | CMD_DATA_EXP_BIT;
 356         if(cmd == SD_WRITE_MULTIPLE_BLOCK)
 357             MCI_COMMAND |= CMD_RW_BIT | CMD_CHECK_CRC_BIT;
 358     }
 359
 360     int clkena = MCI_CLKENA;
 361     MCI_CLKENA = 0;
 362
 363     MCI_ARGUMENT = arg;
 364     MCI_COMMAND |= CMD_DONE_BIT;
 365
 366     int max = 0x40000;
 367     while(MCI_COMMAND & CMD_DONE_BIT)
 368     {
 369         if(--max == 0)  /* timeout */
 370         {
 371             MCI_CLKENA = clkena;
 372             return false;
 373         }
 374     }
 375
 376     MCI_CLKENA = clkena;
 377
 378     if(flags & MCI_RESP)
 379     {
 380         if(flags & MCI_LONG_RESP)
 381         {
 382             /* store the response in little endian order for the words */
 383             response[0] = MCI_RESP3;
 384             response[1] = MCI_RESP2;
 385             response[2] = MCI_RESP1;
 386             response[3] = MCI_RESP0;
 387         }
 388         else
 389             response[0] = MCI_RESP0;
 390     }
 391     return true;
 392 }
 393
 394 static int sd_init_card(void)
 395 {
 396     unsigned long response;
 397     unsigned long temp_reg[4];
 398     int max_tries = 100; /* max acmd41 attemps */
 399     bool sd_v2;
 400     int i;
 401
 402     /*  assume 24 MHz clock / 60 = 400 kHz  */
 403     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
 404
 405     if(!send_cmd(SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 406         return -1;
 407
 408     mci_delay();
 409
 410     sd_v2 = false;
 411     if(send_cmd(SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 412         if((response & 0xFFF) == 0x1AA)
 413             sd_v2 = true;
 414
 415     do {
 416         /* some MicroSD cards seems to need more delays, so play safe */
 417         mci_delay();
 418         mci_delay();
 419         mci_delay();
 420
 421         /* app_cmd */
 422         if( !send_cmd(SD_APP_CMD, 0, MCI_RESP, &response) ||
 423             !(response & (1<<5)))
 424         {
 425             return -2;
 426         }
 427
 428         /* acmd41 */
 429         if(!send_cmd(SD_APP_OP_COND, (sd_v2 ? 0x40FF8000 : (1<<23)),
 430                         MCI_RESP, &card_info.ocr))
 431             return -3;
 432     } while(!(card_info.ocr & (1<<31)) && max_tries--);
 433
 434     if(max_tries < 0)
 435         return -4;
 436
 437     mci_delay();
 438     mci_delay();
 439     mci_delay();
 440
 441     /* send CID */
 442     if(!send_cmd(SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info.cid))
 443         return -5;
 444
 445     /* send RCA */
 446     if(!send_cmd(SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info.rca))
 447         return -6;
 448
 449     /* send CSD */
 450     if(!send_cmd(SD_SEND_CSD, card_info.rca,
 451                  MCI_RESP|MCI_LONG_RESP, temp_reg))
 452         return -7;
 453
 454     for(i=0; i<4; i++)
 455         card_info.csd[3-i] = temp_reg[i];
 456
 457     sd_parse_csd(&card_info);
 458
 459     if(!send_cmd(SD_APP_CMD, 0, MCI_RESP, &response) ||
 460        !send_cmd(42, 0, MCI_NO_RESP, NULL)) /* disconnect the 50 KOhm pull-up
 461                                                resistor on CD/DAT3 */
 462         return -13;
 463
 464     if(!send_cmd(SD_APP_CMD, card_info.rca, MCI_NO_RESP, NULL))
 465         return -10;
 466
 467     if(!send_cmd(SD_SET_BUS_WIDTH, card_info.rca | 2, MCI_NO_RESP, NULL))
 468         return -11;
 469
 470     if(!send_cmd(SD_SELECT_CARD, card_info.rca, MCI_NO_RESP, NULL))
 471         return -9;
 472
 473     /* not sent in init_card() by OF */
 474     if(!send_cmd(SD_SET_BLOCKLEN, card_info.blocksize, MCI_NO_RESP,
 475                  NULL))
 476         return -12;
 477
 478     /*  Card back to full speed  */
 479     MCI_CLKDIV &= ~(0xFF);    /* CLK_DIV_0 : bits 7:0  */
 480
 481     card_info.initialized = 1;
 482
 483     return 0;
 484 }
 485
 486 static void sd_thread(void) __attribute__((noreturn));
 487 static void sd_thread(void)
 488 {
 489     struct queue_event ev;
 490     bool idle_notified = false;
 491
 492     while (1)
 493     {
 494         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 495
 496         switch ( ev.id )
 497         {
 498         case SYS_TIMEOUT:
 499             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 500             {
 501                 idle_notified = false;
 502             }
 503             else
 504             {
 505                 /* never let a timer wrap confuse us */
 506                 next_yield = current_tick;
 507
 508                 if (!idle_notified)
 509                 {
 510                     call_storage_idle_notifys(false);
 511                     idle_notified = true;
 512                 }
 513             }
 514             break;
 515 #if 0
 516         case SYS_USB_CONNECTED:
 517             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 518             /* Wait until the USB cable is extracted again */
 519             usb_wait_for_disconnect(&sd_queue);
 520
 521             break;
 522         case SYS_USB_DISCONNECTED:
 523             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 524             break;
 525 #endif
 526         }
 527     }
 528 }
 529
 530 static void init_controller(void)
 531 {
 532
 533     int temp = MCI_HCON;                   /* we just need to read HCON */
 534     (void)temp;
 535 //    panicf("HCON: %8x",temp);
 536 //    int idx = (MCI_HCON >> 1) & 31;      /* Maximum card Index */
 537 //    int idx_bits = (1 << idx) -1;
 538
 539     MCI_PWREN = 0x0;                       /*  power off all cards  */
 540
 541     MCI_CLKSRC = 0x00;                     /* All CLK_SRC_CRD set to 0*/
 542     MCI_CLKDIV = 0x00;                     /* CLK_DIV_0 : bits 7:0  */
 543
 544     MCI_PWREN = PWR_CRD_0;                 /*  power up card 0 (internal)  */
 545     mci_delay();
 546
 547     MCI_CTRL |= CTRL_RESET;
 548     while(MCI_CTRL & CTRL_RESET)
 549         ;
 550
 551     MCI_RAW_STATUS = 0xffffffff;
 552
 553     MCI_TMOUT = 0xffffffff;             /*  data b31:8, response b7:0 */
 554
 555     MCI_CTYPE = 0x0;                    /*  all cards 1 bit bus for now */
 556
 557     MCI_CLKENA = CCLK_ENA_CRD0;
 558
 559     MCI_ARGUMENT = 0;
 560     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 561     while(MCI_COMMAND & CMD_DONE_BIT)
 562         ;
 563
 564     MCI_DEBNCE = 0xfffff;   /* default value */
 565
 566     MCI_FIFOTH &= MCI_FIFOTH_MASK;
 567     MCI_FIFOTH |= 0x503f0080;
 568
 569     MCI_MASK = 0xffffffff & ~(MCI_INT_ACD|MCI_INT_CRDDET);
 570
 571     MCI_CTRL |= INT_ENABLE;
 572 }
 573
 574 int sd_init(void)
 575 {
 576     int ret;
 577     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 578
 579     CGU_IDE =   (1<<7)  /* AHB interface enable */  |
 580                 (1<<6)  /* interface enable */      |
 581                 ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) << 2) |
 582                 1;       /* clock source = PLLA */
 583
 584     CGU_MEMSTICK = (1<<8) | (1<<7) |
 585         ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) << 2) | 1;
 586
 587     /* FIXME: divider should be shifted by 2, but doing prevents card
 588      * initialisation */
 589     *(volatile int*)(CGU_BASE+0x3C) = (1<<7) |
 590         (CLK_DIV(AS3525_PLLA_FREQ, 24000000) -1) | 1;
 591
 592     wakeup_init(&transfer_completion_signal);
 593
 594     VIC_INT_ENABLE |= INTERRUPT_NAND;
 595
 596     init_controller();
 597     ret = sd_init_card();
 598     if(ret < 0)
 599         return ret;
 600
 601     /* init mutex */
 602     mutex_init(&sd_mtx);
 603
 604     queue_init(&sd_queue, true);
 605     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 606             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 607
 608 #ifndef BOOTLOADER
 609     sd_enabled = true;
 610     sd_enable(false);
 611 #endif
 612     return 0;
 613 }
 614
 615 #ifdef STORAGE_GET_INFO
 616 void sd_get_info(struct storage_info *info)
 617 {
 618     info->sector_size=card_info.blocksize;
 619     info->num_sectors=card_info.numblocks;
 620     info->vendor="Rockbox";
 621     info->product = "Internal Storage";
 622     info->revision="0.00";
 623 }
 624 #endif
 625
 626 static int sd_wait_for_state(unsigned int state)
 627 {
 628     unsigned long response;
 629     unsigned int timeout = 100; /* ticks */
 630     long t = current_tick;
 631
 632     while (1)
 633     {
 634         long tick;
 635
 636         if(!send_cmd(SD_SEND_STATUS, card_info.rca,
 637                     MCI_RESP, &response))
 638             return -1;
 639
 640         if (((response >> 9) & 0xf) == state)
 641             return 0;
 642
 643         if(TIME_AFTER(current_tick, t + timeout))
 644             return -10 * ((response >> 9) & 0xf);
 645
 646         if (TIME_AFTER((tick = current_tick), next_yield))
 647         {
 648             yield();
 649             timeout += current_tick - tick;
 650             next_yield = tick + MIN_YIELD_PERIOD;
 651         }
 652     }
 653 }
 654
 655 static int sd_transfer_sectors(unsigned long start, int count, void* buf, bool write)
 656 {
 657     int ret = 0;
 658
 659     /* skip SanDisk OF */
 660     start += 0xf000;
 661
 662     mutex_lock(&sd_mtx);
 663 #ifndef BOOTLOADER
 664     sd_enable(true);
 665 #endif
 666
 667     if (card_info.initialized <= 0)
 668     {
 669         ret = sd_init_card();
 670         if (!(card_info.initialized))
 671         {
 672             panicf("card not initialised (%d)", ret);
 673             goto sd_transfer_error;
 674         }
 675     }
 676
 677     last_disk_activity = current_tick;
 678     ret = sd_wait_for_state(SD_TRAN);
 679     if (ret < 0)
 680     {
 681         static const char *st[9] = {
 682             "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV", "PRG", "DIS"
 683         };
 684         if(ret <= -10)
 685             panicf("wait for state failed (%s)", st[(-ret / 10) % 9]);
 686         else
 687             panicf("wait for state failed");
 688         goto sd_transfer_error;
 689     }
 690
 691     dma_retain();
 692
 693     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 694
 695     /* Interrupt handler might set this to true during transfer */
 696     do
 697     {
 698         void *dma_buf = aligned_buffer;
 699         unsigned int transfer = count;
 700         if(transfer > UNALIGNED_NUM_SECTORS)
 701             transfer = UNALIGNED_NUM_SECTORS;
 702
 703         if(write)
 704             memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 705
 706         retry = false;
 707
 708         MCI_BLKSIZ = SD_BLOCK_SIZE;
 709         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
 710
 711         MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 712         while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 713             ;
 714
 715         MCI_CTRL |= DMA_ENABLE;
 716         MCI_MASK = MCI_INT_CD|MCI_INT_DTO|MCI_INT_DCRC|MCI_INT_DRTO| \
 717             MCI_INT_HTO|MCI_INT_FRUN|MCI_INT_HLE|MCI_INT_SBE|MCI_INT_EBE;
 718
 719         MCI_FIFOTH &= MCI_FIFOTH_MASK;
 720         MCI_FIFOTH |= 0x503f0080;
 721
 722
 723         if(card_info.ocr & (1<<30) ) /* SDHC */
 724             ret = send_cmd(cmd, start, MCI_NO_RESP, NULL);
 725         else
 726             ret = send_cmd(cmd, start * SD_BLOCK_SIZE,
 727                     MCI_NO_RESP, NULL);
 728
 729         if (ret < 0)
 730             panicf("transfer multiple blocks failed (%d)", ret);
 731
 732         if(write)
 733             dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
 734                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 735         else
 736             dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
 737                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 738
 739         data_transfer = true;
 740         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 741         data_transfer = false;
 742
 743         last_disk_activity = current_tick;
 744
 745         if(!send_cmd(SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
 746         {
 747             ret = -666;
 748             panicf("STOP TRANSMISSION failed");
 749             goto sd_transfer_error;
 750         }
 751
 752         ret = sd_wait_for_state(SD_TRAN);
 753         if (ret < 0)
 754         {
 755             panicf(" wait for state TRAN failed (%d)", ret);
 756             goto sd_transfer_error;
 757         }
 758
 759         if(!retry)
 760         {
 761             if(!write)
 762                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 763             buf += transfer * SD_BLOCK_SIZE;
 764             start += transfer;
 765             count -= transfer;
 766         }
 767     } while(retry || count);
 768
 769     dma_release();
 770
 771 #ifndef BOOTLOADER
 772     sd_enable(false);
 773 #endif
 774     mutex_unlock(&sd_mtx);
 775     return 0;
 776
 777 sd_transfer_error:
 778     panicf("transfer error : %d",ret);
 779     card_info.initialized = 0;
 780     return ret;
 781 }
 782
 783 int sd_read_sectors(unsigned long start, int count, void* buf)
 784 {
 785     return sd_transfer_sectors(start, count, buf, false);
 786 }
 787
 788 int sd_write_sectors(unsigned long start, int count, const void* buf)
 789 {
 790 #if 1 /* disabled until stable*/ \
 791     || defined(BOOTLOADER) /* we don't need write support in bootloader */
 792     (void) start;
 793     (void) count;
 794     (void) buf;
 795     return -1;
 796 #else
 797     return sd_transfer_sectors(start, count, (void*)buf, true);
 798 #endif
 799 }
 800
 801 #ifndef BOOTLOADER
 802 long sd_last_disk_activity(void)
 803 {
 804     return last_disk_activity;
 805 }
 806
 807 void sd_enable(bool on)
 808 {
 809     /* TODO */
 810     (void)on;
 811     return;
 812 }
 813
 814 tCardInfo *card_get_info_target(int card_no)
 815 {
 816     (void)card_no;
 817     return &card_info;
 818 }
 819
 820 #endif /* BOOTLOADER */