firmware/target/arm/s3c2440/system-target.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by Greg White
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef SYSTEM_TARGET_H
  22 #define SYSTEM_TARGET_H
  23
  24 #include "system-arm.h"
  25 #include "mmu-arm.h"
  26
  27 /* NB: These values must match the register settings in s3c2440/crt0.S */
  28
  29 #ifdef GIGABEAT_F
  30     #define CPUFREQ_DEFAULT 98784000
  31     #define CPUFREQ_NORMAL  98784000
  32     #define CPUFREQ_MAX    296352000
  33
  34     /* Uses 1:3:6 */
  35     #define FCLK    CPUFREQ_MAX
  36     #define HCLK    (FCLK/3)   /* = 98,784,000 */
  37     #define PCLK    (HCLK/2)   /* = 49,392,000 */
  38
  39     #ifdef BOOTLOADER
  40         /* All addresses within rockbox are in IRAM in the bootloader so
  41            are therefore uncached */
  42         #define UNCACHED_ADDR(a) (a)
  43     #else /* !BOOTLOADER */
  44         #define UNCACHED_BASE_ADDR 0x30000000
  45         #define UNCACHED_ADDR(a)  ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))
  46     #endif /* BOOTLOADER */
  47
  48 #elif defined(MINI2440)
  49
  50     /* Uses 1:4:8 */
  51     #define FCLK 406000000
  52     #define HCLK (FCLK/4)   /* = 101,250,000 */
  53     #define PCLK (HCLK/2)   /* =  50,625,000 */
  54
  55     #define CPUFREQ_DEFAULT FCLK    /* 406 MHz */
  56     #define CPUFREQ_NORMAL  (FCLK/4)/* 101.25 MHz */
  57     #define CPUFREQ_MAX     FCLK    /* 406 MHz */
  58
  59     #define UNCACHED_BASE_ADDR 0x30000000
  60     #define UNCACHED_ADDR(a)  ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))
  61
  62 #else
  63     #error Unknown target
  64 #endif
  65
  66
  67 void system_prepare_fw_start(void);
  68 void tick_stop(void);
  69
  70 /* Functions to set and clear register bits atomically */
  71
  72 /* Set and clear register bits */
  73 void s3c_regmod32(volatile unsigned long *reg, unsigned long bits,
  74                   unsigned long mask);
  75 /* Set register bits */
  76 void s3c_regset32(volatile unsigned long *reg, unsigned long bits);
  77 /* Clear register bits */
  78 void s3c_regclr32(volatile unsigned long *reg, unsigned long bits);
  79
  80 #endif /* SYSTEM_TARGET_H */