firmware/target/arm/as3525/system-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by Rob Purchase
  11  * Copyright © 2008 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h"
  24 #include "kernel.h"
  25 #include "system.h"
  26 #include "panic.h"
  27 #include "ascodec-target.h"
  28 #include "adc.h"
  29 #include "dma-target.h"
  30 #include "clock-target.h"
  31 #include "fmradio_i2c.h"
  32 #include "button-target.h"
  33 #ifndef BOOTLOADER
  34 #include "mmu-arm.h"
  35 #endif
  36 #include "backlight-target.h"
  37
  38 #define default_interrupt(name) \
  39   extern __attribute__((weak,alias("UIRQ"))) void name (void)
  40
  41 void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
  42 void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
  43
  44 default_interrupt(INT_WATCHDOG);
  45 default_interrupt(INT_TIMER1);
  46 default_interrupt(INT_TIMER2);
  47 default_interrupt(INT_USB);
  48 default_interrupt(INT_DMAC);
  49 default_interrupt(INT_NAND);
  50 default_interrupt(INT_IDE);
  51 default_interrupt(INT_MCI0);
  52 default_interrupt(INT_MCI1);
  53 default_interrupt(INT_AUDIO);
  54 default_interrupt(INT_SSP);
  55 default_interrupt(INT_I2C_MS);
  56 default_interrupt(INT_I2C_AUDIO);
  57 default_interrupt(INT_I2SIN);
  58 default_interrupt(INT_I2SOUT);
  59 default_interrupt(INT_UART);
  60 default_interrupt(INT_GPIOD);
  61 default_interrupt(RESERVED1); /* Interrupt 17 : unused */
  62 default_interrupt(INT_CGU);
  63 default_interrupt(INT_MEMORY_STICK);
  64 default_interrupt(INT_DBOP);
  65 default_interrupt(RESERVED2); /* Interrupt 21 : unused */
  66 default_interrupt(RESERVED3); /* Interrupt 22 : unused */
  67 default_interrupt(RESERVED4); /* Interrupt 23 : unused */
  68 default_interrupt(RESERVED5); /* Interrupt 24 : unused */
  69 default_interrupt(RESERVED6); /* Interrupt 25 : unused */
  70 default_interrupt(RESERVED7); /* Interrupt 26 : unused */
  71 default_interrupt(RESERVED8); /* Interrupt 27 : unused */
  72 default_interrupt(RESERVED9); /* Interrupt 28 : unused */
  73 /* INT_GPIOA is declared in this file */
  74 void INT_GPIOA(void);
  75 default_interrupt(INT_GPIOB);
  76 default_interrupt(INT_GPIOC);
  77
  78 static const char * const irqname[] =
  79 {
  80     "INT_WATCHDOG", "INT_TIMER1", "INT_TIMER2", "INT_USB", "INT_DMAC", "INT_NAND",
  81     "INT_IDE", "INT_MCI0", "INT_MCI1", "INT_AUDIO", "INT_SSP", "INT_I2C_MS",
  82     "INT_I2C_AUDIO", "INT_I2SIN", "INT_I2SOUT", "INT_UART", "INT_GPIOD", "RESERVED1",
  83     "INT_CGU", "INT_MEMORY_STICK", "INT_DBOP", "RESERVED2", "RESERVED3", "RESERVED4",
  84     "RESERVED5", "RESERVED6", "RESERVED7", "RESERVED8", "RESERVED9", "INT_GPIOA",
  85     "INT_GPIOB", "INT_GPIOC"
  86 };
  87
  88 static void UIRQ(void)
  89 {
  90     unsigned int irq_no = 0;
  91     int status = VIC_IRQ_STATUS;
  92
  93     if(status == 0)
  94         panicf("Unhandled IRQ (source unknown!)");
  95
  96     while((status >>= 1))
  97         irq_no++;
  98
  99     panicf("Unhandled IRQ %02X: %s", irq_no, irqname[irq_no]);
 100 }
 101
 102 struct vec_int_src
 103 {
 104     int source;
 105     void (*isr) (void);
 106 };
 107
 108 /* Vectored interrupts (16 available) */
 109 struct vec_int_src vec_int_srcs[] =
 110 {
 111     { INT_SRC_TIMER1, INT_TIMER1 },
 112     { INT_SRC_TIMER2, INT_TIMER2 },
 113     { INT_SRC_DMAC, INT_DMAC },
 114     { INT_SRC_NAND, INT_NAND },
 115     { INT_SRC_I2C_AUDIO, INT_I2C_AUDIO },
 116     { INT_SRC_AUDIO, INT_AUDIO },
 117     { INT_SRC_USB, INT_USB, },
 118 #if (defined HAVE_MULTIDRIVE  && CONFIG_CPU == AS3525)
 119     { INT_SRC_MCI0, INT_MCI0 },
 120 #endif
 121 #ifdef HAVE_HOTSWAP
 122     { INT_SRC_GPIOA, INT_GPIOA, },
 123 #endif
 124 #ifdef HAVE_RECORDING
 125     { INT_SRC_I2SIN, INT_I2SIN, },
 126 #endif
 127 };
 128
 129 static void setup_vic(void)
 130 {
 131     volatile unsigned long *vic_vect_addrs = VIC_VECT_ADDRS;
 132     volatile unsigned long *vic_vect_cntls = VIC_VECT_CNTLS;
 133     const unsigned int n = sizeof(vec_int_srcs)/sizeof(vec_int_srcs[0]);
 134     unsigned int i;
 135
 136     CGU_PERI |= CGU_VIC_CLOCK_ENABLE; /* enable VIC */
 137     VIC_INT_EN_CLEAR = 0xffffffff; /* disable all interrupt lines */
 138     VIC_INT_SELECT = 0; /* only IRQ, no FIQ */
 139
 140     VIC_DEF_VECT_ADDR = (unsigned long)UIRQ;
 141
 142     for(i = 0; i < n; i++)
 143     {
 144         vic_vect_addrs[i] = (unsigned long)vec_int_srcs[i].isr;
 145         vic_vect_cntls[i] = (1<<5) | vec_int_srcs[i].source;
 146     }
 147 }
 148
 149 void INT_GPIOA(void)
 150 {
 151 #ifdef HAVE_MULTIDRIVE
 152     void sd_gpioa_isr(void);
 153     sd_gpioa_isr();
 154 #endif
 155 #if (defined(HAVE_SCROLLWHEEL) && CONFIG_CPU != AS3525)
 156     void button_gpioa_isr(void);
 157     button_gpioa_isr();
 158 #endif
 159 }
 160
 161 void irq_handler(void)
 162 {
 163     asm volatile(   "stmfd  sp!, {r0-r5,ip,lr}      \n" /* Store context */
 164                     "ldr    r5, =0xC6010030         \n" /* VIC_VECT_ADDR */
 165                     "mov    lr, pc                  \n" /* Return from ISR */
 166                     "ldr    pc, [r5]                \n" /* execute ISR */
 167                     "str    r0, [r5]                \n" /* Ack interrupt */
 168                     "ldmfd  sp!, {r0-r5,ip,lr}      \n" /* Restore context */
 169                     "subs   pc, lr, #4              \n" /* Return from IRQ */
 170             );
 171 }
 172
 173 void fiq_handler(void)
 174 {
 175     asm volatile (
 176         "subs   pc, lr, #4   \r\n"
 177     );
 178 }
 179
 180 #if defined(SANSA_C200V2)
 181 #include "dbop-as3525.h"
 182
 183 int c200v2_variant = 0;
 184
 185 static void check_model_variant(void)
 186 {
 187     unsigned int i;
 188     unsigned int saved_dir = GPIOA_DIR;
 189
 190     /* Make A7 input */
 191     GPIOA_DIR &= ~(1<<7);
 192     /* wait a little to allow the pullup/pulldown resistor
 193      * to charge the input capacitance */
 194     for (i=0; i<1000; i++) asm volatile ("nop\n");
 195     /* read the pullup/pulldown value on A7 to determine the variant */
 196     if (GPIOA_PIN(7) == 0) {
 197         /*
 198          * Backlight on A7.
 199          */
 200         c200v2_variant = 1;
 201     } else {
 202         /*
 203          * Backlight on A5.
 204          */
 205         c200v2_variant = 0;
 206     }
 207     GPIOA_DIR = saved_dir;
 208 }
 209 #else
 210 static inline void check_model_variant(void)
 211 {
 212 }
 213 #endif /* SANSA_C200V2*/
 214
 215 #if defined(BOOTLOADER)
 216 static void sdram_delay(void)
 217 {
 218     int delay = 1024; /* arbitrary */
 219     while (delay--) ;
 220 }
 221
 222 /* Use the same initialization than OF */
 223 static void sdram_init(void)
 224 {
 225     CGU_PERI |= (CGU_EXTMEM_CLOCK_ENABLE|CGU_EXTMEMIF_CLOCK_ENABLE);
 226
 227     MPMC_CONTROL = 0x1; /* enable MPMC */
 228
 229     MPMC_DYNAMIC_CONTROL = 0x183; /* SDRAM NOP, all clocks high */
 230     sdram_delay();
 231
 232     MPMC_DYNAMIC_CONTROL = 0x103; /* SDRAM PALL, all clocks high */
 233     sdram_delay();
 234
 235     MPMC_DYNAMIC_REFRESH = 0x138; /* 0x138 * 16 HCLK ticks between SDRAM refresh cycles */
 236
 237     MPMC_CONFIG = 0; /* little endian, HCLK:MPMCCLKOUT[3:0] ratio = 1:1 */
 238
 239     if(MPMC_PERIPH_ID2 & 0xf0)
 240         MPMC_DYNAMIC_READ_CONFIG = 0x1; /* command delayed, clock out not delayed */
 241
 242     /* timings */
 243     MPMC_DYNAMIC_tRP    = 2;
 244     MPMC_DYNAMIC_tRAS   = 4;
 245     MPMC_DYNAMIC_tSREX  = 5;
 246     MPMC_DYNAMIC_tAPR   = 0;
 247     MPMC_DYNAMIC_tDAL   = 4;
 248     MPMC_DYNAMIC_tWR    = 2;
 249     MPMC_DYNAMIC_tRC    = 5;
 250     MPMC_DYNAMIC_tRFC   = 5;
 251     MPMC_DYNAMIC_tXSR   = 5;
 252     MPMC_DYNAMIC_tRRD   = 2;
 253     MPMC_DYNAMIC_tMRD   = 2;
 254
 255 #if defined(SANSA_CLIP) || defined(SANSA_M200V4) || defined(SANSA_C200V2)
 256 /* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */
 257 #define MEMORY_MODEL 0x21
 258
 259 #elif defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_CLIPV2) \
 260     || defined(SANSA_CLIPPLUS) || defined(SANSA_FUZEV2)
 261 /* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */
 262 #define MEMORY_MODEL 0x5
 263
 264 #else
 265 #error "The external memory in your player is unknown"
 266 #endif
 267
 268     MPMC_DYNAMIC_RASCAS_0 = (2<<8)|2; /* CAS & RAS latency = 2 clock cycles */
 269     MPMC_DYNAMIC_CONFIG_0 = (MEMORY_MODEL << 7);
 270
 271     MPMC_DYNAMIC_RASCAS_1 = MPMC_DYNAMIC_CONFIG_1 =
 272     MPMC_DYNAMIC_RASCAS_2 = MPMC_DYNAMIC_CONFIG_2 =
 273     MPMC_DYNAMIC_RASCAS_3 = MPMC_DYNAMIC_CONFIG_3 = 0;
 274
 275     MPMC_DYNAMIC_CONTROL = 0x82; /* SDRAM MODE, MPMCCLKOUT runs continuously */
 276
 277     /* program the SDRAM mode register */
 278     /* FIXME: details the exact settings of mode register */
 279     asm volatile(
 280         "ldr r4, [%0]\n"
 281         : : "p"(0x30000000+0x2300*MEM) : "r4");
 282
 283     /* SDRAM NORMAL, MPMCCLKOUT stopped when SDRAM is idle */
 284     MPMC_DYNAMIC_CONTROL = 0x0;
 285
 286     MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */
 287 }
 288 #endif /* BOOTLOADER */
 289
 290 void system_init(void)
 291 {
 292 #if CONFIG_CPU == AS3525v2
 293     CCU_SRC = 0x57D7BF0;
 294 #else
 295     CCU_SRC = 0x1fffff0
 296         & ~CCU_SRC_IDE_EN; /* FIXME */
 297 #endif
 298
 299     unsigned int reset_loops = 640;
 300     while(reset_loops--)
 301         CCU_SRL = CCU_SRL_MAGIC_NUMBER;
 302     CCU_SRC = CCU_SRL = 0;
 303
 304     CCU_SCON = 1; /* AHB master's priority configuration :
 305                      TIC (Test Interface Controller) > DMA > USB > IDE > ARM */
 306
 307     CGU_PROC = 0;           /* fclk 24 MHz */
 308 #if CONFIG_CPU == AS3525v2
 309     /* pclk is always based on PLLA, since we don't know the current PLLA speed,
 310      * avoid having pclk too fast and hope it's not too low */
 311     CGU_PERI |= 0xf << 2;   /* pclk lowest */
 312 #else
 313     CGU_PERI &= ~0x7f;      /* pclk 24 MHz */
 314 #endif
 315
 316     /* bits 31:30 should be set to 0 in arm926-ejs */
 317     asm volatile(
 318         "mrc p15, 0, r0, c1, c0   \n"      /* control register */
 319         "bic r0, r0, #3<<30       \n"      /* clears bus bits : sets fastbus */
 320         "mcr p15, 0, r0, c1, c0   \n"
 321         : : : "r0" );
 322
 323     CGU_COUNTA = 0xff;
 324     CGU_PLLA = AS3525_PLLA_SETTING;
 325     CGU_PLLASUP = 0;        /* enable PLLA */
 326     while(!(CGU_INTCTRL & (1<<0)));           /* wait until PLLA is locked */
 327
 328 #if defined(USE_ROCKBOX_USB) || (AS3525_MCLK_SEL == AS3525_CLK_PLLB)
 329     CGU_COUNTB = 0xff;
 330     CGU_PLLB = AS3525_PLLB_SETTING;
 331     CGU_PLLBSUP = 0;        /* enable PLLB */
 332     while(!(CGU_INTCTRL & (1<<1)));           /* wait until PLLB is locked */
 333 #endif
 334
 335     /*  Set FCLK frequency */
 336     CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
 337                 (AS3525_FCLK_PREDIV  << 2) |
 338                  AS3525_FCLK_SEL);
 339
 340     /*  Set PCLK frequency */
 341     CGU_PERI = ((CGU_PERI & ~0x7F)  |       /* reset divider & clksel bits */
 342                  (AS3525_PCLK_DIV0 << 2) |
 343 #if CONFIG_CPU == AS3525
 344                  (AS3525_PCLK_DIV1 << 6) |
 345 #endif
 346                   AS3525_PCLK_SEL);
 347
 348 #if defined(BOOTLOADER)
 349     sdram_init();
 350 #elif defined(SANSA_FUZE) || defined(SANSA_CLIP) || defined(SANSA_E200V2)
 351     /* XXX: remove me when we have a new bootloader */
 352     MPMC_DYNAMIC_CONTROL = 0x0; /* MPMCCLKOUT stops when all SDRAMs are idle */
 353 #endif  /* BOOTLOADER */
 354
 355 #if 0 /* the GPIO clock is already enabled by the dualboot function */
 356     CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
 357 #endif
 358
 359     /* enable timer interface for TIMER1 & TIMER2 */
 360     CGU_PERI |= CGU_TIMERIF_CLOCK_ENABLE;
 361
 362     setup_vic();
 363
 364     dma_init();
 365
 366     ascodec_init();
 367
 368 #ifndef BOOTLOADER
 369     /* setup isr for microsd monitoring and for scrollwheel irq */
 370 #if defined(HAVE_MULTIDRIVE) || (defined(HAVE_SCROLLWHEEL) && CONFIG_CPU != AS3525)
 371     VIC_INT_ENABLE = (INTERRUPT_GPIOA);
 372     /* pin selection for irq happens in the drivers */
 373 #endif
 374
 375     /*  Initialize power management settings */
 376     ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING);
 377 #if CONFIG_TUNER
 378     fmradio_i2c_init();
 379 #endif
 380 #endif /* !BOOTLOADER */
 381     check_model_variant();
 382 }
 383
 384 void system_reboot(void)
 385 {
 386     _backlight_off();
 387     /* use watchdog to reset */
 388     CGU_PERI |= (CGU_WDOCNT_CLOCK_ENABLE | CGU_WDOIF_CLOCK_ENABLE);
 389     WDT_LOAD = 1; /* set counter to 1 */
 390     WDT_CONTROL = 3; /* enable watchdog counter & reset */
 391     while(1);
 392 }
 393
 394 void system_exception_wait(void)
 395 {
 396     /* wait until button release (if a button is pressed) */
 397     while(button_read_device());
 398     /* then wait until next button press */
 399     while(!button_read_device());
 400 }
 401
 402 int system_memory_guard(int newmode)
 403 {
 404     (void)newmode;
 405     return 0;
 406 }
 407
 408 #ifndef BOOTLOADER
 409 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 410
 411 #if CONFIG_CPU == AS3525
 412 void set_cpu_frequency(long frequency)
 413 {
 414     if(frequency == CPUFREQ_MAX)
 415     {
 416 #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
 417         /* Increasing frequency so boost voltage before change */
 418         ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20));
 419
 420         /* Some players run a bit low so use 1.175 volts instead of 1.20  */
 421         /* Wait for voltage to be at least 1.175v before making fclk > 200 MHz */
 422         while(adc_read(ADC_CVDD) < 470); /* 470 * .0025 = 1.175V */
 423 #endif  /*  HAVE_ADJUSTABLE_CPU_VOLTAGE */
 424
 425         asm volatile(
 426             "mrc p15, 0, r0, c1, c0  \n"
 427
 428 #ifdef ASYNCHRONOUS_BUS
 429             "orr r0, r0, #3<<30      \n"   /* asynchronous bus clocking */
 430 #else
 431             "bic r0, r0, #3<<30      \n"   /* clear bus bits */
 432             "orr r0, r0, #1<<30      \n"   /* synchronous bus clocking */
 433 #endif
 434
 435             "mcr p15, 0, r0, c1, c0  \n"
 436             : : : "r0" );
 437
 438         cpu_frequency = CPUFREQ_MAX;
 439     }
 440     else
 441     {
 442         asm volatile(
 443             "mrc p15, 0, r0, c1, c0  \n"
 444             "bic r0, r0, #3<<30      \n"     /* fastbus clocking */
 445             "mcr p15, 0, r0, c1, c0  \n"
 446             : : : "r0" );
 447
 448
 449 #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
 450         /* Decreasing frequency so reduce voltage after change */
 451         ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10));
 452 #endif  /*  HAVE_ADJUSTABLE_CPU_VOLTAGE */
 453
 454         cpu_frequency = CPUFREQ_NORMAL;
 455     }
 456 }
 457 #else   /* as3525v2  */
 458 /* FIXME : disabled for now, seems to cause buggy memory accesses
 459  * Disabling MMU or putting the function in uncached memory seems to help? */
 460 void set_cpu_frequency(long frequency)
 461 {
 462     int oldstatus = disable_irq_save();
 463
 464     /* We only have 2 settings */
 465     cpu_frequency = (frequency == CPUFREQ_MAX) ? frequency : CPUFREQ_NORMAL;
 466
 467     if(frequency == CPUFREQ_MAX)
 468     {
 469         /* Change PCLK while FCLK is low, so it doesn't go too high */
 470         CGU_PERI = (CGU_PERI & ~(0xF << 2)) | (AS3525_PCLK_DIV0 << 2);
 471
 472         CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
 473                     (AS3525_FCLK_PREDIV  << 2) |
 474                     AS3525_FCLK_SEL);
 475     }
 476     else
 477     {
 478         CGU_PROC = ((AS3525_FCLK_POSTDIV_UNBOOSTED << 4) |
 479                     (AS3525_FCLK_PREDIV  << 2) |
 480                     AS3525_FCLK_SEL);
 481
 482         /* Change PCLK after FCLK is low, so it doesn't go too high */
 483         CGU_PERI = (CGU_PERI & ~(0xF << 2)) | (AS3525_PCLK_DIV0_UNBOOSTED << 2);
 484     }
 485
 486     restore_irq(oldstatus);
 487 }
 488 #endif
 489
 490 #endif /* HAVE_ADJUSTABLE_CPU_FREQ */
 491 #endif /* !BOOTLOADER */