firmware/target/arm/as3525/debug-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2008 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include <stdbool.h>
  23 #include "debug-target.h"
  24 #include "button.h"
  25 #include "lcd.h"
  26 #include "font.h"
  27 #include "system.h"
  28 #include "cpu.h"
  29 #include "pl180.h"
  30 #include "ascodec-target.h"
  31 #include "adc.h"
  32 #include "storage.h"
  33
  34 #define ON "Enabled"
  35 #define OFF "Disabled"
  36
  37 #define CP15_MMU (1<<0)            /* mmu off/on */
  38 #define CP15_DC  (1<<2)            /* dcache off/on */
  39 #define CP15_IC  (1<<12)           /* icache off/on */
  40
  41 #define CLK_MAIN         24000000     /* 24 MHz  */
  42
  43 #define CLK_PLLA             0
  44 #define CLK_PLLB             1
  45 #define CLK_PROC             2
  46 #define CLK_FCLK             3
  47 #define CLK_EXTMEM           4
  48 #define CLK_PCLK             5
  49 #define CLK_IDE              6
  50 #define CLK_I2C              7
  51 #define CLK_I2SI             8
  52 #define CLK_I2SO             9
  53 #define CLK_DBOP             10
  54 #define CLK_SD_MCLK_NAND     11
  55 #define CLK_SD_MCLK_MSD      12
  56 #define CLK_USB              13
  57
  58 #define I2C2_CPSR0      *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x1C))
  59 #define I2C2_CPSR1      *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x20))
  60 #define MCI_NAND        *((volatile unsigned long *)(NAND_FLASH_BASE + 0x04))
  61 #define MCI_SD          *((volatile unsigned long *)(SD_MCI_BASE + 0x04))
  62
  63 extern bool sd_enabled;
  64
  65 /* FIXME: target tree is including ./debug-target.h rather than the one in
  66  * sansa-fuze/, even though deps contains the correct one
  67  * if I put the below into a sansa-fuze/debug-target.h, it doesn't work*/
  68 #if defined(SANSA_FUZE) || defined(SANSA_E200V2) || defined(SANSA_C200V2)
  69 #define DEBUG_DBOP
  70 #include "dbop-as3525.h"
  71 #endif
  72
  73 static inline unsigned read_cp15 (void)
  74 {
  75     unsigned cp15_value;
  76     asm volatile (
  77         "mrc p15, 0, %0, c1, c0, 0   @ read control reg\n" : "=r"(cp15_value));
  78     return (cp15_value);
  79 }
  80
  81 static int calc_freq(int clk)
  82 {
  83     unsigned int prediv = ((unsigned int)CGU_PROC>>2) & 0x3;
  84     unsigned int postdiv = ((unsigned int)CGU_PROC>>4) & 0xf;
  85 #if CONFIG_CPU == AS3525
  86     int out_div;
  87
  88     switch(clk) {
  89         /* clk_main = clk_int = 24MHz oscillator */
  90         case CLK_PLLA:
  91             if(CGU_PLLASUP & (1<<3))
  92                 return 0;
  93
  94                  /*assume 24MHz oscillator only input available */
  95             out_div = ((CGU_PLLA>>13) & 0x3);         /* bits 13:14 */
  96             if (out_div == 3)                         /* for 11 NO=4  */
  97                 out_div=4;
  98             if(out_div)                               /*  NO = 0 not allowed */
  99                 return ((2 * (CGU_PLLA & 0xff))*CLK_MAIN)/
 100                                                (((CGU_PLLA>>8) & 0x1f)*out_div);
 101             return 0;
 102        case CLK_PLLB:
 103             if(CGU_PLLBSUP & (1<<3))
 104                 return 0;
 105
 106                  /*assume 24MHz oscillator only input available */
 107             out_div = ((CGU_PLLB>>13) & 0x3);         /* bits 13:14 */
 108             if (out_div == 3)                         /* for 11 NO=4  */
 109                 out_div=4;
 110             if(out_div)                               /*  NO = 0 not allowed */
 111                 return ((2 * (CGU_PLLB & 0xff))*CLK_MAIN)/
 112                                                (((CGU_PLLB>>8) & 0x1f)*out_div);
 113             return 0;
 114 #else
 115     /* AS3525v2  */
 116     switch(clk) {
 117         /*  we're using a known setting for PLLA = 240 MHz and PLLB inop  */
 118         case CLK_PLLA:
 119             return 240000000;
 120
 121         case CLK_PLLB:
 122             return 0;
 123 #endif
 124         case CLK_PROC:
 125 #if CONFIG_CPU == AS3525 /* not in arm926-ejs */
 126             if (!(read_cp15()>>30))                 /* fastbus */
 127                 return calc_freq(CLK_PCLK);
 128             else                                    /* Synch or Asynch bus*/
 129 #endif /* CONFIG_CPU == AS3525 */
 130                 return calc_freq(CLK_FCLK);
 131         case CLK_FCLK:
 132             switch(CGU_PROC & 3) {
 133                 case 0:
 134                     return (CLK_MAIN * (8 - prediv)) / (8 * (postdiv + 1));
 135                 case 1:
 136                     return (calc_freq(CLK_PLLA) * (8 - prediv)) /
 137                                                             (8 * (postdiv + 1));
 138                 case 2:
 139                     return (calc_freq(CLK_PLLB) * (8 - prediv)) /
 140                                                             (8 * (postdiv + 1));
 141                 default:
 142                     return 0;
 143             }
 144         case CLK_EXTMEM:
 145 #if CONFIG_CPU == AS3525
 146             switch(CGU_PERI & 3) {
 147 #else
 148             /* bits 1:0 of CGU_PERI always read as 0 and source = FCLK */
 149             switch(3) {
 150 #endif
 151                 case 0:
 152                     return CLK_MAIN/(((CGU_PERI>>2)& 0xf)+1);
 153                 case 1:
 154                     return calc_freq(CLK_PLLA)/(((CGU_PERI>>2)& 0xf)+1);
 155                 case 2:
 156                     return calc_freq(CLK_PLLB)/(((CGU_PERI>>2)& 0xf)+1);
 157                 case 3:
 158                 default:
 159                     return calc_freq(CLK_FCLK)/(((CGU_PERI>>2)& 0xf)+1);
 160             }
 161         case CLK_PCLK:
 162             return calc_freq(CLK_EXTMEM)/(((CGU_PERI>>6)& 0x1)+1);
 163         case CLK_IDE:
 164             switch(CGU_IDE & 3) {
 165                 case 0:
 166                     return CLK_MAIN/(((CGU_IDE>>2)& 0xf)+1);
 167                 case 1:
 168                     return calc_freq(CLK_PLLA)/(((CGU_IDE>>2)& 0xf)+1);
 169                 case 2:
 170                     return calc_freq(CLK_PLLB)/(((CGU_IDE>>2)& 0xf)+1);
 171                 default:
 172                     return 0;
 173             }
 174         case CLK_I2C:
 175             return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER;
 176         case CLK_I2SI:
 177             switch((CGU_AUDIO>>12) & 3) {
 178                 case 0:
 179                     return CLK_MAIN/(((CGU_AUDIO>>14) & 0x1ff)+1);
 180                 case 1:
 181                     return calc_freq(CLK_PLLA)/(((CGU_AUDIO>>14) & 0x1ff)+1);
 182                 case 2:
 183                     return calc_freq(CLK_PLLB)/(((CGU_AUDIO>>14) & 0x1ff)+1);
 184                 default:
 185                     return 0;
 186             }
 187         case CLK_I2SO:
 188             switch(CGU_AUDIO & 3) {
 189                 case 0:
 190                     return CLK_MAIN/(((CGU_AUDIO>>2) & 0x1ff)+1);
 191                 case 1:
 192                     return calc_freq(CLK_PLLA)/(((CGU_AUDIO>>2) & 0x1ff)+1);
 193                 case 2:
 194                     return calc_freq(CLK_PLLB)/(((CGU_AUDIO>>2) & 0x1ff)+1);
 195                 default:
 196                     return 0;
 197             }
 198         case CLK_DBOP:
 199             return calc_freq(CLK_PCLK)/((CGU_DBOP & 7)+1);
 200 #if CONFIG_CPU == AS3525
 201         case CLK_SD_MCLK_NAND:
 202             if(!(MCI_NAND & (1<<8)))
 203                 return 0;
 204             else if(MCI_NAND & (1<<10))
 205                 return calc_freq(CLK_IDE);
 206             else
 207                 return calc_freq(CLK_IDE)/(((MCI_NAND & 0xff)+1)*2);
 208         case CLK_SD_MCLK_MSD:
 209             if(!(MCI_SD & (1<<8)))
 210                 return 0;
 211             else if(MCI_SD & (1<<10))
 212                 return calc_freq(CLK_PCLK);
 213             else
 214             return calc_freq(CLK_PCLK)/(((MCI_SD & 0xff)+1)*2);
 215 #endif
 216         case CLK_USB:
 217             switch(CGU_USB & 3) {     /* 0-> div=1  other->div=1/(2*n)  */
 218                 case 0:
 219                     if (!((CGU_USB>>2) & 0x7))
 220                         return CLK_MAIN;
 221                     else
 222                         return CLK_MAIN/(2*((CGU_USB>>2) & 0x7));
 223                 case 1:
 224                     if (!((CGU_USB>>2) & 0x7))
 225                         return calc_freq(CLK_PLLA);
 226                     else
 227                         return calc_freq(CLK_PLLA)/(2*((CGU_USB>>2) & 0x7));
 228                 case 2:
 229                     if (!((CGU_USB>>2) & 0x7))
 230                         return calc_freq(CLK_PLLB);
 231                     else
 232                         return calc_freq(CLK_PLLB)/(2*((CGU_USB>>2) & 0x7));
 233                 default:
 234                     return 0;
 235             }
 236         default:
 237             return 0;
 238         }
 239 }
 240
 241 bool __dbg_hw_info(void)
 242 {
 243     int line;
 244 #if CONFIG_CPU == AS3525
 245     int last_nand = 0;
 246 #ifdef HAVE_MULTIDRIVE
 247     int last_sd = 0;
 248 #endif
 249 #endif /* CONFIG_CPU == AS3525 */
 250
 251     lcd_clear_display();
 252     lcd_setfont(FONT_SYSFIXED);
 253
 254     while(1)
 255     {
 256         while(1)
 257         {
 258 #ifdef SANSA_C200V2
 259         extern int dbop_denoise_accept;
 260         extern int dbop_denoise_reject;
 261
 262         lcd_clear_display();
 263         line = 0;
 264         lcd_puts(0, line++, "[Submodel:]");
 265         lcd_putsf(0, line++, "C200v2 variant %d", c200v2_variant);
 266         if (dbop_denoise_accept) {
 267             lcd_putsf(0, line++, "DBOP noise: %d%%",
 268                       (100*dbop_denoise_reject)/dbop_denoise_accept);
 269         } else {
 270             lcd_puts(0, line++, "DBOP noise: oo");
 271         }
 272         lcd_putsf(0, line++, "reject: %d", dbop_denoise_reject);
 273         lcd_putsf(0, line++, "accept: %d", dbop_denoise_accept);
 274         lcd_update();
 275         int btn = button_get_w_tmo(HZ/10);
 276         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 277             goto end;
 278         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 279             break;
 280         }
 281         while(1)
 282         {
 283 #endif
 284         lcd_clear_display();
 285         line = 0;
 286         lcd_puts(0, line++, "[Clock Frequencies:]");
 287         lcd_puts(0, line++, "     SET       ACTUAL");
 288 #if CONFIG_CPU == AS3525
 289         lcd_putsf(0, line++, "922T:%s     %3dMHz",
 290                                         (!(read_cp15()>>30)) ? "FAST " :
 291                                         (read_cp15()>>31) ? "ASYNC" : "SYNC ",
 292 #else
 293         lcd_putsf(0, line++, "926ejs:        %3dMHz",
 294 #endif
 295                                          calc_freq(CLK_PROC)/1000000);
 296         lcd_putsf(0, line++, "PLLA:%3dMHz    %3dMHz", AS3525_PLLA_FREQ/1000000,
 297                                                    calc_freq(CLK_PLLA)/1000000);
 298         lcd_putsf(0, line++, "PLLB:          %3dMHz", calc_freq(CLK_PLLB)/1000000);
 299         lcd_putsf(0, line++, "FCLK:          %3dMHz", calc_freq(CLK_FCLK)/1000000);
 300         lcd_putsf(0, line++, "DRAM:%3dMHz    %3dMHz", AS3525_PCLK_FREQ/1000000,
 301                                                  calc_freq(CLK_EXTMEM)/1000000);
 302         lcd_putsf(0, line++, "PCLK:%3dMHz    %3dMHz", AS3525_PCLK_FREQ/1000000,
 303                                                    calc_freq(CLK_PCLK)/1000000);
 304
 305 #if LCD_HEIGHT < 176  /* clip  */
 306         lcd_update();
 307         int btn = button_get_w_tmo(HZ/10);
 308         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 309             goto end;
 310         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 311             break;
 312         }
 313         while(1)
 314         {
 315         lcd_clear_display();
 316         line = 0;
 317 #endif  /*  LCD_HEIGHT < 176 */
 318
 319         lcd_putsf(0, line++, "IDE :%3dMHz    %3dMHz", AS3525_IDE_FREQ/1000000,
 320                                                     calc_freq(CLK_IDE)/1000000);
 321         lcd_putsf(0, line++, "DBOP:%3dMHz    %3dMHz", AS3525_DBOP_FREQ/1000000,
 322                                                    calc_freq(CLK_DBOP)/1000000);
 323         lcd_putsf(0, line++, "I2C :%3dkHz    %3dkHz", AS3525_I2C_FREQ/1000,
 324                                                        calc_freq(CLK_I2C)/1000);
 325         lcd_putsf(0, line++, "I2SI: %s      %3dMHz", (CGU_AUDIO & (1<<23)) ?
 326                                    "on " : "off" , calc_freq(CLK_I2SI)/1000000);
 327         lcd_putsf(0, line++, "I2SO: %s      %3dMHz", (CGU_AUDIO & (1<<11)) ?
 328                                     "on " : "off", calc_freq(CLK_I2SO)/1000000);
 329 #if CONFIG_CPU == AS3525
 330         /* If disabled, enable SD cards so we can read the registers */
 331         if(sd_enabled == false)
 332         {
 333             sd_enable(true);
 334             last_nand = MCI_NAND;
 335 #ifdef HAVE_MULTIDRIVE
 336             last_sd = MCI_SD;
 337 #endif
 338             sd_enable(false);
 339         }
 340
 341         lcd_putsf(0, line++, "SD  :%3dMHz    %3dMHz",
 342             ((AS3525_IDE_FREQ/ 1000000) /
 343             ((last_nand & MCI_CLOCK_BYPASS)? 1:(((last_nand & 0xff)+1) * 2))),
 344             calc_freq(CLK_SD_MCLK_NAND)/1000000);
 345 #ifdef HAVE_MULTIDRIVE
 346         lcd_putsf(0, line++, "uSD :%3dMHz    %3dMHz",
 347             ((AS3525_PCLK_FREQ/ 1000000) /
 348             ((last_sd & MCI_CLOCK_BYPASS) ? 1: (((last_sd & 0xff) + 1) * 2))),
 349             calc_freq(CLK_SD_MCLK_MSD)/1000000);
 350 #endif
 351 #endif  /* CONFIG_CPU == AS3525 */
 352         lcd_putsf(0, line++, "USB :          %3dMHz", calc_freq(CLK_USB)/1000000);
 353
 354 #if LCD_HEIGHT < 176  /* clip  */
 355         lcd_update();
 356         int btn = button_get_w_tmo(HZ/10);
 357         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 358             goto end;
 359         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 360             break;
 361         }
 362         while(1)
 363         {
 364         lcd_clear_display();
 365         line = 0;
 366 #endif  /*  LCD_HEIGHT < 176 */
 367
 368         lcd_putsf(0, line++, "MMU :  %s CVDDP:%4d", (read_cp15() & CP15_MMU) ?
 369                                         " on" : "off", adc_read(ADC_CVDD) * 25);
 370         lcd_putsf(0, line++, "Icache:%s Dcache:%s",
 371                                       (read_cp15() & CP15_IC)  ? " on" : "off",
 372                                       (read_cp15() & CP15_DC)  ? " on" : "off");
 373
 374         lcd_update();
 375         int btn = button_get_w_tmo(HZ/10);
 376         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 377             goto end;
 378         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 379             break;
 380         }
 381         while(1)
 382         {
 383         lcd_clear_display();
 384         line = 0;
 385
 386         lcd_putsf(0, line++, "CGU_PLLA  :%8x", (unsigned int)(CGU_PLLA));
 387         lcd_putsf(0, line++, "CGU_PLLB  :%8x", (unsigned int)(CGU_PLLB));
 388         lcd_putsf(0, line++, "CGU_PROC  :%8x", (unsigned int)(CGU_PROC));
 389         lcd_putsf(0, line++, "CGU_PERI  :%8x", (unsigned int)(CGU_PERI));
 390         lcd_putsf(0, line++, "CGU_IDE   :%8x", (unsigned int)(CGU_IDE));
 391         lcd_putsf(0, line++, "CGU_DBOP  :%8x", (unsigned int)(CGU_DBOP));
 392         lcd_putsf(0, line++, "CGU_AUDIO :%8x", (unsigned int)(CGU_AUDIO));
 393         lcd_putsf(0, line++, "CGU_USB   :%8x", (unsigned int)(CGU_USB));
 394
 395 #if LCD_HEIGHT < 176  /* clip  */
 396         lcd_update();
 397         int btn = button_get_w_tmo(HZ/10);
 398         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 399             goto end;
 400         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 401             break;
 402         }
 403         while(1)
 404         {
 405         lcd_clear_display();
 406         line = 0;
 407 #endif  /*  LCD_HEIGHT < 176 */
 408
 409         lcd_putsf(0, line++, "I2C2_CPSR :%8x", (unsigned int)(I2C2_CPSR1<<8 |
 410                                                        I2C2_CPSR0));
 411 #if CONFIG_CPU == AS3525
 412         lcd_putsf(0, line++, "MCI_NAND  :%8x", (unsigned int)(MCI_NAND));
 413         lcd_putsf(0, line++, "MCI_SD    :%8x", (unsigned int)(MCI_SD));
 414 #else
 415         lcd_putsf(0, line++, "CGU_MEMSTK:%8x", (unsigned int)(CGU_MEMSTICK));
 416         lcd_putsf(0, line++, "CGU_SDSLOT:%8x", (unsigned int)(CGU_SDSLOT));
 417 #endif
 418
 419         lcd_update();
 420         int btn = button_get_w_tmo(HZ/10);
 421         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 422             goto end;
 423         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 424             break;
 425         }
 426     }
 427
 428 end:
 429     lcd_setfont(FONT_UI);
 430     return false;
 431 }
 432
 433 bool __dbg_ports(void)
 434 {
 435     int line;
 436
 437     lcd_clear_display();
 438     lcd_setfont(FONT_SYSFIXED);
 439
 440     while(1)
 441     {
 442         line = 0;
 443         lcd_puts(0, line++, "[GPIO Values and Directions]");
 444         lcd_putsf(0, line++, "GPIOA: %2x DIR: %2x", GPIOA_DATA, GPIOA_DIR);
 445         lcd_putsf(0, line++, "GPIOB: %2x DIR: %2x", GPIOB_DATA, GPIOB_DIR);
 446         lcd_putsf(0, line++, "GPIOC: %2x DIR: %2x", GPIOC_DATA, GPIOC_DIR);
 447         lcd_putsf(0, line++, "GPIOD: %2x DIR: %2x", GPIOD_DATA, GPIOD_DIR);
 448 #ifdef DEBUG_DBOP
 449         line++;
 450         lcd_puts(0, line++, "[DBOP_DIN]");
 451         lcd_putsf(0, line++, "DBOP_DIN: %4x", dbop_debug());
 452 #endif
 453         line++;
 454         lcd_puts(0, line++, "[CP15]");
 455         lcd_putsf(0, line++, "CP15: 0x%8x", read_cp15());
 456         lcd_update();
 457         if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL))
 458             break;
 459     }
 460     lcd_setfont(FONT_UI);
 461     return false;
 462 }