1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2002 by Linus Nielsen Feltzing
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
24 .section .init.text,"ax",@progbits
43 clr.l (0x180,%a1) /* PLLCR = 0 */
45 /* 64K DMA-capable SRAM at 0x10000000
46 DMA is enabled and has priority in both banks
47 All types of accesses are allowed
48 (We might want to restrict that to save power) */
49 move.l #0x10000e01,%d0
52 /* 32K Non-DMA SRAM at 0x10010000
53 All types of accesses are allowed
54 (We might want to restrict that to save power) */
55 move.l #0x10010001,%d0
58 /* Chip select 0 - Flash ROM */
59 moveq.l #0x00,%d0 /* CSAR0 - Base = 0x00000000 */
60 move.l %d0,(0x080,%a0)
61 move.l #FLASH_SIZE-0x10000+1,%d0 /* CSMR0 - All access */
62 move.l %d0,(0x084,%a0)
63 move.l #0x00000180,%d0 /* CSCR0 - no wait states, 16 bits, no bursts */
64 move.l %d0,(0x088,%a0)
67 /* Chip select 3 - LCD controller */
68 /* values taken from original firmware except base address*/
69 move.l #0xf0000000,%d0 /* CSAR3 - Base = 0xf0000000 */
70 move.l %d0,(0x0a4,%a0)
71 moveq.l #0x1,%d0 /* CSMR3 - 64K */
72 move.l %d0,(0x0a8,%a0)
73 move.l #0x00000980,%d0 /* CSCR3 - 1 wait state, 16 bits no bursts */
74 move.l %d0,(0x0ac,%a0)
75 #elif !(defined IAUDIO_M3)
76 /* Chip select 1 - LCD controller */
77 move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */
78 move.l %d0,(0x08c,%a0)
79 moveq.l #0x1,%d0 /* CSMR1 - 64K */
80 move.l %d0,(0x090,%a0)
81 move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */
82 move.l %d0,(0x094,%a0)
85 /* Chip select 2 - ATA controller */
86 move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */
87 move.l %d0,(0x098,%a0)
88 moveq.l #0x1,%d0 /* CSMR2 - 64K */
89 move.l %d0,(0x09c,%a0)
90 move.l #0x00000080,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */
91 move.l %d0,(0x0a0,%a0) /* wait states are handled by the coldfire
92 * IDE interface logic. */
94 #if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
95 /* Chip select 3 - USBOTG controller */
96 move.l #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */
97 move.l %d0,(0x0a4,%a0)
98 moveq.l #0x1,%d0 /* CSMR3 - 64K */
99 move.l %d0,(0x0a8,%a0)
100 move.l #0x00000180,%d0 /* CSCR3 - no wait states, 16 bits, no bursts */
101 move.l %d0,(0x0ac,%a0)
105 /* Check if we have a Rockbox ROM image */
108 move.l #FLASH_MAGIC,%d1
112 /* Check for RAM image */
115 move.l #FLASH_MAGIC,%d1
119 /* Not either ROM or RAM image was found, so original firmware
120 should be still present. */
122 /* Check if the cookie is present. */
125 move.l #0xc0015a17,%d1
129 /* The cookie is not reset. This must mean that the boot loader
130 has crashed. Let's start the original firmware immediately. */
140 /* Set up the DRAM controller. The refresh is based on the 11.2896MHz
141 clock (5.6448MHz bus frequency). We haven't yet started the PLL */
143 move.w #0x8004,%d0 /* DCR - Synchronous, 80 cycle refresh */
145 move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */
147 move.w %d0,(0x100,%a0)
149 /* Note on 32Mbyte models:
150 We place the SDRAM on an 0x1000000 (16M) offset because
151 the 5249 BGA chip has a fault which disables the use of A24. The
152 suggested workaround by FreeScale is to offset the base address by
153 half the DRAM size and increase the mask to the double.
154 In our case this means that we set the base address 16M ahead and
158 move.l #0x31002324,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up,
159 CAS latency 2, Page mode, No refresh yet */
160 move.l %d0,(0x108,%a0)
161 move.l #0x00fc0001,%d0 /* Size: 16M */
162 move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */
164 move.l #0x31002524,%d0 /* DACR0 - Base 0x31000000, Banks on 23 and up,
165 CAS latency 2, Page mode, No refresh yet */
166 move.l %d0,(0x108,%a0)
167 move.l #0x03fc0001,%d0 /* Size: 64M because of workaround above */
168 move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */
173 or.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a
175 move.l #0xabcd1234,%d0
176 move.l %d0,0x31000000 /* Issue precharge command */
179 or.l %d0,(0x108,%a0) /* Enable refresh */
187 /* Mode Register init */
188 moveq.l #0x40,%d0 /* DACR0[IMRS] = 1, next access will set the
192 move.l #0xabcd1234,%d0
193 move.l %d0,0x31000800 /* A11=1 means CASL=2 (connected to SDRAM A5). */
195 /* DACR0[IMRS] gets deactivated by the SDRAM controller */
197 /* Check if we have a Rockbox ROM image. For RAM image only cookie is
198 not set at all. But we could support also RAM images loading. */
201 move.l #FLASH_MAGIC,%d1
205 /* Check again if the cookie is present. */
208 move.l #0xc0015a17,%d1
212 /* We have found Rockbox in ROM!
213 Clear the cookie and load the ROM image */
228 #endif /* BOOTLOADER */
230 /* Invalicate cache */
231 move.l #0x01000000,%d0
234 /* Enable cache, default=non-cacheable, no buffered writes */
235 move.l #0x80000000,%d0
238 /* Cache enabled in SDRAM only, buffered writes enabled */
239 move.l #0x3103c020,%d0
241 /* Buffered writes enabled for the LCD */
242 move.l #0xf000c060,%d0
246 /* .iram copy is done first since it is reclaimed for other
247 * uninitialized sections */
249 /* copy the .iram section */
269 #endif /* !BOOTLOADER */
271 #ifdef IRIVER_H300_SERIES
272 /* Set KEEP_ACT before doing the lengthy copy and zero-fill operations */
273 move.l #0x00080000,%d0
281 * Set GPIO57 high to remove hissing nois on startup
283 move.l #0x02200000,%d0
299 /* copy the .data section */
303 beq.b .nodatacopy /* Don't copy if src and dest are equal */
313 /* Munge the main stack */
317 move.l #0xdeadbeef,%d0
327 .section .resetvectors