4 OUTPUT_FORMAT(elf32-littlearm)
6 STARTUP(target/arm/crt0-pp502x-bl-usb.o)
8 #define DRAMORIG 0x01000000 /* Load at 16 MB */
9 #define DRAMSIZE 0x00100000 /* 1MB for bootloader */
10 #define MEMEND (MEMORYSIZE*0x100000) /* From virtual mapping at 0 */
11 #define NOCACHE_BASE 0x10000000
13 #define IRAMORIG 0x40000000
15 #define IRAMSIZE 0x20000
16 #define FLASHORIG 0x001f0000
19 #define CACHEALIGN_SIZE 16
23 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
24 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
30 _loadaddress = . + NOCACHE_BASE;
43 *(.rodata) /* problems without this, dunno why */
56 /* .ncdata section is placed at uncached physical alias address and is
57 * loaded at the proper cached virtual address - no copying is
58 * performed in the init code */
59 .ncdata . + NOCACHE_BASE :
61 . = ALIGN(CACHEALIGN_SIZE);
63 . = ALIGN(CACHEALIGN_SIZE);
66 /DISCARD/ . - NOCACHE_BASE :
73 .ibss IRAMORIG (NOLOAD) :
91 _iramcopy = LOADADDR(.iram);
95 _loadaddressend = . + NOCACHE_BASE;
107 /* .bss and .ncbss are treated as a single section to use one init loop
108 * to zero them - note "_edata" and "_end" */
109 .bss _noloaddram (NOLOAD) :
116 .ncbss . + NOCACHE_BASE (NOLOAD) :
118 . = ALIGN(CACHEALIGN_SIZE);
120 . = ALIGN(CACHEALIGN_SIZE);
123 /* This will be aligned by preceding alignments */
124 .endaddr . - NOCACHE_BASE (NOLOAD) :
129 /* Reference to all DRAM after loaded bootloader image */
130 .freebuffer _end (NOLOAD) :