firmware/target/arm/imx31/dvfs_dptc-imx31.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2010 by Michael Sevakis
  11  *
  12  * i.MX31 DVFS and DPTC drivers
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23 #include "config.h"
  24 #include "system.h"
  25 #include "logf.h"
  26 #include "mc13783.h"
  27 #include "iomuxc-imx31.h"
  28 #include "ccm-imx31.h"
  29 #include "avic-imx31.h"
  30 #include "dvfs_dptc-imx31.h"
  31 #include "dvfs_dptc_tables-target.h"
  32
  33 /* Most of the code in here is based upon the Linux BSP provided by Freescale
  34  * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. */
  35
  36 /* The current DVFS index level */
  37 static volatile unsigned int dvfs_level = DVFS_LEVEL_DEFAULT;
  38 /* The current DPTC working point */
  39 static volatile unsigned int dptc_wp = DPTC_WP_DEFAULT;
  40
  41
  42 static void update_dptc_counts(unsigned int level, unsigned int wp)
  43 {
  44     int oldlevel = disable_irq_save();
  45     const struct dptc_dcvr_table_entry *entry = &dptc_dcvr_table[level][wp];
  46
  47     CCM_DCVR0 = entry->dcvr0;
  48     CCM_DCVR1 = entry->dcvr1;
  49     CCM_DCVR2 = entry->dcvr2;
  50     CCM_DCVR3 = entry->dcvr3;
  51
  52     restore_irq(oldlevel);
  53 }
  54
  55
  56 static uint32_t check_regulator_setting(uint32_t setting)
  57 {
  58     /* Simply a safety check *in case* table gets scrambled */
  59     if (setting < VOLTAGE_SETTING_MIN)
  60         setting = VOLTAGE_SETTING_MIN;
  61     else if (setting > VOLTAGE_SETTING_MAX)
  62         setting = VOLTAGE_SETTING_MAX;
  63
  64     return setting;
  65 }
  66
  67
  68 /** DVFS **/
  69 static bool dvfs_running = false; /* Has driver enabled DVFS? */
  70
  71 /* Request tracking since boot */
  72 unsigned int dvfs_nr_dn = 0;
  73 unsigned int dvfs_nr_up = 0;
  74 unsigned int dvfs_nr_pnc = 0;
  75
  76 static void dvfs_stop(void);
  77
  78
  79 /* Wait for the UPDTEN flag to be set so that all bits may be written */
  80 static inline void wait_for_dvfs_update_en(void)
  81 {
  82     while (!(CCM_PMCR0 & CCM_PMCR0_UPDTEN));
  83 }
  84
  85
  86 static void do_dvfs_update(unsigned int level)
  87 {
  88     const struct dvfs_clock_table_entry *setting = &dvfs_clock_table[level];
  89     unsigned long pmcr0 = CCM_PMCR0;
  90
  91     if (pmcr0 & CCM_PMCR0_DPTEN)
  92     {
  93         /* Ignore voltage change request from DPTC. Voltage is *not* valid. */
  94         pmcr0 &= ~CCM_PMCR0_DPVCR;
  95     }
  96
  97     pmcr0 &= ~CCM_PMCR0_VSCNT;
  98
  99     if (level > ((pmcr0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS))
 100     {
 101         pmcr0 |= CCM_PMCR0_UDSC; /* Up scaling, increase */
 102         pmcr0 |= setting->vscnt << CCM_PMCR0_VSCNT_POS;
 103     }
 104     else
 105     {
 106         pmcr0 &= ~CCM_PMCR0_UDSC; /* Down scaling, decrease */
 107         pmcr0 |= 0x1 << CCM_PMCR0_VSCNT_POS;
 108     }
 109
 110     /* DVSUP (new frequency index) setup */
 111     pmcr0 = (pmcr0 & ~CCM_PMCR0_DVSUP) | (level << CCM_PMCR0_DVSUP_POS);
 112
 113     dvfs_level = level;
 114
 115     if ((setting->pll_num << CCM_PMCR0_DFSUP_MCUPLL_POS) ^
 116         (pmcr0 & CCM_PMCR0_DFSUP_MCUPLL))
 117     {
 118         /* Update pll and post-dividers. */
 119         pmcr0 ^= CCM_PMCR0_DFSUP_MCUPLL;
 120         pmcr0 &= ~CCM_PMCR0_DFSUP_POST_DIVIDERS;
 121     }
 122     else
 123     {
 124         /* Post-dividers update only */
 125         pmcr0 |= CCM_PMCR0_DFSUP_POST_DIVIDERS;
 126     }
 127
 128     CCM_PMCR0 = pmcr0;
 129     udelay(100); /* Software wait for voltage ramp-up */
 130     CCM_PDR0 = setting->pdr_val;
 131
 132     if (!(pmcr0 & CCM_PMCR0_DFSUP_POST_DIVIDERS))
 133     {
 134         /* Update the PLL settings */
 135         if (pmcr0 & CCM_PMCR0_DFSUP_MCUPLL)
 136             CCM_MPCTL = setting->pll_val;
 137         else
 138             CCM_SPCTL = setting->pll_val;
 139     }
 140
 141     cpu_frequency = ccm_get_mcu_clk();
 142
 143     if (pmcr0 & CCM_PMCR0_DPTEN)
 144     {
 145         update_dptc_counts(level, dptc_wp);
 146         /* Enable DPTC to request voltage changes. Voltage is valid. */
 147         CCM_PMCR0 |= CCM_PMCR0_DPVCR;
 148         udelay(2);
 149         CCM_PMCR0 |= CCM_PMCR0_DPVV;
 150     }
 151 }
 152
 153
 154 /* Start DVFS, change the set point and stop it */
 155 static void set_current_dvfs_level(unsigned int level)
 156 {
 157     int oldlevel = disable_irq_save();
 158
 159     CCM_PMCR0 |= CCM_PMCR0_DVFEN;
 160
 161     wait_for_dvfs_update_en();
 162
 163     do_dvfs_update(level);
 164
 165     wait_for_dvfs_update_en();
 166
 167     CCM_PMCR0 &= ~CCM_PMCR0_DVFEN;
 168
 169     restore_irq(oldlevel);
 170 }
 171
 172
 173 /* DVFS Interrupt handler */
 174 static void __attribute__((used)) dvfs_int(void)
 175 {
 176     unsigned long pmcr0 = CCM_PMCR0;
 177     unsigned long fsvai = pmcr0 & CCM_PMCR0_FSVAI;
 178     unsigned int level = (pmcr0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS;
 179
 180     if (pmcr0 & CCM_PMCR0_FSVAIM)
 181         return; /* Do nothing. DVFS interrupt is masked. */
 182
 183     if (!(pmcr0 & CCM_PMCR0_UPDTEN))
 184         return; /* Do nothing. DVFS didn't finish previous flow update. */
 185
 186     switch (fsvai)
 187     {
 188     case CCM_PMCR0_FSVAI_DECREASE:
 189         if (level >= DVFS_NUM_LEVELS - 1)
 190             return; /* DVFS already at lowest level */
 191
 192         /* Upon the DECREASE event, the frequency will be changed to the next
 193          * higher state index. */
 194         level++;
 195         dvfs_nr_dn++;
 196         break;
 197
 198     /* Single-step frequency increase */
 199     case CCM_PMCR0_FSVAI_INCREASE:
 200         if (level == 0)
 201             return; /* DVFS already at highest level */
 202
 203         /* Upon the INCREASE event, the frequency will be changed to the next
 204          * lower state index. */
 205         level--;
 206         dvfs_nr_up++;
 207         break;
 208
 209     /* Right to highest if panic */
 210     case CCM_PMCR0_FSVAI_INCREASE_NOW:
 211         if (level == 0)
 212             return; /* DVFS already at highest level */
 213
 214         /* Upon the INCREASE_NOW event, the frequency will be increased to
 215          * the maximum (index 0). */
 216         level = 0;
 217         dvfs_nr_pnc++;
 218         break;
 219
 220     case CCM_PMCR0_FSVAI_NO_INT:
 221     default:
 222         return;     /* Do nothing. Freq change is not required */
 223     } /* end switch */
 224
 225     do_dvfs_update(level);
 226 }
 227
 228
 229 /* Interrupt vector for DVFS */
 230 static __attribute__((naked, interrupt("IRQ"))) void CCM_DVFS_HANDLER(void)
 231 {
 232     /* Audio can glitch with the long udelay if nested IRQ isn't allowed. */
 233     AVIC_NESTED_NI_CALL_PROLOGUE();
 234     asm volatile ("bl dvfs_int");
 235     AVIC_NESTED_NI_CALL_EPILOGUE();
 236 }
 237
 238
 239 /* Initialize the DVFS hardware */
 240 static void dvfs_init(void)
 241 {
 242     if (CCM_PMCR0 & CCM_PMCR0_DVFEN)
 243     {
 244         /* Turn it off first. Really, shouldn't happen though. */
 245         dvfs_running = true;
 246         dvfs_stop();
 247     }
 248
 249     /* Combine SW1A and SW1B DVS pins for a possible five DVS levels
 250      * per working point. Four, MAXIMUM, are actually used, one for each
 251      * frequency. */
 252     mc13783_set(MC13783_ARBITRATION_SWITCHERS, MC13783_SW1ABDVS);
 253
 254     /* Set DVS speed to 25mV every 4us. */
 255     mc13783_write_masked(MC13783_SWITCHERS4, MC13783_SW1ADVSSPEED_4US,
 256                          MC13783_SW1ADVSSPEED);
 257
 258     /* Set DVFS pins to functional outputs. Input mode and pad setting is
 259      * fixed in hardware. */
 260     iomuxc_set_pin_mux(IOMUXC_DVFS0,
 261                        IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_NONE);
 262     iomuxc_set_pin_mux(IOMUXC_DVFS1,
 263                        IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_NONE);
 264
 265 #ifndef DVFS_NO_PWRRDY
 266     /* Configure PWRRDY signal pin. */
 267     imx31_regclr32(&GPIO1_GDIR, (1 << 5));
 268     iomuxc_set_pin_mux(IOMUXC_GPIO1_5,
 269                        IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_FUNCTIONAL);
 270 #endif
 271
 272     /* Initialize DVFS signal weights and detection modes. */
 273     int i;
 274     for (i = 0; i < 16; i++)
 275     {
 276         dvfs_set_lt_weight(i, lt_signals[i].weight);
 277         dvfs_set_lt_detect(i, lt_signals[i].detect);
 278     }
 279
 280     /* Set up LTR0. */
 281     imx31_regmod32(&CCM_LTR0,
 282                    DVFS_UPTHR << CCM_LTR0_UPTHR_POS |
 283                    DVFS_DNTHR << CCM_LTR0_DNTHR_POS |
 284                    DVFS_DIV3CK,
 285                    CCM_LTR0_UPTHR | CCM_LTR0_DNTHR | CCM_LTR0_DIV3CK);
 286
 287     /* Set up LTR1. */
 288     imx31_regmod32(&CCM_LTR1,
 289                    DVFS_DNCNT << CCM_LTR1_DNCNT_POS |
 290                    DVFS_UPCNT << CCM_LTR1_UPCNT_POS |
 291                    DVFS_PNCTHR << CCM_LTR1_PNCTHR_POS |
 292                    CCM_LTR1_LTBRSR,
 293                    CCM_LTR1_DNCNT | CCM_LTR1_UPCNT |
 294                    CCM_LTR1_PNCTHR | CCM_LTR1_LTBRSR);
 295
 296     /* Set up LTR2-- EMA configuration. */
 297     imx31_regmod32(&CCM_LTR2, DVFS_EMAC << CCM_LTR2_EMAC_POS,
 298                    CCM_LTR2_EMAC);
 299
 300     /* DVFS interrupt goes to MCU. Mask load buffer full interrupt. */
 301     imx31_regset32(&CCM_PMCR0, CCM_PMCR0_DVFIS | CCM_PMCR0_LBMI);
 302
 303     /* Initialize current core PLL and dividers for default level. Assumes
 304      * clocking scheme has been set up appropriately in other init code. */
 305     ccm_set_mcupll_and_pdr(dvfs_clock_table[DVFS_LEVEL_DEFAULT].pll_val,
 306                            dvfs_clock_table[DVFS_LEVEL_DEFAULT].pdr_val);
 307
 308     /* Set initial level and working point. */
 309     set_current_dvfs_level(DVFS_LEVEL_DEFAULT);
 310
 311     logf("DVFS: Initialized");
 312 }
 313
 314
 315 /* Start the DVFS hardware */
 316 static void dvfs_start(void)
 317 {
 318     int oldlevel;
 319
 320     /* Have to wait at least 3 div3 clocks before enabling after being
 321      * stopped. */
 322     udelay(1500);
 323
 324     oldlevel = disable_irq_save();
 325
 326     if (!dvfs_running)
 327     {
 328         dvfs_running = true;
 329
 330         /* Unmask DVFS interrupt source and enable DVFS. */
 331         avic_enable_int(INT_CCM_DVFS, INT_TYPE_IRQ, INT_PRIO_DVFS,
 332                         CCM_DVFS_HANDLER);
 333
 334         CCM_PMCR0 = (CCM_PMCR0 & ~CCM_PMCR0_FSVAIM) | CCM_PMCR0_DVFEN;
 335     }
 336
 337     restore_irq(oldlevel);
 338
 339     logf("DVFS: started");
 340 }
 341
 342
 343 /* Stop the DVFS hardware and return to default frequency */
 344 static void dvfs_stop(void)
 345 {
 346     int oldlevel = disable_irq_save();
 347
 348     if (dvfs_running)
 349     {
 350         /* Mask DVFS interrupts. */
 351         CCM_PMCR0 |= CCM_PMCR0_FSVAIM | CCM_PMCR0_LBMI;
 352         avic_disable_int(INT_CCM_DVFS);
 353
 354         if (((CCM_PMCR0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS) !=
 355                 DVFS_LEVEL_DEFAULT)
 356         {
 357             /* Set default frequency level */
 358             wait_for_dvfs_update_en();
 359             do_dvfs_update(DVFS_LEVEL_DEFAULT);
 360             wait_for_dvfs_update_en();
 361         }
 362
 363         /* Disable DVFS. */
 364         CCM_PMCR0 &= ~CCM_PMCR0_DVFEN;
 365         dvfs_running = false;
 366     }
 367
 368     restore_irq(oldlevel);
 369
 370     logf("DVFS: stopped");
 371 }
 372
 373
 374 /** DPTC **/
 375
 376 /* Request tracking since boot */
 377 static bool dptc_running = false; /* Has driver enabled DPTC? */
 378
 379 unsigned int dptc_nr_dn = 0;
 380 unsigned int dptc_nr_up = 0;
 381 unsigned int dptc_nr_pnc = 0;
 382
 383 static struct spi_transfer_desc dptc_pmic_xfer; /* Transfer descriptor */
 384 static const unsigned char dptc_pmic_regs[2] =  /* Register subaddresses */
 385 { MC13783_SWITCHERS0, MC13783_SWITCHERS1 };
 386 static uint32_t dptc_reg_shadows[2];            /* shadow regs */
 387 static uint32_t dptc_regs_buf[2];               /* buffer for async write */
 388
 389
 390 /* Enable DPTC and unmask interrupt. */
 391 static void enable_dptc(void)
 392 {
 393     int oldlevel = disable_irq_save();
 394
 395     /* Enable DPTC, assert voltage change request. */
 396     CCM_PMCR0 = (CCM_PMCR0 & ~CCM_PMCR0_PTVAIM) | CCM_PMCR0_DPTEN |
 397                     CCM_PMCR0_DPVCR;
 398
 399     udelay(2);
 400
 401     /* Set voltage valid *after* setting change request */
 402     CCM_PMCR0 |= CCM_PMCR0_DPVV;
 403
 404     restore_irq(oldlevel);
 405 }
 406
 407
 408 /* Called after asynchronous PMIC write is completed */
 409 static void dptc_transfer_done_callback(struct spi_transfer_desc *xfer)
 410 {
 411     if (xfer->count != 0)
 412         return;
 413
 414     update_dptc_counts(dvfs_level, dptc_wp);
 415
 416     if (dptc_running)
 417         enable_dptc();
 418 }
 419
 420
 421 /* Handle the DPTC interrupt and sometimes the manual setting */
 422 static void dptc_int(unsigned long pmcr0)
 423 {
 424     const union dvfs_dptc_voltage_table_entry *entry;
 425     uint32_t sw1a, sw1advs, sw1bdvs, sw1bstby;
 426     uint32_t switchers0, switchers1;
 427
 428     int wp = dptc_wp;
 429
 430     /* Mask DPTC interrupt and disable DPTC until the change request is
 431      * serviced. */
 432     CCM_PMCR0 = (pmcr0 & ~CCM_PMCR0_DPTEN) | CCM_PMCR0_PTVAIM;
 433
 434     switch (pmcr0 & CCM_PMCR0_PTVAI)
 435     {
 436     case CCM_PMCR0_PTVAI_DECREASE:
 437         wp++;
 438         dptc_nr_dn++;
 439         break;
 440
 441     case CCM_PMCR0_PTVAI_INCREASE:
 442         wp--;
 443         dptc_nr_up++;
 444         break;
 445
 446     case CCM_PMCR0_PTVAI_INCREASE_NOW:
 447         if (--wp > DPTC_WP_PANIC)
 448             wp = DPTC_WP_PANIC;
 449         dptc_nr_pnc++;
 450         break;
 451
 452     case CCM_PMCR0_PTVAI_NO_INT:
 453         break; /* Just maintain at global level */
 454     }
 455
 456     if (wp < 0)
 457         wp = 0;
 458     else if (wp >= DPTC_NUM_WP)
 459         wp = DPTC_NUM_WP - 1;
 460
 461     entry = &dvfs_dptc_voltage_table[wp];
 462
 463     sw1a = check_regulator_setting(entry->sw1a);
 464     sw1advs = check_regulator_setting(entry->sw1advs);
 465     sw1bdvs = check_regulator_setting(entry->sw1bdvs);
 466     sw1bstby = check_regulator_setting(entry->sw1bstby);
 467
 468     switchers0 = dptc_reg_shadows[0] & ~(MC13783_SW1A | MC13783_SW1ADVS);
 469     dptc_regs_buf[0] = switchers0 |
 470                        sw1a << MC13783_SW1A_POS |         /* SW1A */
 471                        sw1advs << MC13783_SW1ADVS_POS;    /* SW1ADVS */
 472     switchers1 = dptc_reg_shadows[1] & ~(MC13783_SW1BDVS | MC13783_SW1BSTBY);
 473     dptc_regs_buf[1] = switchers1 |
 474                        sw1bdvs << MC13783_SW1BDVS_POS |   /* SW1BDVS */
 475                        sw1bstby << MC13783_SW1BSTBY_POS;  /* SW1BSTBY */
 476
 477     dptc_wp = wp;
 478
 479     mc13783_write_async(&dptc_pmic_xfer, dptc_pmic_regs,
 480                         dptc_regs_buf, 2, dptc_transfer_done_callback);
 481 }
 482
 483
 484 static void dptc_new_wp(unsigned int wp)
 485 {
 486     dptc_wp = wp;
 487     /* "NO_INT" so the working point isn't incremented, just set. */
 488     dptc_int((CCM_PMCR0 & ~CCM_PMCR0_PTVAI) | CCM_PMCR0_PTVAI_NO_INT);
 489 }
 490
 491
 492 /* Interrupt vector for DPTC */
 493 static __attribute__((interrupt("IRQ"))) void CCM_CLK_HANDLER(void)
 494 {
 495     dptc_int(CCM_PMCR0);
 496 }
 497
 498
 499 /* Initialize the DPTC hardware */
 500 static void dptc_init(void)
 501 {
 502     /* Force DPTC off if running for some reason. */
 503     imx31_regmod32(&CCM_PMCR0, CCM_PMCR0_PTVAIM,
 504                    CCM_PMCR0_PTVAIM | CCM_PMCR0_DPTEN);
 505
 506      /* Shadow the regulator registers */
 507     mc13783_read_regs(dptc_pmic_regs, dptc_reg_shadows, 2);
 508
 509     /* Set default, safe working point. */
 510     dptc_new_wp(DPTC_WP_DEFAULT);
 511
 512     /* Interrupt goes to MCU, specified reference circuits enabled when
 513      * DPTC is active. */
 514     imx31_regset32(&CCM_PMCR0, CCM_PMCR0_PTVIS);
 515
 516     imx31_regmod32(&CCM_PMCR0, DPTC_DRCE_MASK,
 517                    CCM_PMCR0_DRCE0 | CCM_PMCR0_DRCE1 |
 518                    CCM_PMCR0_DRCE2 | CCM_PMCR0_DRCE3);
 519
 520     /* DPTC counting range = 256 system clocks */
 521     imx31_regclr32(&CCM_PMCR0, CCM_PMCR0_DCR);
 522
 523     logf("DPTC: Initialized");
 524 }
 525
 526
 527 /* Start DPTC module */
 528 static void dptc_start(void)
 529 {
 530     int oldlevel = disable_irq_save();
 531
 532     if (!dptc_running)
 533     {
 534         dptc_running = true;
 535
 536         /* Enable DPTC and unmask interrupt. */
 537         avic_enable_int(INT_CCM_CLK, INT_TYPE_IRQ, INT_PRIO_DPTC,
 538                         CCM_CLK_HANDLER);
 539
 540         update_dptc_counts(dvfs_level, dptc_wp);
 541         enable_dptc();
 542     }
 543
 544     restore_irq(oldlevel);
 545
 546     logf("DPTC: started");
 547 }
 548
 549
 550 /* Stop the DPTC hardware if running and go back to default working point */
 551 static void dptc_stop(void)
 552 {
 553     int oldlevel = disable_irq_save();
 554
 555     if (dptc_running)
 556     {
 557         /* Disable DPTC and mask interrupt. */
 558         CCM_PMCR0 = (CCM_PMCR0 & ~CCM_PMCR0_DPTEN) | CCM_PMCR0_PTVAIM;
 559         avic_disable_int(INT_CCM_CLK);
 560         dptc_running = false;
 561     }
 562
 563     /* Go back to default working point. */
 564     dptc_new_wp(DPTC_WP_DEFAULT);
 565
 566     restore_irq(oldlevel);
 567
 568     logf("DPTC: stopped");
 569 }
 570
 571
 572 /** Main module interface **/
 573
 574 /* Initialize DVFS and DPTC */
 575 void dvfs_dptc_init(void)
 576 {
 577     dptc_init();
 578     dvfs_init();
 579 }
 580
 581
 582 /* Start DVFS and DPTC */
 583 void dvfs_dptc_start(void)
 584 {
 585     dvfs_start();
 586     dptc_start();
 587 }
 588
 589
 590 /* Stop DVFS and DPTC */
 591 void dvfs_dptc_stop(void)
 592 {
 593     dptc_stop();
 594     dvfs_stop();
 595 }
 596
 597
 598 /* Set a signal load tracking weight */
 599 void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value)
 600 {
 601     volatile unsigned long *reg_p = &CCM_LTR2;
 602     unsigned int shift = 3 * index;
 603
 604     if (index < 9)
 605     {
 606         reg_p = &CCM_LTR3;
 607         shift += 5; /* Bits 7:5, 10:8 ... 31:29 */
 608     }
 609     else if (index < 16)
 610     {
 611         shift -= 16; /* Bits 13:11, 16:14 ... 31:29 */
 612     }
 613
 614     imx31_regmod32(reg_p, value << shift, 0x7 << shift);
 615 }
 616
 617
 618 /* Set a signal load detection mode */
 619 void dvfs_set_lt_detect(enum DVFS_LT_SIGS index, bool edge)
 620 {
 621     unsigned long bit = 0;
 622
 623     if ((unsigned)index < 13)
 624         bit = 1ul << (index + 3);
 625     else if ((unsigned)index < 16)
 626         bit = 1ul << (index + 29);
 627
 628     imx31_regmod32(&CCM_LTR0, edge ? bit : 0, bit);
 629 }
 630
 631
 632 void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert)
 633 {
 634     if ((unsigned)dvgp <= 3)
 635     {
 636         unsigned long bit = 1ul << dvgp;
 637         imx31_regmod32(&CCM_PMCR1, assert ? bit : 0, bit);
 638     }
 639 }
 640
 641
 642 /* Turn the wait-for-interrupt monitoring on or off */
 643 void dvfs_wfi_monitor(bool on)
 644 {
 645     imx31_regmod32(&CCM_PMCR0, on ? 0 : CCM_PMCR0_WFIM,
 646                    CCM_PMCR0_WFIM);
 647 }
 648
 649
 650 /* Obtain the current core voltage setting, in millivolts 8-) */
 651 unsigned int dvfs_dptc_get_voltage(void)
 652 {
 653     unsigned int v;
 654
 655     int oldlevel = disable_irq_save();
 656     v = dvfs_dptc_voltage_table[dptc_wp].sw[dvfs_level];
 657     restore_irq(oldlevel);
 658
 659     /* 25mV steps from 0.900V to 1.675V */
 660     return v * 25 + 900;
 661 }
 662
 663
 664 /* Get the current DVFS level */
 665 unsigned int dvfs_get_level(void)
 666 {
 667     return dvfs_level;
 668 }
 669
 670
 671 /* If DVFS is disabled, set the level explicitly */
 672 void dvfs_set_level(unsigned int level)
 673 {
 674     int oldlevel = disable_irq_save();
 675
 676     unsigned int currlevel =
 677         (CCM_PMCR0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS;
 678
 679     if (!dvfs_running && level < DVFS_NUM_LEVELS && level != currlevel)
 680         set_current_dvfs_level(level);
 681
 682     restore_irq(oldlevel);
 683 }
 684
 685
 686 /* Get the current DPTC working point */
 687 unsigned int dptc_get_wp(void)
 688 {
 689     return dptc_wp;
 690 }
 691
 692
 693 /* If DPTC is not running, set the working point explicitly */
 694 void dptc_set_wp(unsigned int wp)
 695 {
 696     int oldlevel = disable_irq_save();
 697
 698     if (!dptc_running && wp < DPTC_NUM_WP)
 699         dptc_new_wp(wp);
 700
 701     restore_irq(oldlevel);
 702 }