firmware/target/arm/as3525/debug-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2008 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include <stdbool.h>
  23 #include "debug-target.h"
  24 #include "button.h"
  25 #include "lcd.h"
  26 #include "font.h"
  27 #include "system.h"
  28 #include "sprintf.h"
  29 #include "cpu.h"
  30 #include "pl180.h"
  31 #include "ascodec-target.h"
  32 #include "adc.h"
  33 #include "storage.h"
  34
  35 #define ON "Enabled"
  36 #define OFF "Disabled"
  37
  38 #define CP15_MMU (1<<0)            /* mmu off/on */
  39 #define CP15_DC  (1<<2)            /* dcache off/on */
  40 #define CP15_IC  (1<<12)           /* icache off/on */
  41
  42 #define CLK_MAIN         24000000     /* 24 MHz  */
  43
  44 #define CLK_PLLA             0
  45 #define CLK_PLLB             1
  46 #define CLK_PROC             2
  47 #define CLK_FCLK             3
  48 #define CLK_EXTMEM           4
  49 #define CLK_PCLK             5
  50 #define CLK_IDE              6
  51 #define CLK_I2C              7
  52 #define CLK_I2SI             8
  53 #define CLK_I2SO             9
  54 #define CLK_DBOP             10
  55 #define CLK_SD_MCLK_NAND     11
  56 #define CLK_SD_MCLK_MSD      12
  57 #define CLK_USB              13
  58
  59 #define I2C2_CPSR0      *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x1C))
  60 #define I2C2_CPSR1      *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x20))
  61 #define MCI_NAND        *((volatile unsigned long *)(NAND_FLASH_BASE + 0x04))
  62 #define MCI_SD          *((volatile unsigned long *)(SD_MCI_BASE + 0x04))
  63
  64 extern bool sd_enabled;
  65
  66 /* FIXME: target tree is including ./debug-target.h rather than the one in
  67  * sansa-fuze/, even though deps contains the correct one
  68  * if I put the below into a sansa-fuze/debug-target.h, it doesn't work*/
  69 #if defined(SANSA_FUZE) || defined(SANSA_E200V2) || defined(SANSA_C200V2)
  70 #define DEBUG_DBOP
  71 #include "dbop-as3525.h"
  72 #endif
  73
  74 static inline unsigned read_cp15 (void)
  75 {
  76     unsigned cp15_value;
  77     asm volatile (
  78         "mrc p15, 0, %0, c1, c0, 0   @ read control reg\n" : "=r"(cp15_value));
  79     return (cp15_value);
  80 }
  81
  82 static int calc_freq(int clk)
  83 {
  84     unsigned int prediv = ((unsigned int)CGU_PROC>>2) & 0x3;
  85     unsigned int postdiv = ((unsigned int)CGU_PROC>>4) & 0xf;
  86 #if CONFIG_CPU == AS3525
  87     int out_div;
  88
  89     switch(clk) {
  90         /* clk_main = clk_int = 24MHz oscillator */
  91         case CLK_PLLA:
  92             if(CGU_PLLASUP & (1<<3))
  93                 return 0;
  94
  95                  /*assume 24MHz oscillator only input available */
  96             out_div = ((CGU_PLLA>>13) & 0x3);         /* bits 13:14 */
  97             if (out_div == 3)                         /* for 11 NO=4  */
  98                 out_div=4;
  99             if(out_div)                               /*  NO = 0 not allowed */
 100                 return ((2 * (CGU_PLLA & 0xff))*CLK_MAIN)/
 101                                                (((CGU_PLLA>>8) & 0x1f)*out_div);
 102             return 0;
 103        case CLK_PLLB:
 104             if(CGU_PLLBSUP & (1<<3))
 105                 return 0;
 106
 107                  /*assume 24MHz oscillator only input available */
 108             out_div = ((CGU_PLLB>>13) & 0x3);         /* bits 13:14 */
 109             if (out_div == 3)                         /* for 11 NO=4  */
 110                 out_div=4;
 111             if(out_div)                               /*  NO = 0 not allowed */
 112                 return ((2 * (CGU_PLLB & 0xff))*CLK_MAIN)/
 113                                                (((CGU_PLLB>>8) & 0x1f)*out_div);
 114             return 0;
 115 #else
 116     /* AS3525v2  */
 117     switch(clk) {
 118         /*  we're using a known setting for PLLA = 240 MHz and PLLB inop  */
 119         case CLK_PLLA:
 120             return 240000000;
 121
 122         case CLK_PLLB:
 123             return 0;
 124 #endif
 125         case CLK_PROC:
 126             if (!(read_cp15()>>30))                 /* fastbus */
 127                 return calc_freq(CLK_PCLK);
 128             else                                    /* Synch or Asynch bus*/
 129                 return calc_freq(CLK_FCLK);
 130         case CLK_FCLK:
 131             switch(CGU_PROC & 3) {
 132                 case 0:
 133                     return (CLK_MAIN * (8 - prediv)) / (8 * (postdiv + 1));
 134                 case 1:
 135                     return (calc_freq(CLK_PLLA) * (8 - prediv)) /
 136                                                             (8 * (postdiv + 1));
 137                 case 2:
 138                     return (calc_freq(CLK_PLLB) * (8 - prediv)) /
 139                                                             (8 * (postdiv + 1));
 140                 default:
 141                     return 0;
 142             }
 143         case CLK_EXTMEM:
 144             switch(CGU_PERI & 3) {
 145                 case 0:
 146                     return CLK_MAIN/(((CGU_PERI>>2)& 0xf)+1);
 147                 case 1:
 148                     return calc_freq(CLK_PLLA)/(((CGU_PERI>>2)& 0xf)+1);
 149                 case 2:
 150                     return calc_freq(CLK_PLLB)/(((CGU_PERI>>2)& 0xf)+1);
 151                 case 3:
 152                     return calc_freq(CLK_FCLK)/(((CGU_PERI>>2)& 0xf)+1);
 153                 default:
 154                     return 0;
 155             }
 156         case CLK_PCLK:
 157             return calc_freq(CLK_EXTMEM)/(((CGU_PERI>>6)& 0x1)+1);
 158         case CLK_IDE:
 159             switch(CGU_IDE & 3) {
 160                 case 0:
 161                     return CLK_MAIN/(((CGU_IDE>>2)& 0xf)+1);
 162                 case 1:
 163                     return calc_freq(CLK_PLLA)/(((CGU_IDE>>2)& 0xf)+1);
 164                 case 2:
 165                     return calc_freq(CLK_PLLB)/(((CGU_IDE>>2)& 0xf)+1);
 166                 default:
 167                     return 0;
 168             }
 169         case CLK_I2C:
 170             return calc_freq(CLK_PCLK)/(I2C2_CPSR1<<8 | I2C2_CPSR0);
 171         case CLK_I2SI:
 172             switch((CGU_AUDIO>>12) & 3) {
 173                 case 0:
 174                     return CLK_MAIN/(((CGU_AUDIO>>14) & 0x1ff)+1);
 175                 case 1:
 176                     return calc_freq(CLK_PLLA)/(((CGU_AUDIO>>14) & 0x1ff)+1);
 177                 case 2:
 178                     return calc_freq(CLK_PLLB)/(((CGU_AUDIO>>14) & 0x1ff)+1);
 179                 default:
 180                     return 0;
 181             }
 182         case CLK_I2SO:
 183             switch(CGU_AUDIO & 3) {
 184                 case 0:
 185                     return CLK_MAIN/(((CGU_AUDIO>>2) & 0x1ff)+1);
 186                 case 1:
 187                     return calc_freq(CLK_PLLA)/(((CGU_AUDIO>>2) & 0x1ff)+1);
 188                 case 2:
 189                     return calc_freq(CLK_PLLB)/(((CGU_AUDIO>>2) & 0x1ff)+1);
 190                 default:
 191                     return 0;
 192             }
 193         case CLK_DBOP:
 194             return calc_freq(CLK_PCLK)/((CGU_DBOP & 7)+1);
 195 #if CONFIG_CPU == AS3525
 196         case CLK_SD_MCLK_NAND:
 197             if(!(MCI_NAND & (1<<8)))
 198                 return 0;
 199             else if(MCI_NAND & (1<<10))
 200                 return calc_freq(CLK_IDE);
 201             else
 202                 return calc_freq(CLK_IDE)/(((MCI_NAND & 0xff)+1)*2);
 203         case CLK_SD_MCLK_MSD:
 204             if(!(MCI_SD & (1<<8)))
 205                 return 0;
 206             else if(MCI_SD & (1<<10))
 207                 return calc_freq(CLK_PCLK);
 208             else
 209             return calc_freq(CLK_PCLK)/(((MCI_SD & 0xff)+1)*2);
 210 #endif
 211         case CLK_USB:
 212             switch(CGU_USB & 3) {     /* 0-> div=1  other->div=1/(2*n)  */
 213                 case 0:
 214                     if (!((CGU_USB>>2) & 0xf))
 215                         return CLK_MAIN;
 216                     else
 217                         return CLK_MAIN/(2*((CGU_USB>>2) & 0xf));
 218                 case 1:
 219                     if (!((CGU_USB>>2) & 0xf))
 220                         return calc_freq(CLK_PLLA);
 221                     else
 222                         return calc_freq(CLK_PLLA)/(2*((CGU_USB>>2) & 0xf));
 223                 case 2:
 224                     if (!((CGU_USB>>2) & 0xf))
 225                         return calc_freq(CLK_PLLB);
 226                     else
 227                         return calc_freq(CLK_PLLB)/(2*((CGU_USB>>2) & 0xf));
 228                 default:
 229                     return 0;
 230             }
 231         default:
 232             return 0;
 233         }
 234 }
 235
 236 bool __dbg_hw_info(void)
 237 {
 238     int line;
 239 #if CONFIG_CPU == AS3525
 240     int last_nand = 0;
 241 #ifdef HAVE_MULTIDRIVE
 242     int last_sd = 0;
 243 #endif
 244 #endif /* CONFIG_CPU == AS3525 */
 245
 246     lcd_clear_display();
 247     lcd_setfont(FONT_SYSFIXED);
 248
 249     while(1)
 250     {
 251         while(1)
 252         {
 253         lcd_clear_display();
 254         line = 0;
 255         lcd_puts(0, line++, "[Clock Frequencies:]");
 256         lcd_puts(0, line++, "     SET       ACTUAL");
 257 #if CONFIG_CPU == AS3525
 258         lcd_putsf(0, line++, "922T:%s     %3dMHz",
 259 #else
 260         lcd_putsf(0, line++, "926ejs:%s   %3dMHz",
 261 #endif
 262                                         (!(read_cp15()>>30)) ? "FAST " :
 263                                         (read_cp15()>>31) ? "ASYNC" : "SYNC ",
 264                                          calc_freq(CLK_PROC)/1000000);
 265         lcd_putsf(0, line++, "PLLA:%3dMHz    %3dMHz", AS3525_PLLA_FREQ/1000000,
 266                                                    calc_freq(CLK_PLLA)/1000000);
 267         lcd_putsf(0, line++, "PLLB:          %3dMHz", calc_freq(CLK_PLLB)/1000000);
 268         lcd_putsf(0, line++, "FCLK:          %3dMHz", calc_freq(CLK_FCLK)/1000000);
 269         lcd_putsf(0, line++, "DRAM:%3dMHz    %3dMHz", AS3525_PCLK_FREQ/1000000,
 270                                                  calc_freq(CLK_EXTMEM)/1000000);
 271         lcd_putsf(0, line++, "PCLK:%3dMHz    %3dMHz", AS3525_PCLK_FREQ/1000000,
 272                                                    calc_freq(CLK_PCLK)/1000000);
 273
 274 #if LCD_HEIGHT < 176  /* clip  */
 275         lcd_update();
 276         int btn = button_get_w_tmo(HZ/10);
 277         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 278             goto end;
 279         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 280             break;
 281         }
 282         while(1)
 283         {
 284         lcd_clear_display();
 285         line = 0;
 286 #endif  /*  LCD_HEIGHT < 176 */
 287
 288         lcd_putsf(0, line++, "IDE :%3dMHz    %3dMHz", AS3525_IDE_FREQ/1000000,
 289                                                     calc_freq(CLK_IDE)/1000000);
 290         lcd_putsf(0, line++, "DBOP:%3dMHz    %3dMHz", AS3525_DBOP_FREQ/1000000,
 291                                                    calc_freq(CLK_DBOP)/1000000);
 292         lcd_putsf(0, line++, "I2C :%3dkHz    %3dkHz", AS3525_I2C_FREQ/1000,
 293                                                        calc_freq(CLK_I2C)/1000);
 294         lcd_putsf(0, line++, "I2SI: %s      %3dMHz", (CGU_AUDIO & (1<<23)) ?
 295                                    "on " : "off" , calc_freq(CLK_I2SI)/1000000);
 296         lcd_putsf(0, line++, "I2SO: %s      %3dMHz", (CGU_AUDIO & (1<<11)) ?
 297                                     "on " : "off", calc_freq(CLK_I2SO)/1000000);
 298 #if CONFIG_CPU == AS3525
 299         /* If disabled, enable SD cards so we can read the registers */
 300         if(sd_enabled == false)
 301         {
 302             sd_enable(true);
 303             last_nand = MCI_NAND;
 304 #ifdef HAVE_MULTIDRIVE
 305             last_sd = MCI_SD;
 306 #endif
 307             sd_enable(false);
 308         }
 309
 310         lcd_putsf(0, line++, "SD  :%3dMHz    %3dMHz",
 311             ((AS3525_IDE_FREQ/ 1000000) /
 312             ((last_nand & MCI_CLOCK_BYPASS)? 1:(((last_nand & 0xff)+1) * 2))),
 313             calc_freq(CLK_SD_MCLK_NAND)/1000000);
 314 #ifdef HAVE_MULTIDRIVE
 315         lcd_putsf(0, line++, "uSD :%3dMHz    %3dMHz",
 316             ((AS3525_PCLK_FREQ/ 1000000) /
 317             ((last_sd & MCI_CLOCK_BYPASS) ? 1: (((last_sd & 0xff) + 1) * 2))),
 318             calc_freq(CLK_SD_MCLK_MSD)/1000000);
 319 #endif
 320 #endif  /* CONFIG_CPU == AS3525 */
 321         lcd_putsf(0, line++, "USB :          %3dMHz", calc_freq(CLK_USB)/1000000);
 322
 323 #if LCD_HEIGHT < 176  /* clip  */
 324         lcd_update();
 325         int btn = button_get_w_tmo(HZ/10);
 326         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 327             goto end;
 328         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 329             break;
 330         }
 331         while(1)
 332         {
 333         lcd_clear_display();
 334         line = 0;
 335 #endif  /*  LCD_HEIGHT < 176 */
 336
 337         lcd_putsf(0, line++, "MMU :  %s CVDDP:%4d", (read_cp15() & CP15_MMU) ?
 338                                         " on" : "off", adc_read(ADC_CVDD) * 25);
 339         lcd_putsf(0, line++, "Icache:%s Dcache:%s",
 340                                       (read_cp15() & CP15_IC)  ? " on" : "off",
 341                                       (read_cp15() & CP15_DC)  ? " on" : "off");
 342
 343         lcd_update();
 344         int btn = button_get_w_tmo(HZ/10);
 345         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 346             goto end;
 347         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 348             break;
 349         }
 350         while(1)
 351         {
 352         lcd_clear_display();
 353         line = 0;
 354
 355         lcd_putsf(0, line++, "CGU_PLLA  :%8x", (unsigned int)(CGU_PLLA));
 356         lcd_putsf(0, line++, "CGU_PLLB  :%8x", (unsigned int)(CGU_PLLB));
 357         lcd_putsf(0, line++, "CGU_PROC  :%8x", (unsigned int)(CGU_PROC));
 358         lcd_putsf(0, line++, "CGU_PERI  :%8x", (unsigned int)(CGU_PERI));
 359         lcd_putsf(0, line++, "CGU_IDE   :%8x", (unsigned int)(CGU_IDE));
 360         lcd_putsf(0, line++, "CGU_DBOP  :%8x", (unsigned int)(CGU_DBOP));
 361         lcd_putsf(0, line++, "CGU_AUDIO :%8x", (unsigned int)(CGU_AUDIO));
 362         lcd_putsf(0, line++, "CGU_USB   :%8x", (unsigned int)(CGU_USB));
 363
 364 #if LCD_HEIGHT < 176  /* clip  */
 365         lcd_update();
 366         int btn = button_get_w_tmo(HZ/10);
 367         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 368             goto end;
 369         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 370             break;
 371         }
 372         while(1)
 373         {
 374         lcd_clear_display();
 375         line = 0;
 376 #endif  /*  LCD_HEIGHT < 176 */
 377
 378         lcd_putsf(0, line++, "I2C2_CPSR :%8x", (unsigned int)(I2C2_CPSR1<<8 |
 379                                                        I2C2_CPSR0));
 380 #if CONFIG_CPU == AS3525
 381         lcd_putsf(0, line++, "MCI_NAND  :%8x", (unsigned int)(MCI_NAND));
 382         lcd_putsf(0, line++, "MCI_SD    :%8x", (unsigned int)(MCI_SD));
 383 #endif
 384
 385         lcd_update();
 386         int btn = button_get_w_tmo(HZ/10);
 387         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 388             goto end;
 389         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 390             break;
 391         }
 392     }
 393
 394 end:
 395     lcd_setfont(FONT_UI);
 396     return false;
 397 }
 398
 399 bool __dbg_ports(void)
 400 {
 401     int line;
 402
 403     lcd_clear_display();
 404     lcd_setfont(FONT_SYSFIXED);
 405
 406     while(1)
 407     {
 408         line = 0;
 409         lcd_puts(0, line++, "[GPIO Values and Directions]");
 410         lcd_putsf(0, line++, "GPIOA: %2x DIR: %2x", GPIOA_DATA, GPIOA_DIR);
 411         lcd_putsf(0, line++, "GPIOB: %2x DIR: %2x", GPIOB_DATA, GPIOB_DIR);
 412         lcd_putsf(0, line++, "GPIOC: %2x DIR: %2x", GPIOC_DATA, GPIOC_DIR);
 413         lcd_putsf(0, line++, "GPIOD: %2x DIR: %2x", GPIOD_DATA, GPIOD_DIR);
 414 #ifdef DEBUG_DBOP
 415         line++;
 416         lcd_puts(0, line++, "[DBOP_DIN]");
 417         lcd_putsf(0, line++, "DBOP_DIN: %4x", dbop_debug());
 418 #endif
 419         line++;
 420         lcd_puts(0, line++, "[CP15]");
 421         lcd_putsf(0, line++, "CP15: 0x%8x", read_cp15());
 422         lcd_update();
 423         if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL))
 424             break;
 425     }
 426     lcd_setfont(FONT_UI);
 427     return false;
 428 }