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Rockbox supports not only 1bpp BMPs
[kugel-rb.git] / firmware / drivers / audio / uda1380.c
blobefe02caca8a0bafd1e26930be957527c13ae3299
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2005 by Andy Young
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21 #include "logf.h"
22 #include "system.h"
23 #include "string.h"
24 #include "audio.h"
25 #include "debug.h"
26
27 #include "i2c-coldfire.h"
28 #include "audiohw.h"
29 #include "pcf50606.h"
30
31 const struct sound_settings_info audiohw_settings[] = {
32 [SOUND_VOLUME] = {"dB", 0, 1, -84, 0, -25},
33 [SOUND_BASS] = {"dB", 0, 2, 0, 24, 0},
34 [SOUND_TREBLE] = {"dB", 0, 2, 0, 6, 0},
35 [SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0},
36 [SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
37 [SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
38 #ifdef HAVE_RECORDING
39 [SOUND_LEFT_GAIN] = {"dB", 1, 1,-128, 96, 0},
40 [SOUND_RIGHT_GAIN] = {"dB", 1, 1,-128, 96, 0},
41 [SOUND_MIC_GAIN] = {"dB", 1, 1,-128, 108, 16},
42 #endif
43 };
44
45 /* convert tenth of dB volume (-840..0) to master volume register value */
46 int tenthdb2master(int db)
47 {
48 if (db < -720) /* 1.5 dB steps */
49 return (2940 - db) / 15;
50 else if (db < -660) /* 0.75 dB steps */
51 return (1110 - db) * 2 / 15;
52 else if (db < -520) /* 0.5 dB steps */
53 return (520 - db) / 5;
54 else /* 0.25 dB steps */
55 return -db * 2 / 5;
56 }
57
58 /* convert tenth of dB volume (-780..0) to mixer volume register value */
59 int tenthdb2mixer(int db)
60 {
61 if (db < -660) /* 1.5 dB steps */
62 return (2640 - db) / 15;
63 else if (db < -600) /* 0.75 dB steps */
64 return (990 - db) * 2 / 15;
65 else if (db < -460) /* 0.5 dB steps */
66 return (460 - db) / 5;
67 else /* 0.25 dB steps */
68 return -db * 2 / 5;
69 }
70
71 /* ------------------------------------------------- */
72 /* Local functions and variables */
73 /* ------------------------------------------------- */
74
75 static int uda1380_write_reg(unsigned char reg, unsigned short value);
76 unsigned short uda1380_regs[0x30];
77 short recgain_mic;
78 short recgain_line;
79
80 /* Definition of a playback configuration to start with */
81
82 #define NUM_DEFAULT_REGS 13
83 unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] =
84 {
85 REG_0, EN_DAC | EN_INT | EN_DEC | ADC_CLK | DAC_CLK |
86 SYSCLK_256FS | WSPLL_25_50,
87 REG_I2S, I2S_IFMT_IIS,
88 REG_PWR, PON_PLL | PON_BIAS,
89 /* PON_HP & PON_DAC is enabled later */
90 REG_AMIX, AMIX_RIGHT(0x3f) | AMIX_LEFT(0x3f),
91 /* 00=max, 3f=mute */
92 REG_MASTER_VOL, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20),
93 /* 00=max, ff=mute */
94 REG_MIX_VOL, MIX_VOL_CH_1(0) | MIX_VOL_CH_2(0xff),
95 /* 00=max, ff=mute */
96 REG_EQ, EQ_MODE_MAX,
97 /* Bass and treble = 0 dB */
98 REG_MUTE, MUTE_MASTER | MUTE_CH2,
99 /* Mute everything to start with */
100 REG_MIX_CTL, MIX_CTL_MIX,
101 /* Enable mixer */
102 REG_DEC_VOL, 0,
103 REG_PGA, MUTE_ADC,
104 REG_ADC, SKIP_DCFIL,
105 REG_AGC, 0
106 };
107
108
109 /* Returns 0 if register was written or -1 if write failed */
110 static int uda1380_write_reg(unsigned char reg, unsigned short value)
111 {
112 unsigned char data[3];
113
114 data[0] = reg;
115 data[1] = value >> 8;
116 data[2] = value & 0xff;
117
118 if (i2c_write(I2C_IFACE_0, UDA1380_ADDR, data, 3) != 3)
119 {
120 DEBUGF("uda1380 error reg=0x%x", reg);
121 return -1;
122 }
123
124 uda1380_regs[reg] = value;
125
126 return 0;
127 }
128
129 /**
130 * Sets left and right master volume (0(max) to 252(muted))
131 */
132 void audiohw_set_master_vol(int vol_l, int vol_r)
133 {
134 uda1380_write_reg(REG_MASTER_VOL,
135 MASTER_VOL_LEFT(vol_l) | MASTER_VOL_RIGHT(vol_r));
136 }
137
138 /**
139 * Sets mixer volume for both channels (0(max) to 228(muted))
140 */
141 void audiohw_set_mixer_vol(int channel1, int channel2)
142 {
143 uda1380_write_reg(REG_MIX_VOL,
144 MIX_VOL_CH_1(channel1) | MIX_VOL_CH_2(channel2));
145 }
146
147 /**
148 * Sets the bass value (0-12)
149 */
150 void audiohw_set_bass(int value)
151 {
152 uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~BASS_MASK)
153 | BASSL(value) | BASSR(value));
154 }
155
156 /**
157 * Sets the treble value (0-3)
158 */
159 void audiohw_set_treble(int value)
160 {
161 uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~TREBLE_MASK)
162 | TREBLEL(value) | TREBLER(value));
163 }
164
165 void audiohw_mute(bool mute)
166 {
167 unsigned int value = uda1380_regs[REG_MUTE];
168
169 if (mute)
170 value = value | MUTE_MASTER;
171 else
172 value = value & ~MUTE_MASTER;
173
174 uda1380_write_reg(REG_MUTE, value);
175 }
176
177 /* Returns 0 if successful or -1 if some register failed */
178 static int audiohw_set_regs(void)
179 {
180 int i;
181 memset(uda1380_regs, 0, sizeof(uda1380_regs));
182
183 /* Initialize all registers */
184 for (i=0; i<NUM_DEFAULT_REGS; i++)
185 {
186 unsigned char reg = uda1380_defaults[i*2+0];
187 unsigned short value = uda1380_defaults[i*2+1];
188
189 if (uda1380_write_reg(reg, value) == -1)
190 return -1;
191 }
192
193 return 0;
194 }
195
196 static void reset(void)
197 {
198 #ifdef IRIVER_H300_SERIES
199 int mask = disable_irq_save();
200 pcf50606_write(0x3b, 0x00); /* GPOOD2 high Z */
201 pcf50606_write(0x3b, 0x07); /* GPOOD2 low */
202 restore_irq(mask);
203 #else
204 /* RESET signal */
205 or_l(1<<29, &GPIO_OUT);
206 or_l(1<<29, &GPIO_ENABLE);
207 or_l(1<<29, &GPIO_FUNCTION);
208 sleep(HZ/100);
209 and_l(~(1<<29), &GPIO_OUT);
210 #endif
211 }
212
213 /**
214 * Sets frequency settings for DAC and ADC relative to MCLK
215 *
216 * Selection for frequency ranges:
217 * Fs: range: with:
218 * 11025: 0 = 6.25 to 12.5 MCLK/2 SCLK, LRCK: Audio Clk / 16
219 * 22050: 1 = 12.5 to 25 MCLK/2 SCLK, LRCK: Audio Clk / 8
220 * 44100: 2 = 25 to 50 MCLK SCLK, LRCK: Audio Clk / 4 (default)
221 * 88200: 3 = 50 to 100 MCLK SCLK, LRCK: Audio Clk / 2
222 */
223 void audiohw_set_frequency(int fsel)
224 {
225 static const unsigned short values_reg[HW_NUM_FREQ][2] =
226 {
227 [HW_FREQ_11] = /* Fs: */
228 {
229 0,
230 WSPLL_625_125 | SYSCLK_512FS
231 },
232 [HW_FREQ_22] =
233 {
234 0,
235 WSPLL_125_25 | SYSCLK_256FS
236 },
237 [HW_FREQ_44] =
238 {
239 MIX_CTL_SEL_NS,
240 WSPLL_25_50 | SYSCLK_256FS
241 },
242 [HW_FREQ_88] =
243 {
244 MIX_CTL_SEL_NS,
245 WSPLL_50_100 | SYSCLK_256FS
246 },
247 };
248
249 const unsigned short *ent;
250
251 if ((unsigned)fsel >= HW_NUM_FREQ)
252 fsel = HW_FREQ_DEFAULT;
253
254 ent = values_reg[fsel];
255
256 /* Set WSPLL input frequency range or SYSCLK divider */
257 uda1380_regs[REG_0] &= ~0xf;
258 uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ent[1]);
259
260 /* Choose 3rd order or 5th order noise shaper */
261 uda1380_regs[REG_MIX_CTL] &= ~MIX_CTL_SEL_NS;
262 uda1380_write_reg(REG_MIX_CTL, uda1380_regs[REG_MIX_CTL] | ent[0]);
263 }
264
265 /* Initialize UDA1380 codec with default register values (uda1380_defaults) */
266 void audiohw_init(void)
267 {
268 recgain_mic = 0;
269 recgain_line = 0;
270
271 reset();
272
273 if (audiohw_set_regs() == -1)
274 {
275 /* this shoud never (!) happen. */
276 logf("uda1380: audiohw_init failed");
277 }
278 }
279
280 void audiohw_postinit(void)
281 {
282 /* Sleep a while so the power can stabilize (especially a long
283 delay is needed for the line out connector). */
284 sleep(HZ);
285
286 /* Power on FSDAC and HP amp. */
287 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_DAC | PON_HP);
288
289 /* UDA1380: Unmute the master channel
290 (DAC should be at zero point now). */
291 audiohw_mute(false);
292 }
293
294 void audiohw_set_prescaler(int val)
295 {
296 audiohw_set_mixer_vol(tenthdb2mixer(-val), tenthdb2mixer(-val));
297 }
298
299 /* Nice shutdown of UDA1380 codec */
300 void audiohw_close(void)
301 {
302 /* First enable mute and sleep a while */
303 uda1380_write_reg(REG_MUTE, MUTE_MASTER);
304 sleep(HZ/8);
305
306 /* Then power off the rest of the chip */
307 uda1380_write_reg(REG_PWR, 0);
308 uda1380_write_reg(REG_0, 0); /* Disable codec */
309 }
310
311 /**
312 * Calling this function enables the UDA1380 to send
313 * sound samples over the I2S bus, which is connected
314 * to the processor's IIS1 interface.
315 *
316 * source_mic: true=record from microphone, false=record from line-in (or radio)
317 */
318 void audiohw_enable_recording(bool source_mic)
319 {
320 uda1380_regs[REG_0] &= ~(ADC_CLK | DAC_CLK);
321 uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC);
322
323 if (source_mic)
324 {
325 /* VGA_GAIN: 0=0 dB, F=30dB */
326 /* Output of left ADC is fed into right bitstream */
327 uda1380_regs[REG_PWR] &= ~(PON_PGAR | PON_ADCR);
328 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_LNA | PON_ADCL);
329 uda1380_regs[REG_ADC] &= ~SKIP_DCFIL;
330 uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & VGA_GAIN_MASK)
331 | SEL_LNA | SEL_MIC | EN_DCFIL);
332 uda1380_write_reg(REG_PGA, 0);
333 }
334 else
335 {
336 /* PGA_GAIN: 0=0 dB, F=24dB */
337 uda1380_regs[REG_PWR] &= ~PON_LNA;
338 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PGAL | PON_ADCL
339 | PON_PGAR | PON_ADCR);
340 uda1380_write_reg(REG_ADC, EN_DCFIL);
341 uda1380_write_reg(REG_PGA, uda1380_regs[REG_PGA] & PGA_GAIN_MASK);
342 }
343
344 sleep(HZ/8);
345
346 uda1380_write_reg(REG_I2S, uda1380_regs[REG_I2S] | I2S_MODE_MASTER);
347 uda1380_write_reg(REG_MIX_CTL, MIX_MODE(1));
348 }
349
350 /**
351 * Stop sending samples on the I2S bus
352 */
353 void audiohw_disable_recording(void)
354 {
355 uda1380_write_reg(REG_PGA, MUTE_ADC);
356 sleep(HZ/8);
357
358 uda1380_write_reg(REG_I2S, I2S_IFMT_IIS);
359
360 uda1380_regs[REG_PWR] &= ~(PON_LNA | PON_ADCL | PON_ADCR |
361 PON_PGAL | PON_PGAR);
362 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR]);
363
364 uda1380_regs[REG_0] &= ~EN_ADC;
365 uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ADC_CLK | DAC_CLK);
366
367 uda1380_write_reg(REG_ADC, SKIP_DCFIL);
368 }
369
370 /**
371 * Set recording gain and volume
372 *
373 * type: params: ranges:
374 * AUDIO_GAIN_MIC: left -128 .. 108 -> -64 .. 54 dB gain
375 * AUDIO_GAIN_LINEIN left & right -128 .. 96 -> -64 .. 48 dB gain
376 *
377 * Note: - For all types the value 0 gives 0 dB gain.
378 * - order of setting both values determines if the small glitch will
379 be a peak or a dip. The small glitch is caused by the time between
380 setting the two gains
381 */
382 void audiohw_set_recvol(int left, int right, int type)
383 {
384 int left_ag, right_ag;
385
386 switch (type)
387 {
388 case AUDIO_GAIN_MIC:
389 left_ag = MIN(MAX(0, left / 4), 15);
390 left -= left_ag * 4;
391
392 if(left < recgain_mic)
393 {
394 uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
395 | DEC_VOLR(left));
396 uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC]
397 & ~VGA_GAIN_MASK)
398 | VGA_GAIN(left_ag));
399 }
400 else
401 {
402 uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC]
403 & ~VGA_GAIN_MASK)
404 | VGA_GAIN(left_ag));
405 uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
406 | DEC_VOLR(left));
407 }
408 recgain_mic = left;
409 logf("Mic: %dA/%dD", left_ag, left);
410 break;
411
412 case AUDIO_GAIN_LINEIN:
413 left_ag = MIN(MAX(0, left / 6), 8);
414 left -= left_ag * 6;
415 right_ag = MIN(MAX(0, right / 6), 8);
416 right -= right_ag * 6;
417
418 if(left < recgain_line)
419 {
420 /* for this order we can combine both registers,
421 making the glitch even smaller */
422 unsigned char data[5];
423 unsigned short value_dec;
424 unsigned short value_pga;
425 value_dec = DEC_VOLL(left) | DEC_VOLR(right);
426 value_pga = (uda1380_regs[REG_PGA] & ~PGA_GAIN_MASK)
427 | PGA_GAINL(left_ag) | PGA_GAINR(right_ag);
428
429 data[0] = REG_DEC_VOL;
430 data[1] = value_dec >> 8;
431 data[2] = value_dec & 0xff;
432 data[3] = value_pga >> 8;
433 data[4] = value_pga & 0xff;
434
435 if (i2c_write(I2C_IFACE_0, UDA1380_ADDR, data, 5) != 5)
436 {
437 DEBUGF("uda1380 error reg=combi rec gain");
438 }
439 else
440 {
441 uda1380_regs[REG_DEC_VOL] = value_dec;
442 uda1380_regs[REG_PGA] = value_pga;
443 }
444 }
445 else
446 {
447 uda1380_write_reg(REG_PGA, (uda1380_regs[REG_PGA]
448 & ~PGA_GAIN_MASK)
449 | PGA_GAINL(left_ag)
450 | PGA_GAINR(right_ag));
451 uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
452 | DEC_VOLR(right));
453 }
454
455 recgain_line = left;
456 logf("Line L: %dA/%dD", left_ag, left);
457 logf("Line R: %dA/%dD", right_ag, right);
458 break;
459 }
460 }
461
462
463 /**
464 * Enable or disable recording monitor (so one can listen to the recording)
465 *
466 */
467 void audiohw_set_monitor(bool enable)
468 {
469 if (enable) /* enable channel 2 */
470 uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] & ~MUTE_CH2);
471 else /* mute channel 2 */
472 uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] | MUTE_CH2);
473 }
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