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Remove card_enable_monitoring() and use a mutex instead. The card_enable_monitoring...
[kugel-rb.git] / firmware / target / mips / ingenic_jz47xx / ata-sd-jz4740.c
blob8fdf7d02874deecf5c506a0de43a29c18ddfd39d
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Maurus Cuelenaere
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22 #include "config.h"
23 #include "jz4740.h"
24 #include "ata.h"
25 #include "ata_idle_notify.h"
26 #include "ata-sd-target.h"
27 #include "disk.h"
28 #include "fat.h"
29 #include "led.h"
30 #include "sdmmc.h"
31 #include "logf.h"
32 #include "sd.h"
33 #include "system.h"
34 #include "kernel.h"
35 #include "storage.h"
36 #include "string.h"
37 #include "usb.h"
38
39 static long last_disk_activity = -1;
40 #if defined(CONFIG_STORAGE_MULTI) || defined(HAVE_HOTSWAP)
41 static int sd_drive_nr = 0;
42 #endif
43 static tCardInfo card;
44
45 static long sd_stack[(DEFAULT_STACK_SIZE*2 + 0x1c0)/sizeof(long)];
46 static const char sd_thread_name[] = "ata/sd";
47 static struct event_queue sd_queue;
48 static struct mutex sd_mtx;
49 static struct wakeup sd_wakeup;
50 static void sd_thread(void) __attribute__((noreturn));
51
52 static int use_4bit;
53 static int num_6;
54 static int sd2_0;
55
56 //#define SD_DMA_ENABLE
57 #define SD_DMA_INTERRUPT 0
58
59 //#define DEBUG(x...) logf(x)
60 #define DEBUG(x, ...)
61
62 #define SD_INSERT_STATUS() __gpio_get_pin(MMC_CD_PIN)
63 #define SD_RESET() __msc_reset()
64
65 #define SD_IRQ_MASK() \
66 do { \
67 REG_MSC_IMASK = 0xffff; \
68 REG_MSC_IREG = 0xffff; \
69 } while (0)
70
71 /* Error codes */
72 enum sd_result_t
73 {
74 SD_NO_RESPONSE = -1,
75 SD_NO_ERROR = 0,
76 SD_ERROR_OUT_OF_RANGE,
77 SD_ERROR_ADDRESS,
78 SD_ERROR_BLOCK_LEN,
79 SD_ERROR_ERASE_SEQ,
80 SD_ERROR_ERASE_PARAM,
81 SD_ERROR_WP_VIOLATION,
82 SD_ERROR_CARD_IS_LOCKED,
83 SD_ERROR_LOCK_UNLOCK_FAILED,
84 SD_ERROR_COM_CRC,
85 SD_ERROR_ILLEGAL_COMMAND,
86 SD_ERROR_CARD_ECC_FAILED,
87 SD_ERROR_CC,
88 SD_ERROR_GENERAL,
89 SD_ERROR_UNDERRUN,
90 SD_ERROR_OVERRUN,
91 SD_ERROR_CID_CSD_OVERWRITE,
92 SD_ERROR_STATE_MISMATCH,
93 SD_ERROR_HEADER_MISMATCH,
94 SD_ERROR_TIMEOUT,
95 SD_ERROR_CRC,
96 SD_ERROR_DRIVER_FAILURE,
97 };
98
99 /* Standard MMC/SD clock speeds */
100 #define MMC_CLOCK_SLOW 400000 /* 400 kHz for initial setup */
101 #define SD_CLOCK_FAST 24000000 /* 24 MHz for SD Cards */
102 #define SD_CLOCK_HIGH 48000000 /* 48 MHz for SD Cards */
103
104 /* Extra commands for state control */
105 /* Use negative numbers to disambiguate */
106 #define SD_CIM_RESET -1
107
108 /* Proprietary commands, illegal/reserved according to SD Specification 2.00 */
109 /* class 1 */
110 #define SD_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
111
112 /* class 3 */
113 #define SD_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
114
115 /* class 4 */
116 #define SD_PROGRAM_CID 26 /* adtc R1 */
117 #define SD_PROGRAM_CSD 27 /* adtc R1 */
118
119 /* class 9 */
120 #define SD_GO_IRQ_STATE 40 /* bcr R5 */
121
122 /* Don't change the order of these; they are used in dispatch tables */
123 enum sd_rsp_t
124 {
125 RESPONSE_NONE = 0,
126 RESPONSE_R1 = 1,
127 RESPONSE_R1B = 2,
128 RESPONSE_R2_CID = 3,
129 RESPONSE_R2_CSD = 4,
130 RESPONSE_R3 = 5,
131 RESPONSE_R4 = 6,
132 RESPONSE_R5 = 7,
133 RESPONSE_R6 = 8,
134 RESPONSE_R7 = 9,
135 };
136
137 /*
138 MMC status in R1
139 Type
140 e : error bit
141 s : status bit
142 r : detected and set for the actual command response
143 x : detected and set during command execution. the host must poll
144 the card by sending status command in order to read these bits.
145 Clear condition
146 a : according to the card state
147 b : always related to the previous command. Reception of
148 a valid command will clear it (with a delay of one command)
149 c : clear by read
150 */
151
152 #define R1_OUT_OF_RANGE (1 << 31) /* er, c */
153 #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
154 #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
155 #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
156 #define R1_ERASE_PARAM (1 << 27) /* ex, c */
157 #define R1_WP_VIOLATION (1 << 26) /* erx, c */
158 #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
159 #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
160 #define R1_COM_CRC_ERROR (1 << 23) /* er, b */
161 #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
162 #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
163 #define R1_CC_ERROR (1 << 20) /* erx, c */
164 #define R1_ERROR (1 << 19) /* erx, c */
165 #define R1_UNDERRUN (1 << 18) /* ex, c */
166 #define R1_OVERRUN (1 << 17) /* ex, c */
167 #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
168 #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
169 #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
170 #define R1_ERASE_RESET (1 << 13) /* sr, c */
171 #define R1_STATUS(x) (x & 0xFFFFE000)
172 #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
173 #define R1_READY_FOR_DATA (1 << 8) /* sx, a */
174 #define R1_APP_CMD (1 << 7) /* sr, c */
175
176 /* These are unpacked versions of the actual responses */
177 struct sd_response_r1
178 {
179 unsigned char cmd;
180 unsigned int status;
181 };
182
183 struct sd_response_r3
184 {
185 unsigned int ocr;
186 };
187
188 #define SD_CARD_BUSY 0x80000000 /* Card Power up status bit */
189
190 struct sd_request
191 {
192 int index; /* Slot index - used for CS lines */
193 int cmd; /* Command to send */
194 unsigned int arg; /* Argument to send */
195 enum sd_rsp_t rtype; /* Response type expected */
196
197 /* Data transfer (these may be modified at the low level) */
198 unsigned short nob; /* Number of blocks to transfer*/
199 unsigned short block_len; /* Block length */
200 unsigned char *buffer; /* Data buffer */
201 unsigned int cnt; /* Data length, for PIO */
202
203 /* Results */
204 unsigned char response[18]; /* Buffer to store response - CRC is optional */
205 enum sd_result_t result;
206 };
207
208 #define SD_OCR_ARG 0x00ff8000 /* Argument of OCR */
209
210 /***********************************************************************
211 * SD Events
212 */
213 #define SD_EVENT_NONE 0x00 /* No events */
214 #define SD_EVENT_RX_DATA_DONE 0x01 /* Rx data done */
215 #define SD_EVENT_TX_DATA_DONE 0x02 /* Tx data done */
216 #define SD_EVENT_PROG_DONE 0x04 /* Programming is done */
217
218 /**************************************************************************
219 * Utility functions
220 **************************************************************************/
221
222 #define PARSE_U32(_buf,_index) \
223 (((unsigned int)_buf[_index]) << 24) | (((unsigned int)_buf[_index+1]) << 16) | \
224 (((unsigned int)_buf[_index+2]) << 8) | ((unsigned int)_buf[_index+3]);
225
226 #define PARSE_U16(_buf,_index) \
227 (((unsigned short)_buf[_index]) << 8) | ((unsigned short)_buf[_index+1]);
228
229 static int sd_unpack_r1(struct sd_request *request, struct sd_response_r1 *r1)
230 {
231 unsigned char *buf = request->response;
232
233 if (request->result)
234 return request->result;
235
236 r1->cmd = buf[0];
237 r1->status = PARSE_U32(buf,1);
238
239 DEBUG("sd_unpack_r1: cmd=%d status=%08x", r1->cmd, r1->status);
240
241 if (R1_STATUS(r1->status)) {
242 if (r1->status & R1_OUT_OF_RANGE) return SD_ERROR_OUT_OF_RANGE;
243 if (r1->status & R1_ADDRESS_ERROR) return SD_ERROR_ADDRESS;
244 if (r1->status & R1_BLOCK_LEN_ERROR) return SD_ERROR_BLOCK_LEN;
245 if (r1->status & R1_ERASE_SEQ_ERROR) return SD_ERROR_ERASE_SEQ;
246 if (r1->status & R1_ERASE_PARAM) return SD_ERROR_ERASE_PARAM;
247 if (r1->status & R1_WP_VIOLATION) return SD_ERROR_WP_VIOLATION;
248 //if (r1->status & R1_CARD_IS_LOCKED) return SD_ERROR_CARD_IS_LOCKED;
249 if (r1->status & R1_LOCK_UNLOCK_FAILED) return SD_ERROR_LOCK_UNLOCK_FAILED;
250 if (r1->status & R1_COM_CRC_ERROR) return SD_ERROR_COM_CRC;
251 if (r1->status & R1_ILLEGAL_COMMAND) return SD_ERROR_ILLEGAL_COMMAND;
252 if (r1->status & R1_CARD_ECC_FAILED) return SD_ERROR_CARD_ECC_FAILED;
253 if (r1->status & R1_CC_ERROR) return SD_ERROR_CC;
254 if (r1->status & R1_ERROR) return SD_ERROR_GENERAL;
255 if (r1->status & R1_UNDERRUN) return SD_ERROR_UNDERRUN;
256 if (r1->status & R1_OVERRUN) return SD_ERROR_OVERRUN;
257 if (r1->status & R1_CID_CSD_OVERWRITE) return SD_ERROR_CID_CSD_OVERWRITE;
258 }
259
260 if (buf[0] != request->cmd)
261 return SD_ERROR_HEADER_MISMATCH;
262
263 /* This should be last - it's the least dangerous error */
264
265 return 0;
266 }
267
268 static int sd_unpack_r6(struct sd_request *request, struct sd_response_r1 *r1, unsigned long *rca)
269 {
270 unsigned char *buf = request->response;
271
272 if (request->result)
273 return request->result;
274
275 *rca = PARSE_U16(buf,1); /* Save RCA returned by the SD Card */
276
277 *(buf+1) = 0;
278 *(buf+2) = 0;
279
280 return sd_unpack_r1(request, r1);
281 }
282
283 static int sd_unpack_r3(struct sd_request *request, struct sd_response_r3 *r3)
284 {
285 unsigned char *buf = request->response;
286
287 if (request->result) return request->result;
288
289 r3->ocr = PARSE_U32(buf,1);
290 DEBUG("sd_unpack_r3: ocr=%08x", r3->ocr);
291
292 if (buf[0] != 0x3f)
293 return SD_ERROR_HEADER_MISMATCH;
294
295 return 0;
296 }
297
298 /* Stop the MMC clock and wait while it happens */
299 static inline int jz_sd_stop_clock(void)
300 {
301 register int timeout = 1000;
302
303 //DEBUG("stop MMC clock");
304 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP;
305
306 while (timeout && (REG_MSC_STAT & MSC_STAT_CLK_EN))
307 {
308 timeout--;
309 if (timeout == 0)
310 {
311 DEBUG("Timeout on stop clock waiting");
312 return SD_ERROR_TIMEOUT;
313 }
314 udelay(1);
315 }
316 //DEBUG("clock off time is %d microsec", timeout);
317 return SD_NO_ERROR;
318 }
319
320 /* Start the MMC clock and operation */
321 static inline int jz_sd_start_clock(void)
322 {
323 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP;
324 return SD_NO_ERROR;
325 }
326
327 static int jz_sd_check_status(struct sd_request *request)
328 {
329 (void)request;
330 unsigned int status = REG_MSC_STAT;
331
332 /* Checking for response or data timeout */
333 if (status & (MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ))
334 {
335 DEBUG("SD timeout, MSC_STAT 0x%x CMD %d", status,
336 request->cmd);
337 return SD_ERROR_TIMEOUT;
338 }
339
340 /* Checking for CRC error */
341 if (status &
342 (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR |
343 MSC_STAT_CRC_RES_ERR))
344 {
345 DEBUG("SD CRC error, MSC_STAT 0x%x", status);
346 return SD_ERROR_CRC;
347
348 }
349
350
351 /* Checking for FIFO empty */
352 /*if(status & MSC_STAT_DATA_FIFO_EMPTY && request->rtype != RESPONSE_NONE)
353 {
354 DEBUG("SD FIFO empty, MSC_STAT 0x%x", status);
355 return SD_ERROR_UNDERRUN;
356 }*/
357
358 return SD_NO_ERROR;
359 }
360
361 /* Obtain response to the command and store it to response buffer */
362 static void jz_sd_get_response(struct sd_request *request)
363 {
364 int i;
365 unsigned char *buf;
366 unsigned int data;
367
368 DEBUG("fetch response for request %d, cmd %d", request->rtype,
369 request->cmd);
370 buf = request->response;
371 request->result = SD_NO_ERROR;
372
373 switch (request->rtype)
374 {
375 case RESPONSE_R1:
376 case RESPONSE_R1B:
377 case RESPONSE_R7:
378 case RESPONSE_R6:
379 case RESPONSE_R3:
380 case RESPONSE_R4:
381 case RESPONSE_R5:
382 {
383 data = REG_MSC_RES;
384 buf[0] = (data >> 8) & 0xff;
385 buf[1] = data & 0xff;
386 data = REG_MSC_RES;
387 buf[2] = (data >> 8) & 0xff;
388 buf[3] = data & 0xff;
389 data = REG_MSC_RES;
390 buf[4] = data & 0xff;
391
392 DEBUG("request %d, response [%02x %02x %02x %02x %02x]",
393 request->rtype, buf[0], buf[1], buf[2],
394 buf[3], buf[4]);
395 break;
396 }
397 case RESPONSE_R2_CID:
398 case RESPONSE_R2_CSD:
399 {
400 for (i = 0; i < 16; i += 2)
401 {
402 data = REG_MSC_RES;
403 buf[i] = (data >> 8) & 0xff;
404 buf[i + 1] = data & 0xff;
405 }
406 DEBUG("request %d, response []", request->rtype);
407 break;
408 }
409 case RESPONSE_NONE:
410 DEBUG("No response");
411 break;
412
413 default:
414 DEBUG("unhandled response type for request %d",
415 request->rtype);
416 break;
417 }
418 }
419
420 #ifdef SD_DMA_ENABLE
421 static void jz_sd_receive_data_dma(struct sd_request *req)
422 {
423 unsigned int size = req->block_len * req->nob;
424 #if MMC_DMA_INTERRUPT
425 unsigned char err = 0;
426 #endif
427
428 /* flush dcache */
429 //dma_cache_wback_inv((unsigned long) req->buffer, size);
430 /* setup dma channel */
431 REG_DMAC_DSAR(DMA_SD_RX_CHANNEL) = PHYSADDR(MSC_RXFIFO); /* DMA source addr */
432 REG_DMAC_DTAR(DMA_SD_RX_CHANNEL) = PHYSADDR((unsigned long) req->buffer); /* DMA dest addr */
433 REG_DMAC_DTCR(DMA_SD_RX_CHANNEL) = (size + 3) / 4; /* DMA transfer count */
434 REG_DMAC_DRSR(DMA_SD_RX_CHANNEL) = DMAC_DRSR_RS_MSCIN; /* DMA request type */
435
436 #if SD_DMA_INTERRUPT
437 REG_DMAC_DCMD(DMA_SD_RX_CHANNEL) =
438 DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
439 DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE;
440 REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
441 OSSemPend(sd_dma_rx_sem, 100, &err);
442 #else
443 REG_DMAC_DCMD(DMA_SD_RX_CHANNEL) =
444 DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
445 DMAC_DCMD_DS_32BIT;
446 REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
447
448 //while (REG_DMAC_DTCR(DMA_SD_RX_CHANNEL));
449 while( !(REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) & DMAC_DCCSR_TT) );
450 #endif
451
452 /* clear status and disable channel */
453 REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = 0;
454 }
455
456 static void jz_mmc_transmit_data_dma(struct mmc_request *req)
457 {
458 unsigned int size = req->block_len * req->nob;
459 #if SD_DMA_INTERRUPT
460 unsigned char err = 0;
461 #endif
462
463 /* flush dcache */
464 //dma_cache_wback_inv((unsigned long) req->buffer, size);
465 /* setup dma channel */
466 REG_DMAC_DSAR(DMA_SD_TX_CHANNEL) = PHYSADDR((unsigned long) req->buffer); /* DMA source addr */
467 REG_DMAC_DTAR(DMA_SD_TX_CHANNEL) = PHYSADDR(MSC_TXFIFO); /* DMA dest addr */
468 REG_DMAC_DTCR(DMA_SD_TX_CHANNEL) = (size + 3) / 4; /* DMA transfer count */
469 REG_DMAC_DRSR(DMA_SD_TX_CHANNEL) = DMAC_DRSR_RS_MSCOUT; /* DMA request type */
470
471 #if SD_DMA_INTERRUPT
472 REG_DMAC_DCMD(DMA_SD_TX_CHANNEL) =
473 DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
474 DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE;
475 REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
476 OSSemPend(sd_dma_tx_sem, 100, &err);
477 #else
478 REG_DMAC_DCMD(DMA_SD_TX_CHANNEL) =
479 DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
480 DMAC_DCMD_DS_32BIT;
481 REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
482 /* wait for dma completion */
483 while( !(REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) & DMAC_DCCSR_TT) );
484 #endif
485 /* clear status and disable channel */
486
487 REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = 0;
488 }
489
490 #else /* SD_DMA_ENABLE */
491
492 static int jz_sd_receive_data(struct sd_request *req)
493 {
494 unsigned int nob = req->nob;
495 unsigned int wblocklen = (unsigned int) (req->block_len + 3) >> 2; /* length in word */
496 unsigned char *buf = req->buffer;
497 unsigned int *wbuf = (unsigned int *) buf;
498 unsigned int waligned = (((unsigned int) buf & 0x3) == 0); /* word aligned ? */
499 unsigned int stat, timeout, data, cnt;
500
501 for (; nob >= 1; nob--)
502 {
503 timeout = 0x3FFFFFF;
504
505 while (timeout)
506 {
507 timeout--;
508 stat = REG_MSC_STAT;
509
510 if (stat & MSC_STAT_TIME_OUT_READ)
511 return SD_ERROR_TIMEOUT;
512 else if (stat & MSC_STAT_CRC_READ_ERROR)
513 return SD_ERROR_CRC;
514 else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY)
515 || (stat & MSC_STAT_DATA_FIFO_AFULL))
516 /* Ready to read data */
517 break;
518
519 udelay(1);
520 }
521
522 if (!timeout)
523 return SD_ERROR_TIMEOUT;
524
525 /* Read data from RXFIFO. It could be FULL or PARTIAL FULL */
526 DEBUG("Receive Data = %d", wblocklen);
527 cnt = wblocklen;
528 while (cnt)
529 {
530 data = REG_MSC_RXFIFO;
531 if (waligned)
532 *wbuf++ = data;
533 else
534 {
535 *buf++ = (unsigned char) (data >> 0);
536 *buf++ = (unsigned char) (data >> 8);
537 *buf++ = (unsigned char) (data >> 16);
538 *buf++ = (unsigned char) (data >> 24);
539 }
540 cnt--;
541 while (cnt
542 && (REG_MSC_STAT &
543 MSC_STAT_DATA_FIFO_EMPTY));
544 }
545 }
546
547 return SD_NO_ERROR;
548 }
549
550 static int jz_sd_transmit_data(struct sd_request *req)
551 {
552 unsigned int nob = req->nob;
553 unsigned int wblocklen = (unsigned int) (req->block_len + 3) >> 2; /* length in word */
554 unsigned char *buf = req->buffer;
555 unsigned int *wbuf = (unsigned int *) buf;
556 unsigned int waligned = (((unsigned int) buf & 0x3) == 0); /* word aligned ? */
557 unsigned int stat, timeout, data, cnt;
558
559 for (; nob >= 1; nob--)
560 {
561 timeout = 0x3FFFFFF;
562
563 while (timeout)
564 {
565 timeout--;
566 stat = REG_MSC_STAT;
567
568 if (stat &
569 (MSC_STAT_CRC_WRITE_ERROR |
570 MSC_STAT_CRC_WRITE_ERROR_NOSTS))
571 return SD_ERROR_CRC;
572 else if (!(stat & MSC_STAT_DATA_FIFO_FULL))
573 /* Ready to write data */
574 break;
575
576 udelay(1);
577 }
578
579 if (!timeout)
580 return SD_ERROR_TIMEOUT;
581
582 /* Write data to TXFIFO */
583 cnt = wblocklen;
584 while (cnt)
585 {
586 while (REG_MSC_STAT & MSC_STAT_DATA_FIFO_FULL);
587
588 if (waligned)
589 REG_MSC_TXFIFO = *wbuf++;
590 else
591 {
592 data = *buf++;
593 data |= *buf++ << 8;
594 data |= *buf++ << 16;
595 data |= *buf++ << 24;
596 REG_MSC_TXFIFO = data;
597 }
598
599 cnt--;
600 }
601 }
602
603 return SD_NO_ERROR;
604 }
605 #endif
606
607 static inline unsigned int jz_sd_calc_clkrt(unsigned int rate)
608 {
609 unsigned int clkrt;
610 unsigned int clk_src = sd2_0 ? SD_CLOCK_HIGH : SD_CLOCK_FAST;
611
612 clkrt = 0;
613 while (rate < clk_src)
614 {
615 clkrt++;
616 clk_src >>= 1;
617 }
618 return clkrt;
619 }
620
621 static inline void cpm_select_msc_clk(unsigned int rate)
622 {
623 unsigned int div = __cpm_get_pllout2() / rate;
624
625 REG_CPM_MSCCDR = div - 1;
626 }
627
628 /* Set the MMC clock frequency */
629 static void jz_sd_set_clock(unsigned int rate)
630 {
631 int clkrt;
632
633 jz_sd_stop_clock();
634
635 /* select clock source from CPM */
636 cpm_select_msc_clk(rate);
637
638 REG_CPM_CPCCR |= CPM_CPCCR_CE;
639 clkrt = jz_sd_calc_clkrt(rate);
640 REG_MSC_CLKRT = clkrt;
641
642 DEBUG("set clock to %u Hz clkrt=%d", rate, clkrt);
643 }
644
645 /********************************************************************************************************************
646 ** Name: int jz_sd_exec_cmd()
647 ** Function: send command to the card, and get a response
648 ** Input: struct sd_request *req: SD request
649 ** Output: 0: right >0: error code
650 ********************************************************************************************************************/
651 static int jz_sd_exec_cmd(struct sd_request *request)
652 {
653 unsigned int cmdat = 0, events = 0;
654 int retval, timeout = 0x3fffff;
655
656 /* Indicate we have no result yet */
657 request->result = SD_NO_RESPONSE;
658
659 if (request->cmd == SD_CIM_RESET) {
660 /* On reset, 1-bit bus width */
661 use_4bit = 0;
662
663 /* Reset MMC/SD controller */
664 __msc_reset();
665
666 /* On reset, drop SD clock down */
667 jz_sd_set_clock(MMC_CLOCK_SLOW);
668
669 /* On reset, stop SD clock */
670 jz_sd_stop_clock();
671 }
672 if (request->cmd == SD_SET_BUS_WIDTH)
673 {
674 if (request->arg == 0x2)
675 {
676 DEBUG("Use 4-bit bus width");
677 use_4bit = 1;
678 }
679 else
680 {
681 DEBUG("Use 1-bit bus width");
682 use_4bit = 0;
683 }
684 }
685
686 /* stop clock */
687 jz_sd_stop_clock();
688
689 /* mask all interrupts */
690 //REG_MSC_IMASK = 0xffff;
691 /* clear status */
692 REG_MSC_IREG = 0xffff;
693 /*open interrupt */
694 REG_MSC_IMASK = (~7);
695 /* use 4-bit bus width when possible */
696 if (use_4bit)
697 cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT;
698
699 /* Set command type and events */
700 switch (request->cmd)
701 {
702 /* SD core extra command */
703 case SD_CIM_RESET:
704 cmdat |= MSC_CMDAT_INIT; /* Initialization sequence sent prior to command */
705 break;
706 /* bc - broadcast - no response */
707 case SD_GO_IDLE_STATE:
708 case SD_SET_DSR:
709 break;
710
711 /* bcr - broadcast with response */
712 case SD_APP_OP_COND:
713 case SD_ALL_SEND_CID:
714 case SD_GO_IRQ_STATE:
715 break;
716
717 /* adtc - addressed with data transfer */
718 case SD_READ_DAT_UNTIL_STOP:
719 case SD_READ_SINGLE_BLOCK:
720 case SD_READ_MULTIPLE_BLOCK:
721 case SD_SEND_SCR:
722 #if defined(SD_DMA_ENABLE)
723 cmdat |=
724 MSC_CMDAT_DATA_EN | MSC_CMDAT_READ | MSC_CMDAT_DMA_EN;
725 #else
726 cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
727 #endif
728 events = SD_EVENT_RX_DATA_DONE;
729 break;
730
731 case 6:
732 if (num_6 < 2)
733 {
734 #if defined(SD_DMA_ENABLE)
735 cmdat |=
736 MSC_CMDAT_DATA_EN | MSC_CMDAT_READ |
737 MSC_CMDAT_DMA_EN;
738 #else
739 cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
740 #endif
741 events = SD_EVENT_RX_DATA_DONE;
742 }
743 break;
744
745 case SD_WRITE_DAT_UNTIL_STOP:
746 case SD_WRITE_BLOCK:
747 case SD_WRITE_MULTIPLE_BLOCK:
748 case SD_PROGRAM_CID:
749 case SD_PROGRAM_CSD:
750 case SD_LOCK_UNLOCK:
751 #if defined(SD_DMA_ENABLE)
752 cmdat |=
753 MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE | MSC_CMDAT_DMA_EN;
754 #else
755 cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE;
756 #endif
757 events = SD_EVENT_TX_DATA_DONE | SD_EVENT_PROG_DONE;
758 break;
759
760 case SD_STOP_TRANSMISSION:
761 events = SD_EVENT_PROG_DONE;
762 break;
763
764 /* ac - no data transfer */
765 default:
766 break;
767 }
768
769 /* Set response type */
770 switch (request->rtype)
771 {
772 case RESPONSE_NONE:
773 break;
774 case RESPONSE_R1B:
775 cmdat |= MSC_CMDAT_BUSY;
776 /* FALLTHRU */
777 case RESPONSE_R1:
778 case RESPONSE_R7:
779 cmdat |= MSC_CMDAT_RESPONSE_R1;
780 break;
781 case RESPONSE_R2_CID:
782 case RESPONSE_R2_CSD:
783 cmdat |= MSC_CMDAT_RESPONSE_R2;
784 break;
785 case RESPONSE_R3:
786 cmdat |= MSC_CMDAT_RESPONSE_R3;
787 break;
788 case RESPONSE_R4:
789 cmdat |= MSC_CMDAT_RESPONSE_R4;
790 break;
791 case RESPONSE_R5:
792 cmdat |= MSC_CMDAT_RESPONSE_R5;
793 break;
794 case RESPONSE_R6:
795 cmdat |= MSC_CMDAT_RESPONSE_R6;
796 break;
797 default:
798 break;
799 }
800
801 /* Set command index */
802 if (request->cmd == SD_CIM_RESET)
803 REG_MSC_CMD = SD_GO_IDLE_STATE;
804 else
805 REG_MSC_CMD = request->cmd;
806
807 /* Set argument */
808 REG_MSC_ARG = request->arg;
809
810 /* Set block length and nob */
811 if (request->cmd == SD_SEND_SCR)
812 { /* get SCR from DataFIFO */
813 REG_MSC_BLKLEN = 8;
814 REG_MSC_NOB = 1;
815 }
816 else
817 {
818 REG_MSC_BLKLEN = request->block_len;
819 REG_MSC_NOB = request->nob;
820 }
821
822 /* Set command */
823 REG_MSC_CMDAT = cmdat;
824
825 DEBUG("Send cmd %d cmdat: %x arg: %x resp %d", request->cmd,
826 cmdat, request->arg, request->rtype);
827
828 /* Start SD clock and send command to card */
829 jz_sd_start_clock();
830
831 /* Wait for command completion */
832 //__intc_unmask_irq(IRQ_MSC);
833 //wakeup_wait(&sd_wakeup, 100);
834 while (timeout-- && !(REG_MSC_STAT & MSC_STAT_END_CMD_RES));
835
836
837 if (timeout == 0)
838 return SD_ERROR_TIMEOUT;
839
840 REG_MSC_IREG = MSC_IREG_END_CMD_RES; /* clear flag */
841
842 /* Check for status */
843 retval = jz_sd_check_status(request);
844 if (retval)
845 return retval;
846
847 /* Complete command with no response */
848 if (request->rtype == RESPONSE_NONE)
849 return SD_NO_ERROR;
850
851 /* Get response */
852 jz_sd_get_response(request);
853
854 /* Start data operation */
855 if (events & (SD_EVENT_RX_DATA_DONE | SD_EVENT_TX_DATA_DONE))
856 {
857 if (events & SD_EVENT_RX_DATA_DONE)
858 {
859 if (request->cmd == SD_SEND_SCR)
860 {
861 /* SD card returns SCR register as data.
862 SD core expect it in the response buffer,
863 after normal response. */
864 request->buffer =
865 (unsigned char *) ((unsigned int) request->response + 5);
866 }
867 #ifdef SD_DMA_ENABLE
868 jz_sd_receive_data_dma(request);
869 #else
870 jz_sd_receive_data(request);
871 #endif
872 }
873
874 if (events & SD_EVENT_TX_DATA_DONE)
875 {
876 #ifdef SD_DMA_ENABLE
877 jz_sd_transmit_data_dma(request);
878 #else
879 jz_sd_transmit_data(request);
880 #endif
881 }
882 //__intc_unmask_irq(IRQ_MSC);
883 //wakeup_wait(&sd_wakeup, 100);
884 /* Wait for Data Done */
885 while (!(REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE));
886 REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE; /* clear status */
887 }
888
889 /* Wait for Prog Done event */
890 if (events & SD_EVENT_PROG_DONE)
891 {
892 //__intc_unmask_irq(IRQ_MSC);
893 //wakeup_wait(&sd_wakeup, 100);
894 while (!(REG_MSC_IREG & MSC_IREG_PRG_DONE));
895 REG_MSC_IREG = MSC_IREG_PRG_DONE; /* clear status */
896 }
897
898 /* Command completed */
899
900 return SD_NO_ERROR; /* return successfully */
901 }
902
903 /*******************************************************************************************************************
904 ** Name: int sd_chkcard()
905 ** Function: check whether card is insert entirely
906 ** Input: NULL
907 ** Output: 1: insert entirely 0: not insert entirely
908 ********************************************************************************************************************/
909 static int jz_sd_chkcard(void)
910 {
911 return (SD_INSERT_STATUS() == 0 ? 1 : 0);
912 }
913
914 #if SD_DMA_INTERRUPT
915 static void jz_sd_tx_handler(unsigned int arg)
916 {
917 if (__dmac_channel_address_error_detected(arg))
918 {
919 DEBUG("%s: DMAC address error.", __FUNCTION__);
920 __dmac_channel_clear_address_error(arg);
921 }
922 if (__dmac_channel_transmit_end_detected(arg))
923 {
924 __dmac_channel_clear_transmit_end(arg);
925 OSSemPost(sd_dma_tx_sem);
926 }
927 }
928
929 static void jz_sd_rx_handler(unsigned int arg)
930 {
931 if (__dmac_channel_address_error_detected(arg))
932 {
933 DEBUG("%s: DMAC address error.", __FUNCTION__);
934 __dmac_channel_clear_address_error(arg);
935 }
936 if (__dmac_channel_transmit_end_detected(arg))
937 {
938 __dmac_channel_clear_transmit_end(arg);
939 OSSemPost(sd_dma_rx_sem);
940 }
941 }
942 #endif
943
944 /* MSC interrupt handler */
945 void MSC(void)
946 {
947 //wakeup_signal(&sd_wakeup);
948 logf("MSC interrupt");
949 }
950
951 static void sd_gpio_setup_irq(bool inserted)
952 {
953 if(inserted)
954 __gpio_as_irq_rise_edge(MMC_CD_PIN);
955 else
956 __gpio_as_irq_fall_edge(MMC_CD_PIN);
957 }
958
959 /*******************************************************************************************************************
960 ** Name: void sd_hardware_init()
961 ** Function: initialize the hardware condiction that access sd card
962 ** Input: NULL
963 ** Output: NULL
964 ********************************************************************************************************************/
965 static void jz_sd_hardware_init(void)
966 {
967 __cpm_start_msc(); /* enable mmc clock */
968 sd_init_gpio(); /* init GPIO */
969 sd_gpio_setup_irq(jz_sd_chkcard());
970 #ifdef SD_POWER_ON
971 SD_POWER_ON(); /* turn on power of card */
972 #endif
973 SD_RESET(); /* reset mmc/sd controller */
974 SD_IRQ_MASK(); /* mask all IRQs */
975 jz_sd_stop_clock(); /* stop SD clock */
976 #ifdef SD_DMA_ENABLE
977 // __cpm_start_dmac();
978 // __dmac_enable_module();
979 // REG_DMAC_DMACR = DMAC_DMACR_DME;
980 #if SD_DMA_INTERRUPT
981 sd_dma_rx_sem = OSSemCreate(0);
982 sd_dma_tx_sem = OSSemCreate(0);
983 request_irq(IRQ_DMA_0 + RX_DMA_CHANNEL, jz_sd_rx_handler,
984 RX_DMA_CHANNEL);
985 request_irq(IRQ_DMA_0 + TX_DMA_CHANNEL, jz_sd_tx_handler,
986 TX_DMA_CHANNEL);
987 #endif
988 #endif
989 }
990
991 static int sd_send_cmd(struct sd_request *request, int cmd, unsigned int arg,
992 unsigned short nob, unsigned short block_len,
993 enum sd_rsp_t rtype, unsigned char* buffer)
994 {
995 request->cmd = cmd;
996 request->arg = arg;
997 request->rtype = rtype;
998 request->nob = nob;
999 request->block_len = block_len;
1000 request->buffer = buffer;
1001 request->cnt = nob * block_len;
1002
1003 return jz_sd_exec_cmd(request);
1004 }
1005
1006 static void sd_simple_cmd(struct sd_request *request, int cmd, unsigned int arg,
1007 enum sd_rsp_t rtype)
1008 {
1009 sd_send_cmd(request, cmd, arg, 0, 0, rtype, NULL);
1010 }
1011
1012 #define SD_INIT_DOING 0
1013 #define SD_INIT_PASSED 1
1014 #define SD_INIT_FAILED 2
1015 static int sd_init_card_state(struct sd_request *request)
1016 {
1017 struct sd_response_r1 r1;
1018 struct sd_response_r3 r3;
1019 int retval, i, ocr = 0x40300000, limit_41 = 0;
1020
1021 switch (request->cmd)
1022 {
1023 case SD_GO_IDLE_STATE: /* No response to parse */
1024 sd_simple_cmd(request, SD_SEND_IF_COND, 0x1AA, RESPONSE_R1);
1025 break;
1026
1027 case SD_SEND_IF_COND:
1028 retval = sd_unpack_r1(request, &r1);
1029 sd_simple_cmd(request, SD_APP_CMD, 0, RESPONSE_R1);
1030 break;
1031
1032 case SD_APP_CMD:
1033 retval = sd_unpack_r1(request, &r1);
1034 if (retval & (limit_41 < 100))
1035 {
1036 DEBUG("sd_init_card_state: unable to SD_APP_CMD error=%d",
1037 retval);
1038 limit_41++;
1039 sd_simple_cmd(request, SD_APP_OP_COND, ocr, RESPONSE_R3);
1040 }
1041 else if (limit_41 < 100)
1042 {
1043 limit_41++;
1044 sd_simple_cmd(request, SD_APP_OP_COND, ocr, RESPONSE_R3);
1045 }
1046 else
1047 /* reset the card to idle*/
1048 sd_simple_cmd(request, SD_GO_IDLE_STATE, 0, RESPONSE_NONE);
1049 break;
1050
1051 case SD_APP_OP_COND:
1052 retval = sd_unpack_r3(request, &r3);
1053 if (retval)
1054 break;
1055
1056 DEBUG("sd_init_card_state: read ocr value = 0x%08x", r3.ocr);
1057 card.ocr = r3.ocr;
1058
1059 if(!(r3.ocr & SD_CARD_BUSY || ocr == 0))
1060 {
1061 sleep(HZ / 100);
1062 sd_simple_cmd(request, SD_APP_CMD, 0, RESPONSE_R1);
1063 }
1064 else
1065 {
1066 /* Set the data bus width to 4 bits */
1067 use_4bit = 1;
1068 sd_simple_cmd(request, SD_ALL_SEND_CID, 0, RESPONSE_R2_CID);
1069 }
1070 break;
1071
1072 case SD_ALL_SEND_CID:
1073 for(i=0; i<4; i++)
1074 card.cid[i] = ((request->response[1+i*4]<<24) | (request->response[2+i*4]<<16) |
1075 (request->response[3+i*4]<< 8) | request->response[4+i*4]);
1076
1077 logf("CID: %08lx%08lx%08lx%08lx", card.cid[0], card.cid[1], card.cid[2], card.cid[3]);
1078 sd_simple_cmd(request, SD_SEND_RELATIVE_ADDR, 0, RESPONSE_R6);
1079 break;
1080 case SD_SEND_RELATIVE_ADDR:
1081 retval = sd_unpack_r6(request, &r1, &card.rca);
1082 card.rca = card.rca << 16;
1083 DEBUG("sd_init_card_state: Get RCA from SD: 0x%04lx Status: %x", card.rca, r1.status);
1084 if (retval)
1085 {
1086 DEBUG("sd_init_card_state: unable to SET_RELATIVE_ADDR error=%d",
1087 retval);
1088 return SD_INIT_FAILED;
1089 }
1090
1091 sd_simple_cmd(request, SD_SEND_CSD, card.rca, RESPONSE_R2_CSD);
1092 break;
1093
1094 case SD_SEND_CSD:
1095 for(i=0; i<4; i++)
1096 card.csd[i] = ((request->response[1+i*4]<<24) | (request->response[2+i*4]<<16) |
1097 (request->response[3+i*4]<< 8) | request->response[4+i*4]);
1098
1099 sd_parse_csd(&card);
1100 sd2_0 = (card_extract_bits(card.csd, 127, 2) == 1);
1101
1102 logf("CSD: %08lx%08lx%08lx%08lx", card.csd[0], card.csd[1], card.csd[2], card.csd[3]);
1103 DEBUG("SD card is ready");
1104 jz_sd_set_clock(SD_CLOCK_FAST);
1105 return SD_INIT_PASSED;
1106
1107 default:
1108 DEBUG("sd_init_card_state: error! Illegal last cmd %d", request->cmd);
1109 return SD_INIT_FAILED;
1110 }
1111
1112 return SD_INIT_DOING;
1113 }
1114
1115 static int sd_switch(struct sd_request *request, int mode, int group,
1116 unsigned char value, unsigned char * resp)
1117 {
1118 unsigned int arg;
1119
1120 mode = !!mode;
1121 value &= 0xF;
1122 arg = (mode << 31 | 0x00FFFFFF);
1123 arg &= ~(0xF << (group * 4));
1124 arg |= value << (group * 4);
1125 sd_send_cmd(request, 6, arg, 1, 64, RESPONSE_R1, resp);
1126
1127 return 0;
1128 }
1129
1130 /*
1131 * Fetches and decodes switch information
1132 */
1133 static int sd_read_switch(struct sd_request *request)
1134 {
1135 unsigned int status[64 / 4];
1136
1137 memset((unsigned char *)status, 0, 64);
1138 sd_switch(request, 0, 0, 1, (unsigned char*) status);
1139
1140 if (((unsigned char *)status)[13] & 0x02)
1141 return 0;
1142 else
1143 return 1;
1144 }
1145
1146 /*
1147 * Test if the card supports high-speed mode and, if so, switch to it.
1148 */
1149 static int sd_switch_hs(struct sd_request *request)
1150 {
1151 unsigned int status[64 / 4];
1152
1153 sd_switch(request, 1, 0, 1, (unsigned char*) status);
1154 return 0;
1155 }
1156
1157 static int sd_select_card(void)
1158 {
1159 struct sd_request request;
1160 struct sd_response_r1 r1;
1161 int retval;
1162
1163 sd_simple_cmd(&request, SD_SELECT_CARD, card.rca,
1164 RESPONSE_R1B);
1165 retval = sd_unpack_r1(&request, &r1);
1166 if (retval)
1167 return retval;
1168
1169 if (sd2_0)
1170 {
1171 retval = sd_read_switch(&request);
1172 if (!retval)
1173 {
1174 sd_switch_hs(&request);
1175 jz_sd_set_clock(SD_CLOCK_HIGH);
1176 }
1177 }
1178 num_6 = 3;
1179 sd_simple_cmd(&request, SD_APP_CMD, card.rca,
1180 RESPONSE_R1);
1181 retval = sd_unpack_r1(&request, &r1);
1182 if (retval)
1183 return retval;
1184 sd_simple_cmd(&request, SD_SET_BUS_WIDTH, 2, RESPONSE_R1);
1185 retval = sd_unpack_r1(&request, &r1);
1186 if (retval)
1187 return retval;
1188
1189 card.initialized = 1;
1190
1191 return 0;
1192 }
1193
1194 static int sd_init_device(void)
1195 {
1196 int retval;
1197 struct sd_request init_req;
1198
1199 mutex_lock(&sd_mtx);
1200
1201 /* Initialise card data as blank */
1202 memset(&card, 0, sizeof(tCardInfo));
1203
1204 sd2_0 = 0;
1205 num_6 = 0;
1206 use_4bit = 0;
1207
1208 /* reset mmc/sd controller */
1209 jz_sd_hardware_init();
1210
1211 sd_simple_cmd(&init_req, SD_CIM_RESET, 0, RESPONSE_NONE);
1212 sd_simple_cmd(&init_req, SD_GO_IDLE_STATE, 0, RESPONSE_NONE);
1213
1214 sleep(HZ/2); /* Give the card/controller some rest */
1215
1216 while((retval = sd_init_card_state(&init_req)) == SD_INIT_DOING);
1217 retval = (retval == SD_INIT_PASSED ? sd_select_card() : -1);
1218
1219 __cpm_stop_msc(); /* disable SD clock */
1220 mutex_unlock(&sd_mtx);
1221
1222 return retval;
1223 }
1224
1225 int sd_init(void)
1226 {
1227 static bool inited = false;
1228 if(!inited)
1229 {
1230 wakeup_init(&sd_wakeup);
1231 mutex_init(&sd_mtx);
1232 queue_init(&sd_queue, true);
1233 create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
1234 sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE)
1235 IF_COP(, CPU));
1236
1237 inited = true;
1238 }
1239
1240 return sd_init_device();
1241 }
1242
1243 static inline bool card_detect_target(void)
1244 {
1245 return (jz_sd_chkcard() == 1);
1246 }
1247
1248 tCardInfo* card_get_info_target(int card_no)
1249 {
1250 (void)card_no;
1251 return &card;
1252 }
1253
1254 static inline void sd_start_transfer(void)
1255 {
1256 mutex_lock(&sd_mtx);
1257 __cpm_start_msc();
1258 led(true);
1259 }
1260
1261 static inline void sd_stop_transfer(void)
1262 {
1263 led(false);
1264 __cpm_stop_msc();
1265 mutex_unlock(&sd_mtx);
1266 }
1267
1268 int sd_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf)
1269 {
1270 #ifdef HAVE_MULTIVOLUME
1271 (void)drive;
1272 #endif
1273 sd_start_transfer();
1274
1275 struct sd_request request;
1276 struct sd_response_r1 r1;
1277 int retval = -1;
1278
1279 if (!card_detect_target() || count == 0 || start > card.numblocks)
1280 goto err;
1281
1282 if(card.initialized == 0 && !sd_init_device())
1283 goto err;
1284
1285 sd_simple_cmd(&request, SD_SEND_STATUS, card.rca, RESPONSE_R1);
1286 retval = sd_unpack_r1(&request, &r1);
1287 if (retval && (retval != SD_ERROR_STATE_MISMATCH))
1288 goto err;
1289
1290 sd_simple_cmd(&request, SD_SET_BLOCKLEN, SD_BLOCK_SIZE, RESPONSE_R1);
1291 if ((retval = sd_unpack_r1(&request, &r1)))
1292 goto err;
1293
1294 if (sd2_0)
1295 {
1296 sd_send_cmd(&request, SD_READ_MULTIPLE_BLOCK, start,
1297 count, SD_BLOCK_SIZE, RESPONSE_R1, buf);
1298 if ((retval = sd_unpack_r1(&request, &r1)))
1299 goto err;
1300 }
1301 else
1302 {
1303 sd_send_cmd(&request, SD_READ_MULTIPLE_BLOCK,
1304 start * SD_BLOCK_SIZE, count,
1305 SD_BLOCK_SIZE, RESPONSE_R1, buf);
1306 if ((retval = sd_unpack_r1(&request, &r1)))
1307 goto err;
1308 }
1309
1310 last_disk_activity = current_tick;
1311
1312 sd_simple_cmd(&request, SD_STOP_TRANSMISSION, 0, RESPONSE_R1B);
1313 if ((retval = sd_unpack_r1(&request, &r1)))
1314 goto err;
1315
1316 err:
1317 sd_stop_transfer();
1318
1319 return retval;
1320 }
1321
1322 int sd_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const void* buf)
1323 {
1324 #ifdef HAVE_MULTIVOLUME
1325 (void)drive;
1326 #endif
1327 sd_start_transfer();
1328
1329 struct sd_request request;
1330 struct sd_response_r1 r1;
1331 int retval = -1;
1332
1333 if (!card_detect_target() || count == 0 || start > card.numblocks)
1334 goto err;
1335
1336 if(card.initialized == 0 && !sd_init_device())
1337 goto err;
1338
1339 sd_simple_cmd(&request, SD_SEND_STATUS, card.rca, RESPONSE_R1);
1340 retval = sd_unpack_r1(&request, &r1);
1341 if (retval && (retval != SD_ERROR_STATE_MISMATCH))
1342 goto err;
1343
1344 sd_simple_cmd(&request, SD_SET_BLOCKLEN, SD_BLOCK_SIZE, RESPONSE_R1);
1345 if ((retval = sd_unpack_r1(&request, &r1)))
1346 goto err;
1347
1348 if (sd2_0)
1349 {
1350 sd_send_cmd(&request, SD_WRITE_MULTIPLE_BLOCK, start,
1351 count, SD_BLOCK_SIZE, RESPONSE_R1,
1352 (void*)buf);
1353 if ((retval = sd_unpack_r1(&request, &r1)))
1354 goto err;
1355 }
1356 else
1357 {
1358 sd_send_cmd(&request, SD_WRITE_MULTIPLE_BLOCK,
1359 start * SD_BLOCK_SIZE, count,
1360 SD_BLOCK_SIZE, RESPONSE_R1, (void*)buf);
1361 if ((retval = sd_unpack_r1(&request, &r1)))
1362 goto err;
1363 }
1364
1365 last_disk_activity = current_tick;
1366
1367 sd_simple_cmd(&request, SD_STOP_TRANSMISSION, 0, RESPONSE_R1B);
1368 if ((retval = sd_unpack_r1(&request, &r1)))
1369 goto err;
1370
1371 err:
1372 sd_stop_transfer();
1373
1374 return retval;
1375 }
1376
1377 long sd_last_disk_activity(void)
1378 {
1379 return last_disk_activity;
1380 }
1381
1382 int sd_spinup_time(void)
1383 {
1384 return 0;
1385 }
1386
1387 void sd_enable(bool on)
1388 {
1389 (void)on;
1390 }
1391
1392 void sd_sleepnow(void)
1393 {
1394 }
1395
1396 bool sd_disk_is_active(void)
1397 {
1398 return false;
1399 }
1400
1401 int sd_soft_reset(void)
1402 {
1403 return 0;
1404 }
1405
1406 #ifdef HAVE_HOTSWAP
1407 bool sd_removable(IF_MV_NONVOID(int drive))
1408 {
1409 #ifdef HAVE_MULTIVOLUME
1410 (void)drive;
1411 #endif
1412 return true;
1413 }
1414
1415 static int sd_oneshot_callback(struct timeout *tmo)
1416 {
1417 (void)tmo;
1418 int state = card_detect_target();
1419
1420 /* This is called only if the state was stable for 300ms - check state
1421 * and post appropriate event. */
1422 if (state)
1423 queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
1424 else
1425 queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
1426
1427 sd_gpio_setup_irq(state);
1428
1429 return 0;
1430 }
1431
1432 /* called on insertion/removal interrupt */
1433 void MMC_CD_IRQ(void)
1434 {
1435 static struct timeout sd_oneshot;
1436 timeout_register(&sd_oneshot, sd_oneshot_callback, (3*HZ/10), 0);
1437 }
1438 #endif
1439
1440 bool sd_present(IF_MV_NONVOID(int drive))
1441 {
1442 #ifdef HAVE_MULTIDRIVE
1443 (void)drive;
1444 #endif
1445 return card_detect_target();
1446 }
1447
1448 #ifdef CONFIG_STORAGE_MULTI
1449 int sd_num_drives(int first_drive)
1450 {
1451 sd_drive_nr = first_drive;
1452 return 1;
1453 }
1454 #endif
1455
1456 static void sd_thread(void)
1457 {
1458 struct queue_event ev;
1459 bool idle_notified = false;
1460
1461 while (1)
1462 {
1463 queue_wait_w_tmo(&sd_queue, &ev, HZ);
1464
1465 switch (ev.id)
1466 {
1467 #ifdef HAVE_HOTSWAP
1468 case SYS_HOTSWAP_INSERTED:
1469 case SYS_HOTSWAP_EXTRACTED:
1470 fat_lock(); /* lock-out FAT activity first -
1471 prevent deadlocking via disk_mount that
1472 would cause a reverse-order attempt with
1473 another thread */
1474 mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
1475 into driver that bypass the fat cache */
1476
1477 /* We now have exclusive control of fat cache and ata */
1478
1479 disk_unmount(sd_drive_nr); /* release "by force", ensure file
1480 descriptors aren't leaked and any busy
1481 ones are invalid if mounting */
1482
1483 /* Force card init for new card, re-init for re-inserted one or
1484 * clear if the last attempt to init failed with an error. */
1485 card.initialized = 0;
1486
1487 if(ev.id == SYS_HOTSWAP_INSERTED)
1488 disk_mount(sd_drive_nr);
1489
1490 queue_broadcast(SYS_FS_CHANGED, 0);
1491
1492 /* Access is now safe */
1493 mutex_unlock(&sd_mtx);
1494 fat_unlock();
1495 break;
1496 #endif
1497 case SYS_TIMEOUT:
1498 if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
1499 idle_notified = false;
1500 else
1501 {
1502 if (!idle_notified)
1503 {
1504 call_storage_idle_notifys(false);
1505 idle_notified = true;
1506 }
1507 }
1508 break;
1509 case SYS_USB_CONNECTED:
1510 usb_acknowledge(SYS_USB_CONNECTED_ACK);
1511 /* Wait until the USB cable is extracted again */
1512 usb_wait_for_disconnect(&sd_queue);
1513 break;
1514 case SYS_USB_DISCONNECTED:
1515 usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
1516 break;
1517 }
1518 }
1519 }
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