firmware/target/arm/usb-s3c6400x.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2009 by Michael Sparmann
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "config.h"
  23 #include "usb.h"
  24 #include "usb-target.h"
  25 #include "usb_drv.h"
  26
  27 #include "cpu.h"
  28 #include "system.h"
  29 #include "kernel.h"
  30 #include "panic.h"
  31
  32 #include "usb-s3c6400x.h"
  33
  34 #ifdef HAVE_USBSTACK
  35 #include "usb_ch9.h"
  36 #include "usb_core.h"
  37 #include <inttypes.h>
  38 #include "power.h"
  39
  40 struct ep_type
  41 {
  42     bool active;
  43     bool busy;
  44     bool done;
  45     int rc;
  46     int size;
  47     struct wakeup complete;
  48 } ;
  49
  50 static struct ep_type endpoints[USB_NUM_ENDPOINTS];
  51 static struct usb_ctrlrequest ctrlreq USB_DEVBSS_ATTR;
  52
  53 int usb_drv_port_speed(void)
  54 {
  55     return (DSTS & 2) == 0 ? 1 : 0;
  56 }
  57
  58 static void reset_endpoints(int reinit)
  59 {
  60     unsigned int i;
  61     for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
  62     {
  63         if (reinit) endpoints[i].active = false;
  64         endpoints[i].busy = false;
  65         endpoints[i].rc = -1;
  66         endpoints[i].done = true;
  67         wakeup_signal(&endpoints[i].complete);
  68     }
  69     DIEPCTL0 = 0x8800;  /* EP0 IN ACTIVE NEXT=1 */
  70     DOEPCTL0 = 0x8000;  /* EP0 OUT ACTIVE */
  71     DOEPTSIZ0 = 0x20080040;  /* EP0 OUT Transfer Size:
  72                                 64 Bytes, 1 Packet, 1 Setup Packet */
  73     DOEPDMA0 = &ctrlreq;
  74     DOEPCTL0 |= 0x84000000;  /* EP0 OUT ENABLE CLEARNAK */
  75     if (reinit)
  76     {
  77         /* The size is getting set to zero, because we don't know
  78            whether we are Full Speed or High Speed at this stage */
  79         /* EP1 IN INACTIVE DATA0 SIZE=0 NEXT=3 */
  80         DIEPCTL1 = 0x10001800;
  81         /* EP2 OUT INACTIVE DATA0 SIZE=0 */
  82         DOEPCTL2 = 0x10000000;
  83         /* EP3 IN INACTIVE DATA0 SIZE=0 NEXT=0 */
  84         DIEPCTL3 = 0x10000000;
  85         /* EP4 OUT INACTIVE DATA0 SIZE=0 */
  86         DOEPCTL4 = 0x10000000;
  87     }
  88     else
  89     {
  90         /* INACTIVE DATA0 */
  91         DIEPCTL1 = (DIEPCTL1 & ~0x00008000) | 0x10000000;
  92         DOEPCTL2 = (DOEPCTL2 & ~0x00008000) | 0x10000000;
  93         DIEPCTL3 = (DIEPCTL3 & ~0x00008000) | 0x10000000;
  94         DOEPCTL4 = (DOEPCTL4 & ~0x00008000) | 0x10000000;
  95     }
  96     DAINTMSK = 0xFFFFFFFF;  /* Enable interrupts on all EPs */
  97 }
  98
  99 int usb_drv_request_endpoint(int type, int dir)
 100 {
 101     size_t ep;
 102     int ret = -1;
 103
 104     if (dir == USB_DIR_IN) ep = 1;
 105     else ep = 2;
 106
 107     while (ep < USB_NUM_ENDPOINTS)
 108     {
 109         if (!endpoints[ep].active)
 110         {
 111             endpoints[ep].active = true;
 112             ret = ep | dir;
 113             uint32_t newbits = (type << 18) | 0x10000000;
 114             if (dir) DIEPCTL(ep) = (DIEPCTL(ep) & ~0x000C0000) | newbits;
 115             else DOEPCTL(ep) = (DOEPCTL(ep) & ~0x000C0000) | newbits;
 116             break;
 117         }
 118         ep += 2;
 119     }
 120
 121     return ret;
 122 }
 123
 124 void usb_drv_release_endpoint(int ep)
 125 {
 126     ep = ep & 0x7f;
 127
 128     if (ep < 1 || ep > USB_NUM_ENDPOINTS) return;
 129
 130     endpoints[ep].active = false;
 131 }
 132
 133 static void usb_reset(void)
 134 {
 135     volatile int i;
 136
 137     DCTL = 0x802;  /* Soft Disconnect */
 138
 139     OPHYPWR = 0;  /* PHY: Power up */
 140     OPHYUNK1 = 1;
 141     OPHYUNK2 = 0xE3F;
 142     OPHYCLK = SYNOPSYSOTG_CLOCK;
 143     ORSTCON = 1;  /* PHY: Assert Software Reset */
 144     for (i = 0; i < 50; i++);
 145     ORSTCON = 0;  /* PHY: Deassert Software Reset */
 146     OPHYUNK3 = 0x600;
 147
 148     GRSTCTL = 1;  /* OTG: Assert Software Reset */
 149     while (GRSTCTL & 1);  /* Wait for OTG to ack reset */
 150     while (!(GRSTCTL & 0x80000000));  /* Wait for OTG AHB master idle */
 151
 152     GRXFSIZ = 0x00000200;  /* RX FIFO: 512 bytes */
 153     GNPTXFSIZ = 0x02000200;  /* Non-periodic TX FIFO: 512 bytes */
 154     GAHBCFG = SYNOPSYSOTG_AHBCFG;
 155     GUSBCFG = 0x1408;  /* OTG: 16bit PHY and some reserved bits */
 156
 157     DCFG = 4;  /* Address 0 */
 158     DCTL = 0x800;  /* Soft Reconnect */
 159     DIEPMSK = 0x0D;  /* IN EP interrupt mask */
 160     DOEPMSK = 0x0D;  /* IN EP interrupt mask */
 161     DAINTMSK = 0xFFFFFFFF;  /* Enable interrupts on all endpoints */
 162     GINTMSK = 0xC3000;  /* Interrupt mask: IN event, OUT event, bus reset */
 163
 164     reset_endpoints(1);
 165 }
 166
 167 /* IRQ handler */
 168 void INT_USB_FUNC(void)
 169 {
 170     int i;
 171     uint32_t ints = GINTSTS;
 172     uint32_t epints;
 173     if (ints & 0x1000)  /* bus reset */
 174     {
 175         DCFG = 4;  /* Address 0 */
 176         reset_endpoints(1);
 177         usb_core_bus_reset();
 178     }
 179
 180     if (ints & 0x2000)  /* enumeration done, we now know the speed */
 181     {
 182         /* Set up the maximum packet sizes accordingly */
 183         uint32_t maxpacket = usb_drv_port_speed() ? 512 : 64;
 184         DIEPCTL1 = (DIEPCTL1 & ~0x000003FF) | maxpacket;
 185         DOEPCTL2 = (DOEPCTL2 & ~0x000003FF) | maxpacket;
 186         DIEPCTL3 = (DIEPCTL3 & ~0x000003FF) | maxpacket;
 187         DOEPCTL4 = (DOEPCTL4 & ~0x000003FF) | maxpacket;
 188     }
 189
 190     if (ints & 0x40000)  /* IN EP event */
 191         for (i = 0; i < 4; i += i + 1)  // 0, 1, 3
 192             if ((epints = DIEPINT(i)))
 193             {
 194                 if (epints & 1)  /* Transfer completed */
 195                 {
 196                     invalidate_dcache();
 197                     int bytes = endpoints[i].size - (DIEPTSIZ(i) & 0x3FFFF);
 198                     if (endpoints[i].busy)
 199                     {
 200                         endpoints[i].busy = false;
 201                         endpoints[i].rc = 0;
 202                         endpoints[i].done = true;
 203                         usb_core_transfer_complete(i, USB_DIR_IN, 0, bytes);
 204                         wakeup_signal(&endpoints[i].complete);
 205                     }
 206                 }
 207                 if (epints & 4)  /* AHB error */
 208                     panicf("USB: AHB error on IN EP%d", i);
 209                 if (epints & 8)  /* Timeout */
 210                 {
 211                     if (endpoints[i].busy)
 212                     {
 213                         endpoints[i].busy = false;
 214                         endpoints[i].rc = 1;
 215                         endpoints[i].done = true;
 216                         wakeup_signal(&endpoints[i].complete);
 217                     }
 218                 }
 219                 DIEPINT(i) = epints;
 220             }
 221
 222     if (ints & 0x80000)  /* OUT EP event */
 223         for (i = 0; i < USB_NUM_ENDPOINTS; i += 2)
 224             if ((epints = DOEPINT(i)))
 225             {
 226                 if (epints & 1)  /* Transfer completed */
 227                 {
 228                     invalidate_dcache();
 229                     int bytes = endpoints[i].size - (DOEPTSIZ(i) & 0x3FFFF);
 230                     if (endpoints[i].busy)
 231                     {
 232                         endpoints[i].busy = false;
 233                         endpoints[i].rc = 0;
 234                         endpoints[i].done = true;
 235                         usb_core_transfer_complete(i, USB_DIR_OUT, 0, bytes);
 236                         wakeup_signal(&endpoints[i].complete);
 237                     }
 238                 }
 239                 if (epints & 4)  /* AHB error */
 240                     panicf("USB: AHB error on OUT EP%d", i);
 241                 if (epints & 8)  /* SETUP phase done */
 242                 {
 243                     invalidate_dcache();
 244                     if (i == 0)
 245                     {
 246                         if (ctrlreq.bRequest == 5)
 247                         {
 248                             /* Already set the new address here,
 249                                before passing the packet to the core.
 250                                See below (usb_drv_set_address) for details. */
 251                             DCFG = (DCFG & ~0x7F0) | (ctrlreq.wValue << 4);
 252                         }
 253                         usb_core_control_request(&ctrlreq);
 254                     }
 255                     else panicf("USB: SETUP done on OUT EP%d!?", i);
 256                 }
 257                 /* Make sure EP0 OUT is set up to accept the next request */
 258                 if (!i)
 259                 {
 260                     DOEPTSIZ0 = 0x20080040;
 261                     DOEPDMA0 = &ctrlreq;
 262                     DOEPCTL0 |= 0x84000000;
 263                 }
 264                 DOEPINT(i) = epints;
 265             }
 266
 267     GINTSTS = ints;
 268 }
 269
 270 void usb_drv_set_address(int address)
 271 {
 272     (void)address;
 273     /* Ignored intentionally, because the controller requires us to set the
 274        new address before sending the response for some reason. So we'll
 275        already set it when the control request arrives, before passing that
 276        into the USB core, which will then call this dummy function. */
 277 }
 278
 279 static void ep_send(int ep, const void *ptr, int length)
 280 {
 281     endpoints[ep].busy = true;
 282     endpoints[ep].size = length;
 283     DIEPCTL(ep) |= 0x8000;  /* EPx OUT ACTIVE */
 284     int blocksize = usb_drv_port_speed() ? 512 : 64;
 285     int packets = (length + blocksize - 1) / blocksize;
 286     if (!length)
 287     {
 288         DIEPTSIZ(ep) = 1 << 19;  /* one empty packet */
 289         DIEPDMA(ep) = NULL;
 290     }
 291     else
 292     {
 293         DIEPTSIZ(ep) = length | (packets << 19);
 294         DIEPDMA(ep) = ptr;
 295     }
 296     clean_dcache();
 297     DIEPCTL(ep) |= 0x84000000;  /* EPx OUT ENABLE CLEARNAK */
 298 }
 299
 300 static void ep_recv(int ep, void *ptr, int length)
 301 {
 302     endpoints[ep].busy = true;
 303     endpoints[ep].size = length;
 304     DOEPCTL(ep) &= ~0x20000;  /* EPx UNSTALL */
 305     DOEPCTL(ep) |= 0x8000;  /* EPx OUT ACTIVE */
 306     int blocksize = usb_drv_port_speed() ? 512 : 64;
 307     int packets = (length + blocksize - 1) / blocksize;
 308     if (!length)
 309     {
 310         DOEPTSIZ(ep) = 1 << 19;  /* one empty packet */
 311         DOEPDMA(ep) = NULL;
 312     }
 313     else
 314     {
 315         DOEPTSIZ(ep) = length | (packets << 19);
 316         DOEPDMA(ep) = ptr;
 317     }
 318     clean_dcache();
 319     DOEPCTL(ep) |= 0x84000000;  /* EPx OUT ENABLE CLEARNAK */
 320 }
 321
 322 int usb_drv_send(int endpoint, void *ptr, int length)
 323 {
 324     endpoint &= 0x7f;
 325     endpoints[endpoint].done = false;
 326     ep_send(endpoint, ptr, length);
 327     while (!endpoints[endpoint].done && endpoints[endpoint].busy)
 328         wakeup_wait(&endpoints[endpoint].complete, TIMEOUT_BLOCK);
 329     return endpoints[endpoint].rc;
 330 }
 331
 332 int usb_drv_send_nonblocking(int endpoint, void *ptr, int length)
 333 {
 334     ep_send(endpoint & 0x7f, ptr, length);
 335     return 0;
 336 }
 337
 338 int usb_drv_recv(int endpoint, void* ptr, int length)
 339 {
 340     ep_recv(endpoint & 0x7f, ptr, length);
 341     return 0;
 342 }
 343
 344 void usb_drv_cancel_all_transfers(void)
 345 {
 346     int flags = disable_irq_save();
 347     reset_endpoints(0);
 348     restore_irq(flags);
 349 }
 350
 351 void usb_drv_set_test_mode(int mode)
 352 {
 353     (void)mode;
 354 }
 355
 356 bool usb_drv_stalled(int endpoint, bool in)
 357 {
 358     if (in) return DIEPCTL(endpoint) & 0x00200000 ? true : false;
 359     else return DOEPCTL(endpoint) & 0x00200000 ? true : false;
 360 }
 361
 362 void usb_drv_stall(int endpoint, bool stall, bool in)
 363 {
 364     if (in)
 365     {
 366         if (stall) DIEPCTL(endpoint) |= 0x00200000;
 367         else DIEPCTL(endpoint) &= ~0x00200000;
 368     }
 369     else
 370     {
 371         if (stall) DOEPCTL(endpoint) |= 0x00200000;
 372         else DOEPCTL(endpoint) &= ~0x00200000;
 373     }
 374 }
 375
 376 void usb_drv_init(void)
 377 {
 378     /* Enable USB clock */
 379 #if CONFIG_CPU==S5L8701
 380     PWRCON &= ~0x4000;
 381     PWRCONEXT &= ~0x800;
 382     INTMSK |= INTMSK_USB_OTG;
 383 #elif CONFIG_CPU==S5L8702
 384     PWRCON(0) &= ~0x4;
 385     PWRCON(1) &= ~0x8;
 386     VIC0INTENABLE |= 1 << 19;
 387 #endif
 388     PCGCCTL = 0;
 389
 390     /* reset the beast */
 391     usb_reset();
 392 }
 393
 394 void usb_drv_exit(void)
 395 {
 396     DCTL = 0x802;  /* Soft Disconnect */
 397
 398     ORSTCON = 1;  /* Put the PHY into reset (needed to get current down) */
 399     PCGCCTL = 1;  /* Shut down PHY clock */
 400     OPHYPWR = 0xF;  /* PHY: Power down */
 401
 402 #if CONFIG_CPU==S5L8701
 403     PWRCON |= 0x4000;
 404     PWRCONEXT |= 0x800;
 405 #elif CONFIG_CPU==S5L8702
 406     PWRCON(0) |= 0x4;
 407     PWRCON(1) |= 0x8;
 408 #endif
 409 }
 410
 411 void usb_init_device(void)
 412 {
 413     unsigned int i;
 414     for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
 415         wakeup_init(&endpoints[i].complete);
 416
 417     /* Power up the core clocks to allow writing
 418        to some registers needed to power it down */
 419     PCGCCTL = 0;
 420 #if CONFIG_CPU==S5L8701
 421     PWRCON &= ~0x4000;
 422     PWRCONEXT &= ~0x800;
 423     INTMSK |= INTMSK_USB_OTG;
 424 #elif CONFIG_CPU==S5L8702
 425     PWRCON(0) &= ~0x4;
 426     PWRCON(1) &= ~0x8;
 427     VIC0INTENABLE |= 1 << 19;
 428 #endif
 429
 430     usb_drv_exit();
 431 }
 432
 433 void usb_enable(bool on)
 434 {
 435     if (on) usb_core_init();
 436     else usb_core_exit();
 437 }
 438
 439 void usb_attach(void)
 440 {
 441     usb_enable(true);
 442 }
 443
 444 int usb_detect(void)
 445 {
 446     if (charger_inserted())
 447         return USB_INSERTED;
 448     return USB_EXTRACTED;
 449 }
 450
 451 #else
 452 void usb_init_device(void)
 453 {
 454     DCTL = 0x802;  /* Soft Disconnect */
 455
 456     ORSTCON = 1;  /* Put the PHY into reset (needed to get current down) */
 457     PCGCCTL = 1;  /* Shut down PHY clock */
 458     OPHYPWR = 0xF;  /* PHY: Power down */
 459
 460 #if CONFIG_CPU==S5L8701
 461     PWRCON |= 0x4000;
 462     PWRCONEXT |= 0x800;
 463 #elif CONFIG_CPU==S5L8702
 464     PWRCON(0) |= 0x4;
 465     PWRCON(1) |= 0x8;
 466 #endif
 467 }
 468
 469 void usb_enable(bool on)
 470 {
 471     (void)on;
 472 }
 473
 474 /* Always return false for now */
 475 int usb_detect(void)
 476 {
 477     return USB_EXTRACTED;
 478 }
 479 #endif