1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (c) 2008 by Michael Sevakis
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
23 #include "gpio-imx31.h"
25 #include "mc13783-target.h"
29 extern const struct mc13783_event mc13783_events
[MC13783_NUM_EVENTS
];
30 extern struct spi_node mc13783_spi
;
32 /* PMIC event service data */
33 static int mc13783_thread_stack
[DEFAULT_STACK_SIZE
/sizeof(int)];
34 static const char *mc13783_thread_name
= "pmic";
35 static struct wakeup mc13783_svc_wake
;
37 /* Synchronous thread communication objects */
38 static struct mutex mc13783_spi_mutex
;
39 static struct wakeup mc13783_spi_wake
;
41 /* Tracking for which interrupts are enabled */
42 static uint32_t pmic_int_enabled
[2] =
43 { 0x00000000, 0x00000000 };
45 static const unsigned char pmic_intm_regs
[2] =
46 { MC13783_INTERRUPT_MASK0
, MC13783_INTERRUPT_MASK1
};
48 static const unsigned char pmic_ints_regs
[2] =
49 { MC13783_INTERRUPT_STATUS0
, MC13783_INTERRUPT_STATUS1
};
51 static volatile unsigned int mc13783_thread_id
= 0;
53 static void mc13783_xfer_complete_cb(struct spi_transfer_desc
*trans
);
55 /* Transfer descriptor for synchronous reads and writes */
56 static struct spi_transfer_desc mc13783_transfer
=
62 .callback
= mc13783_xfer_complete_cb
,
66 /* Called when a transfer is finished and data is ready/written */
67 static void mc13783_xfer_complete_cb(struct spi_transfer_desc
*xfer
)
72 wakeup_signal(&mc13783_spi_wake
);
75 static inline bool wait_for_transfer_complete(void)
77 return wakeup_wait(&mc13783_spi_wake
, HZ
*2) == OBJ_WAIT_SUCCEEDED
&&
78 mc13783_transfer
.count
== 0;
81 static void mc13783_interrupt_thread(void)
85 /* Enable mc13783 GPIO event */
86 gpio_enable_event(MC13783_EVENT_ID
);
90 const struct mc13783_event
*event
, *event_last
;
92 wakeup_wait(&mc13783_svc_wake
, TIMEOUT_BLOCK
);
94 if (mc13783_thread_id
== 0)
97 mc13783_read_regs(pmic_ints_regs
, pending
, 2);
99 /* Only clear interrupts being dispatched */
100 pending
[0] &= pmic_int_enabled
[0];
101 pending
[1] &= pmic_int_enabled
[1];
103 mc13783_write_regs(pmic_ints_regs
, pending
, 2);
105 /* Whatever is going to be serviced in this loop has been
106 * acknowledged. Reenable interrupt and if anything was still
107 * pending or became pending again, another signal will be
109 bitset32(&MC13783_GPIO_IMR
, 1ul << MC13783_GPIO_LINE
);
111 event
= mc13783_events
;
112 event_last
= event
+ MC13783_NUM_EVENTS
;
114 /* .count is surely expected to be > 0 */
117 enum mc13783_event_sets set
= event
->set
;
118 uint32_t pnd
= pending
[set
];
119 uint32_t mask
= event
->mask
;
128 if ((pending
[0] | pending
[1]) == 0)
129 break; /* Terminate early if nothing more to service */
131 while (++event
< event_last
);
134 gpio_disable_event(MC13783_EVENT_ID
);
137 /* GPIO interrupt handler for mc13783 */
138 void mc13783_event(void)
140 /* Mask the interrupt (unmasked when PMIC thread services it). */
141 bitclr32(&MC13783_GPIO_IMR
, 1ul << MC13783_GPIO_LINE
);
142 MC13783_GPIO_ISR
= (1ul << MC13783_GPIO_LINE
);
143 wakeup_signal(&mc13783_svc_wake
);
146 void INIT_ATTR
mc13783_init(void)
148 /* Serial interface must have been initialized first! */
149 wakeup_init(&mc13783_svc_wake
);
150 mutex_init(&mc13783_spi_mutex
);
152 wakeup_init(&mc13783_spi_wake
);
154 /* Enable the PMIC SPI module */
155 spi_enable_module(&mc13783_spi
);
157 /* Mask any PMIC interrupts for now - modules will enable them as
159 mc13783_write(MC13783_INTERRUPT_MASK0
, 0xffffff);
160 mc13783_write(MC13783_INTERRUPT_MASK1
, 0xffffff);
162 MC13783_GPIO_ISR
= (1ul << MC13783_GPIO_LINE
);
165 create_thread(mc13783_interrupt_thread
,
166 mc13783_thread_stack
, sizeof(mc13783_thread_stack
), 0,
167 mc13783_thread_name
IF_PRIO(, PRIORITY_REALTIME
) IF_COP(, CPU
));
170 void mc13783_close(void)
172 unsigned int thread_id
= mc13783_thread_id
;
177 mc13783_thread_id
= 0;
178 wakeup_signal(&mc13783_svc_wake
);
179 thread_wait(thread_id
);
180 spi_disable_module(&mc13783_spi
);
183 bool mc13783_enable_event(enum mc13783_event_ids id
)
185 const struct mc13783_event
* const event
= &mc13783_events
[id
];
186 int set
= event
->set
;
187 uint32_t mask
= event
->mask
;
189 mutex_lock(&mc13783_spi_mutex
);
191 pmic_int_enabled
[set
] |= mask
;
192 mc13783_clear(pmic_intm_regs
[set
], mask
);
194 mutex_unlock(&mc13783_spi_mutex
);
199 void mc13783_disable_event(enum mc13783_event_ids id
)
201 const struct mc13783_event
* const event
= &mc13783_events
[id
];
202 int set
= event
->set
;
203 uint32_t mask
= event
->mask
;
205 mutex_lock(&mc13783_spi_mutex
);
207 pmic_int_enabled
[set
] &= ~mask
;
208 mc13783_set(pmic_intm_regs
[set
], mask
);
210 mutex_unlock(&mc13783_spi_mutex
);
213 uint32_t mc13783_set(unsigned address
, uint32_t bits
)
217 mutex_lock(&mc13783_spi_mutex
);
219 data
= mc13783_read(address
);
221 if (data
!= MC13783_DATA_ERROR
)
222 mc13783_write(address
, data
| bits
);
224 mutex_unlock(&mc13783_spi_mutex
);
229 uint32_t mc13783_clear(unsigned address
, uint32_t bits
)
233 mutex_lock(&mc13783_spi_mutex
);
235 data
= mc13783_read(address
);
237 if (data
!= MC13783_DATA_ERROR
)
238 mc13783_write(address
, data
& ~bits
);
240 mutex_unlock(&mc13783_spi_mutex
);
245 int mc13783_write(unsigned address
, uint32_t data
)
250 if (address
>= MC13783_NUM_REGS
)
253 packet
= (1 << 31) | (address
<< 25) | (data
& 0xffffff);
255 mutex_lock(&mc13783_spi_mutex
);
257 mc13783_transfer
.txbuf
= &packet
;
258 mc13783_transfer
.rxbuf
= NULL
;
259 mc13783_transfer
.count
= 1;
263 if (spi_transfer(&mc13783_transfer
) && wait_for_transfer_complete())
264 i
= 1 - mc13783_transfer
.count
;
266 mutex_unlock(&mc13783_spi_mutex
);
271 uint32_t mc13783_write_masked(unsigned address
, uint32_t data
, uint32_t mask
)
275 mutex_lock(&mc13783_spi_mutex
);
277 old
= mc13783_read(address
);
279 if (old
!= MC13783_DATA_ERROR
)
281 data
= (old
& ~mask
) | (data
& mask
);
283 if (mc13783_write(address
, data
) != 1)
284 old
= MC13783_DATA_ERROR
;
287 mutex_unlock(&mc13783_spi_mutex
);
292 uint32_t mc13783_read(unsigned address
)
296 if (address
>= MC13783_NUM_REGS
)
297 return MC13783_DATA_ERROR
;
299 packet
= address
<< 25;
301 mutex_lock(&mc13783_spi_mutex
);
303 mc13783_transfer
.txbuf
= &packet
;
304 mc13783_transfer
.rxbuf
= &packet
;
305 mc13783_transfer
.count
= 1;
307 if (!spi_transfer(&mc13783_transfer
) || !wait_for_transfer_complete())
308 packet
= MC13783_DATA_ERROR
;
310 mutex_unlock(&mc13783_spi_mutex
);
315 int mc13783_read_regs(const unsigned char *regs
, uint32_t *buffer
,
320 for (i
= 0; i
< count
; i
++)
322 unsigned reg
= regs
[i
];
324 if (reg
>= MC13783_NUM_REGS
)
327 buffer
[i
] = reg
<< 25;
330 mutex_lock(&mc13783_spi_mutex
);
332 mc13783_transfer
.txbuf
= buffer
;
333 mc13783_transfer
.rxbuf
= buffer
;
334 mc13783_transfer
.count
= count
;
338 if (spi_transfer(&mc13783_transfer
) && wait_for_transfer_complete())
339 i
= count
- mc13783_transfer
.count
;
341 mutex_unlock(&mc13783_spi_mutex
);
346 int mc13783_write_regs(const unsigned char *regs
, uint32_t *buffer
,
351 for (i
= 0; i
< count
; i
++)
353 unsigned reg
= regs
[i
];
355 if (reg
>= MC13783_NUM_REGS
)
358 buffer
[i
] = (1 << 31) | (reg
<< 25) | (buffer
[i
] & 0xffffff);
361 mutex_lock(&mc13783_spi_mutex
);
363 mc13783_transfer
.txbuf
= buffer
;
364 mc13783_transfer
.rxbuf
= NULL
;
365 mc13783_transfer
.count
= count
;
369 if (spi_transfer(&mc13783_transfer
) && wait_for_transfer_complete())
370 i
= count
- mc13783_transfer
.count
;
372 mutex_unlock(&mc13783_spi_mutex
);
377 #if 0 /* Not needed right now */
378 bool mc13783_read_async(struct spi_transfer_desc
*xfer
,
379 const unsigned char *regs
, uint32_t *buffer
,
380 int count
, spi_transfer_cb_fn_type callback
)
384 for (i
= 0; i
< count
; i
++)
386 unsigned reg
= regs
[i
];
388 if (reg
>= MC13783_NUM_REGS
)
391 buffer
[i
] = reg
<< 25;
394 xfer
->node
= &mc13783_spi
;
395 xfer
->txbuf
= buffer
;
396 xfer
->rxbuf
= buffer
;
398 xfer
->callback
= callback
;
401 return spi_transfer(xfer
);
405 bool mc13783_write_async(struct spi_transfer_desc
*xfer
,
406 const unsigned char *regs
, uint32_t *buffer
,
407 int count
, spi_transfer_cb_fn_type callback
)
411 for (i
= 0; i
< count
; i
++)
413 unsigned reg
= regs
[i
];
415 if (reg
>= MC13783_NUM_REGS
)
418 buffer
[i
] = (1 << 31) | (reg
<< 25) | (buffer
[i
] & 0xffffff);
421 xfer
->node
= &mc13783_spi
;
422 xfer
->txbuf
= buffer
;
425 xfer
->callback
= callback
;
428 return spi_transfer(xfer
);