Minor clean up in playback.c
[kugel-rb.git] / firmware / export / mipsregs.h
blob197f8eb9926cf35495032894a44f434d6e3c3e0c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2003 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
17 * Coprocessor 0 register names
19 #define CP0_INDEX $0
20 #define CP0_RANDOM $1
21 #define CP0_ENTRYLO0 $2
22 #define CP0_ENTRYLO1 $3
23 #define CP0_CONF $3
24 #define CP0_CONTEXT $4
25 #define CP0_PAGEMASK $5
26 #define CP0_WIRED $6
27 #define CP0_INFO $7
28 #define CP0_BADVADDR $8
29 #define CP0_COUNT $9
30 #define CP0_ENTRYHI $10
31 #define CP0_COMPARE $11
32 #define CP0_STATUS $12
33 #define CP0_CAUSE $13
34 #define CP0_EPC $14
35 #define CP0_PRID $15
36 #define CP0_CONFIG $16
37 #define CP0_LLADDR $17
38 #define CP0_WATCHLO $18
39 #define CP0_WATCHHI $19
40 #define CP0_XCONTEXT $20
41 #define CP0_FRAMEMASK $21
42 #define CP0_DIAGNOSTIC $22
43 #define CP0_DEBUG $23
44 #define CP0_DEPC $24
45 #define CP0_PERFORMANCE $25
46 #define CP0_ECC $26
47 #define CP0_CACHEERR $27
48 #define CP0_TAGLO $28
49 #define CP0_TAGHI $29
50 #define CP0_ERROREPC $30
51 #define CP0_DESAVE $31
54 * R4640/R4650 cp0 register names. These registers are listed
55 * here only for completeness; without MMU these CPUs are not useable
56 * by Linux. A future ELKS port might take make Linux run on them
57 * though ...
59 #define CP0_IBASE $0
60 #define CP0_IBOUND $1
61 #define CP0_DBASE $2
62 #define CP0_DBOUND $3
63 #define CP0_CALG $17
64 #define CP0_IWATCH $18
65 #define CP0_DWATCH $19
68 * Coprocessor 0 Set 1 register names
70 #define CP0_S1_DERRADDR0 $26
71 #define CP0_S1_DERRADDR1 $27
72 #define CP0_S1_INTCONTROL $20
75 * TX39 Series
77 #define CP0_TX39_CACHE $7
80 * Coprocessor 1 (FPU) register names
82 #define CP1_REVISION $0
83 #define CP1_STATUS $31
86 * FPU Status Register Values
89 * Status Register Values
92 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
93 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
94 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
95 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
96 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
97 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
98 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
99 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
100 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
101 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
104 * X the exception cause indicator
105 * E the exception enable
106 * S the sticky/flag bit
108 #define FPU_CSR_ALL_X 0x0003f000
109 #define FPU_CSR_UNI_X 0x00020000
110 #define FPU_CSR_INV_X 0x00010000
111 #define FPU_CSR_DIV_X 0x00008000
112 #define FPU_CSR_OVF_X 0x00004000
113 #define FPU_CSR_UDF_X 0x00002000
114 #define FPU_CSR_INE_X 0x00001000
116 #define FPU_CSR_ALL_E 0x00000f80
117 #define FPU_CSR_INV_E 0x00000800
118 #define FPU_CSR_DIV_E 0x00000400
119 #define FPU_CSR_OVF_E 0x00000200
120 #define FPU_CSR_UDF_E 0x00000100
121 #define FPU_CSR_INE_E 0x00000080
123 #define FPU_CSR_ALL_S 0x0000007c
124 #define FPU_CSR_INV_S 0x00000040
125 #define FPU_CSR_DIV_S 0x00000020
126 #define FPU_CSR_OVF_S 0x00000010
127 #define FPU_CSR_UDF_S 0x00000008
128 #define FPU_CSR_INE_S 0x00000004
130 /* rounding mode */
131 #define FPU_CSR_RN 0x0 /* nearest */
132 #define FPU_CSR_RZ 0x1 /* towards zero */
133 #define FPU_CSR_RU 0x2 /* towards +Infinity */
134 #define FPU_CSR_RD 0x3 /* towards -Infinity */
138 * Values for PageMask register
140 #ifdef CONFIG_CPU_VR41XX
142 /* Why doesn't stupidity hurt ... */
144 #define PM_1K 0x00000000
145 #define PM_4K 0x00001800
146 #define PM_16K 0x00007800
147 #define PM_64K 0x0001f800
148 #define PM_256K 0x0007f800
150 #else
152 #define PM_4K 0x00000000
153 #define PM_16K 0x00006000
154 #define PM_64K 0x0001e000
155 #define PM_256K 0x0007e000
156 #define PM_1M 0x001fe000
157 #define PM_4M 0x007fe000
158 #define PM_16M 0x01ffe000
159 #define PM_64M 0x07ffe000
160 #define PM_256M 0x1fffe000
162 #endif
165 * Values used for computation of new tlb entries
167 #define PL_4K 12
168 #define PL_16K 14
169 #define PL_64K 16
170 #define PL_256K 18
171 #define PL_1M 20
172 #define PL_4M 22
173 #define PL_16M 24
174 #define PL_64M 26
175 #define PL_256M 28
178 * R4x00 interrupt enable / cause bits
180 #define IE_SW0 (_ULCAST_(1) << 8)
181 #define IE_SW1 (_ULCAST_(1) << 9)
182 #define IE_IRQ0 (_ULCAST_(1) << 10)
183 #define IE_IRQ1 (_ULCAST_(1) << 11)
184 #define IE_IRQ2 (_ULCAST_(1) << 12)
185 #define IE_IRQ3 (_ULCAST_(1) << 13)
186 #define IE_IRQ4 (_ULCAST_(1) << 14)
187 #define IE_IRQ5 (_ULCAST_(1) << 15)
190 * R4x00 interrupt cause bits
192 #define C_SW0 (_ULCAST_(1) << 8)
193 #define C_SW1 (_ULCAST_(1) << 9)
194 #define C_IRQ0 (_ULCAST_(1) << 10)
195 #define C_IRQ1 (_ULCAST_(1) << 11)
196 #define C_IRQ2 (_ULCAST_(1) << 12)
197 #define C_IRQ3 (_ULCAST_(1) << 13)
198 #define C_IRQ4 (_ULCAST_(1) << 14)
199 #define C_IRQ5 (_ULCAST_(1) << 15)
202 * Bitfields in the R4xx0 cp0 status register
204 #define ST0_IE 0x00000001
205 #define ST0_EXL 0x00000002
206 #define ST0_ERL 0x00000004
207 #define ST0_KSU 0x00000018
208 # define KSU_USER 0x00000010
209 # define KSU_SUPERVISOR 0x00000008
210 # define KSU_KERNEL 0x00000000
211 #define ST0_UX 0x00000020
212 #define ST0_SX 0x00000040
213 #define ST0_KX 0x00000080
214 #define ST0_DE 0x00010000
215 #define ST0_CE 0x00020000
218 * Bitfields in the R[23]000 cp0 status register.
220 #define ST0_IEC 0x00000001
221 #define ST0_KUC 0x00000002
222 #define ST0_IEP 0x00000004
223 #define ST0_KUP 0x00000008
224 #define ST0_IEO 0x00000010
225 #define ST0_KUO 0x00000020
226 /* bits 6 & 7 are reserved on R[23]000 */
227 #define ST0_ISC 0x00010000
228 #define ST0_SWC 0x00020000
229 #define ST0_CM 0x00080000
232 * Bits specific to the R4640/R4650
234 #define ST0_UM (_ULCAST_(1) << 4)
235 #define ST0_IL (_ULCAST_(1) << 23)
236 #define ST0_DL (_ULCAST_(1) << 24)
239 * Bitfields in the TX39 family CP0 Configuration Register 3
241 #define TX39_CONF_ICS_SHIFT 19
242 #define TX39_CONF_ICS_MASK 0x00380000
243 #define TX39_CONF_ICS_1KB 0x00000000
244 #define TX39_CONF_ICS_2KB 0x00080000
245 #define TX39_CONF_ICS_4KB 0x00100000
246 #define TX39_CONF_ICS_8KB 0x00180000
247 #define TX39_CONF_ICS_16KB 0x00200000
249 #define TX39_CONF_DCS_SHIFT 16
250 #define TX39_CONF_DCS_MASK 0x00070000
251 #define TX39_CONF_DCS_1KB 0x00000000
252 #define TX39_CONF_DCS_2KB 0x00010000
253 #define TX39_CONF_DCS_4KB 0x00020000
254 #define TX39_CONF_DCS_8KB 0x00030000
255 #define TX39_CONF_DCS_16KB 0x00040000
257 #define TX39_CONF_CWFON 0x00004000
258 #define TX39_CONF_WBON 0x00002000
259 #define TX39_CONF_RF_SHIFT 10
260 #define TX39_CONF_RF_MASK 0x00000c00
261 #define TX39_CONF_DOZE 0x00000200
262 #define TX39_CONF_HALT 0x00000100
263 #define TX39_CONF_LOCK 0x00000080
264 #define TX39_CONF_ICE 0x00000020
265 #define TX39_CONF_DCE 0x00000010
266 #define TX39_CONF_IRSIZE_SHIFT 2
267 #define TX39_CONF_IRSIZE_MASK 0x0000000c
268 #define TX39_CONF_DRSIZE_SHIFT 0
269 #define TX39_CONF_DRSIZE_MASK 0x00000003
272 * Status register bits available in all MIPS CPUs.
274 #define ST0_IM 0x0000ff00
275 #define STATUSB_IP0 8
276 #define STATUSF_IP0 (_ULCAST_(1) << 8)
277 #define STATUSB_IP1 9
278 #define STATUSF_IP1 (_ULCAST_(1) << 9)
279 #define STATUSB_IP2 10
280 #define STATUSF_IP2 (_ULCAST_(1) << 10)
281 #define STATUSB_IP3 11
282 #define STATUSF_IP3 (_ULCAST_(1) << 11)
283 #define STATUSB_IP4 12
284 #define STATUSF_IP4 (_ULCAST_(1) << 12)
285 #define STATUSB_IP5 13
286 #define STATUSF_IP5 (_ULCAST_(1) << 13)
287 #define STATUSB_IP6 14
288 #define STATUSF_IP6 (_ULCAST_(1) << 14)
289 #define STATUSB_IP7 15
290 #define STATUSF_IP7 (_ULCAST_(1) << 15)
291 #define STATUSB_IP8 0
292 #define STATUSF_IP8 (_ULCAST_(1) << 0)
293 #define STATUSB_IP9 1
294 #define STATUSF_IP9 (_ULCAST_(1) << 1)
295 #define STATUSB_IP10 2
296 #define STATUSF_IP10 (_ULCAST_(1) << 2)
297 #define STATUSB_IP11 3
298 #define STATUSF_IP11 (_ULCAST_(1) << 3)
299 #define STATUSB_IP12 4
300 #define STATUSF_IP12 (_ULCAST_(1) << 4)
301 #define STATUSB_IP13 5
302 #define STATUSF_IP13 (_ULCAST_(1) << 5)
303 #define STATUSB_IP14 6
304 #define STATUSF_IP14 (_ULCAST_(1) << 6)
305 #define STATUSB_IP15 7
306 #define STATUSF_IP15 (_ULCAST_(1) << 7)
307 #define ST0_CH 0x00040000
308 #define ST0_SR 0x00100000
309 #define ST0_TS 0x00200000
310 #define ST0_BEV 0x00400000
311 #define ST0_RE 0x02000000
312 #define ST0_FR 0x04000000
313 #define ST0_CU 0xf0000000
314 #define ST0_CU0 0x10000000
315 #define ST0_CU1 0x20000000
316 #define ST0_CU2 0x40000000
317 #define ST0_CU3 0x80000000
318 #define ST0_XX 0x80000000 /* MIPS IV naming */
321 * Bitfields and bit numbers in the coprocessor 0 cause register.
323 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
325 #define CAUSEB_EXCCODE 2
326 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
327 #define CAUSEB_IP 8
328 #define CAUSEF_IP (_ULCAST_(255) << 8)
329 #define CAUSEB_IP0 8
330 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
331 #define CAUSEB_IP1 9
332 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
333 #define CAUSEB_IP2 10
334 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
335 #define CAUSEB_IP3 11
336 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
337 #define CAUSEB_IP4 12
338 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
339 #define CAUSEB_IP5 13
340 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
341 #define CAUSEB_IP6 14
342 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
343 #define CAUSEB_IP7 15
344 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
345 #define CAUSEB_IV 23
346 #define CAUSEF_IV (_ULCAST_(1) << 23)
347 #define CAUSEB_CE 28
348 #define CAUSEF_CE (_ULCAST_(3) << 28)
349 #define CAUSEB_BD 31
350 #define CAUSEF_BD (_ULCAST_(1) << 31)
353 * Bits in the coprocessor 0 config register.
355 /* Generic bits. */
356 #define CONF_CM_CACHABLE_NO_WA 0
357 #define CONF_CM_CACHABLE_WA 1
358 #define CONF_CM_UNCACHED 2
359 #define CONF_CM_CACHABLE_NONCOHERENT 3
360 #define CONF_CM_CACHABLE_CE 4
361 #define CONF_CM_CACHABLE_COW 5
362 #define CONF_CM_CACHABLE_CUW 6
363 #define CONF_CM_CACHABLE_ACCELERATED 7
364 #define CONF_CM_CMASK 7
365 #define CONF_BE (_ULCAST_(1) << 15)
367 /* Bits common to various processors. */
368 #define CONF_CU (_ULCAST_(1) << 3)
369 #define CONF_DB (_ULCAST_(1) << 4)
370 #define CONF_IB (_ULCAST_(1) << 5)
371 #define CONF_DC (_ULCAST_(7) << 6)
372 #define CONF_IC (_ULCAST_(7) << 9)
373 #define CONF_EB (_ULCAST_(1) << 13)
374 #define CONF_EM (_ULCAST_(1) << 14)
375 #define CONF_SM (_ULCAST_(1) << 16)
376 #define CONF_SC (_ULCAST_(1) << 17)
377 #define CONF_EW (_ULCAST_(3) << 18)
378 #define CONF_EP (_ULCAST_(15)<< 24)
379 #define CONF_EC (_ULCAST_(7) << 28)
380 #define CONF_CM (_ULCAST_(1) << 31)
382 /* Bits specific to the R4xx0. */
383 #define R4K_CONF_SW (_ULCAST_(1) << 20)
384 #define R4K_CONF_SS (_ULCAST_(1) << 21)
385 #define R4K_CONF_SB (_ULCAST_(3) << 22)
387 /* Bits specific to the R5000. */
388 #define R5K_CONF_SE (_ULCAST_(1) << 12)
389 #define R5K_CONF_SS (_ULCAST_(3) << 20)
391 /* Bits specific to the R10000. */
392 #define R10K_CONF_DN (_ULCAST_(3) << 3)
393 #define R10K_CONF_CT (_ULCAST_(1) << 5)
394 #define R10K_CONF_PE (_ULCAST_(1) << 6)
395 #define R10K_CONF_PM (_ULCAST_(3) << 7)
396 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
397 #define R10K_CONF_SB (_ULCAST_(1) << 13)
398 #define R10K_CONF_SK (_ULCAST_(1) << 14)
399 #define R10K_CONF_SS (_ULCAST_(7) << 16)
400 #define R10K_CONF_SC (_ULCAST_(7) << 19)
401 #define R10K_CONF_DC (_ULCAST_(7) << 26)
402 #define R10K_CONF_IC (_ULCAST_(7) << 29)
404 /* Bits specific to the VR41xx. */
405 #define VR41_CONF_CS (_ULCAST_(1) << 12)
406 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
407 #define VR41_CONF_AD (_ULCAST_(1) << 23)
409 /* Bits specific to the R30xx. */
410 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
411 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
412 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
413 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
414 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
415 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
416 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
417 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
418 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
420 /* Bits specific to the TX49. */
421 #define TX49_CONF_DC (_ULCAST_(1) << 16)
422 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
423 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
424 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
426 /* Bits specific to the MIPS32/64 PRA. */
427 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
428 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
429 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
430 #define MIPS_CONF_M (_ULCAST_(1) << 31)
433 * R10000 performance counter definitions.
435 * FIXME: The R10000 performance counter opens a nice way to implement CPU
436 * time accounting with a precission of one cycle. I don't have
437 * R10000 silicon but just a manual, so ...
441 * Events counted by counter #0
443 #define CE0_CYCLES 0
444 #define CE0_INSN_ISSUED 1
445 #define CE0_LPSC_ISSUED 2
446 #define CE0_S_ISSUED 3
447 #define CE0_SC_ISSUED 4
448 #define CE0_SC_FAILED 5
449 #define CE0_BRANCH_DECODED 6
450 #define CE0_QW_WB_SECONDARY 7
451 #define CE0_CORRECTED_ECC_ERRORS 8
452 #define CE0_ICACHE_MISSES 9
453 #define CE0_SCACHE_I_MISSES 10
454 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
455 #define CE0_EXT_INTERVENTIONS_REQ 12
456 #define CE0_EXT_INVALIDATE_REQ 13
457 #define CE0_VIRTUAL_COHERENCY_COND 14
458 #define CE0_INSN_GRADUATED 15
461 * Events counted by counter #1
463 #define CE1_CYCLES 0
464 #define CE1_INSN_GRADUATED 1
465 #define CE1_LPSC_GRADUATED 2
466 #define CE1_S_GRADUATED 3
467 #define CE1_SC_GRADUATED 4
468 #define CE1_FP_INSN_GRADUATED 5
469 #define CE1_QW_WB_PRIMARY 6
470 #define CE1_TLB_REFILL 7
471 #define CE1_BRANCH_MISSPREDICTED 8
472 #define CE1_DCACHE_MISS 9
473 #define CE1_SCACHE_D_MISSES 10
474 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
475 #define CE1_EXT_INTERVENTION_HITS 12
476 #define CE1_EXT_INVALIDATE_REQ 13
477 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
478 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
481 * These flags define in which priviledge mode the counters count events
483 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
484 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
485 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
486 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
488 #ifndef __ASSEMBLY__
490 #define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE)
491 #define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2))
494 * Functions to access the r10k performance counter and control registers
496 #define read_r10k_perf_cntr(counter) \
497 ({ unsigned int __res; \
498 __asm__ __volatile__( \
499 "mfpc\t%0, "STR(counter) \
500 : "=r" (__res)); \
501 __res;})
503 #define write_r10k_perf_cntr(counter,val) \
504 __asm__ __volatile__( \
505 "mtpc\t%0, "STR(counter) \
506 : : "r" (val));
508 #define read_r10k_perf_cntl(counter) \
509 ({ unsigned int __res; \
510 __asm__ __volatile__( \
511 "mfps\t%0, "STR(counter) \
512 : "=r" (__res)); \
513 __res;})
515 #define write_r10k_perf_cntl(counter,val) \
516 __asm__ __volatile__( \
517 "mtps\t%0, "STR(counter) \
518 : : "r" (val));
521 * Macros to access the system control coprocessor
524 #define __read_32bit_c0_register(source, sel) \
525 ({ unsigned int __res; \
526 if (sel == 0) \
527 __asm__ __volatile__( \
528 "mfc0\t%0, " #source "\n\t" \
529 : "=r" (__res)); \
530 else \
531 __asm__ __volatile__( \
532 ".set\tmips32\n\t" \
533 "mfc0\t%0, " #source ", " #sel "\n\t" \
534 ".set\tmips0\n\t" \
535 : "=r" (__res)); \
536 __res; \
539 #define __read_64bit_c0_register(source, sel) \
540 ({ unsigned long __res; \
541 if (sel == 0) \
542 __asm__ __volatile__( \
543 ".set\tmips3\n\t" \
544 "dmfc0\t%0, " #source "\n\t" \
545 ".set\tmips0" \
546 : "=r" (__res)); \
547 else \
548 __asm__ __volatile__( \
549 ".set\tmips64\n\t" \
550 "dmfc0\t%0, " #source ", " #sel "\n\t" \
551 ".set\tmips0" \
552 : "=r" (__res)); \
553 __res; \
556 #define __write_32bit_c0_register(register, sel, value) \
557 do { \
558 if (sel == 0) \
559 __asm__ __volatile__( \
560 "mtc0\t%z0, " #register "\n\t" \
561 : : "Jr" (value)); \
562 else \
563 __asm__ __volatile__( \
564 ".set\tmips32\n\t" \
565 "mtc0\t%z0, " #register ", " #sel "\n\t" \
566 ".set\tmips0" \
567 : : "Jr" (value)); \
568 } while (0)
570 #define __write_64bit_c0_register(register, sel, value) \
571 do { \
572 if (sel == 0) \
573 __asm__ __volatile__( \
574 ".set\tmips3\n\t" \
575 "dmtc0\t%z0, " #register "\n\t" \
576 ".set\tmips0" \
577 : : "Jr" (value)); \
578 else \
579 __asm__ __volatile__( \
580 ".set\tmips64\n\t" \
581 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
582 ".set\tmips0" \
583 : : "Jr" (value)); \
584 } while (0)
586 #define __read_ulong_c0_register(reg, sel) \
587 ((sizeof(unsigned long) == 4) ? \
588 __read_32bit_c0_register(reg, sel) : \
589 __read_64bit_c0_register(reg, sel))
591 #define __write_ulong_c0_register(reg, sel, val) \
592 do { \
593 if (sizeof(unsigned long) == 4) \
594 __write_32bit_c0_register(reg, sel, val); \
595 else \
596 __write_64bit_c0_register(reg, sel, val); \
597 } while (0)
600 * These versions are only needed for systems with more than 38 bits of
601 * physical address space running the 32-bit kernel. That's none atm :-)
603 #define __read_64bit_c0_split(source, sel) \
604 ({ \
605 unsigned long long val; \
606 unsigned long flags; \
608 local_irq_save(flags); \
609 if (sel == 0) \
610 __asm__ __volatile__( \
611 ".set\tmips64\n\t" \
612 "dmfc0\t%M0, " #source "\n\t" \
613 "dsll\t%L0, %M0, 32\n\t" \
614 "dsrl\t%M0, %M0, 32\n\t" \
615 "dsrl\t%L0, %L0, 32\n\t" \
616 ".set\tmips0" \
617 : "=r" (val)); \
618 else \
619 __asm__ __volatile__( \
620 ".set\tmips64\n\t" \
621 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
622 "dsll\t%L0, %M0, 32\n\t" \
623 "dsrl\t%M0, %M0, 32\n\t" \
624 "dsrl\t%L0, %L0, 32\n\t" \
625 ".set\tmips0" \
626 : "=r" (val)); \
627 local_irq_restore(flags); \
629 val; \
632 #define __write_64bit_c0_split(source, sel, val) \
633 do { \
634 unsigned long flags; \
636 local_irq_save(flags); \
637 if (sel == 0) \
638 __asm__ __volatile__( \
639 ".set\tmips64\n\t" \
640 "dsll\t%L0, %L0, 32\n\t" \
641 "dsrl\t%L0, %L0, 32\n\t" \
642 "dsll\t%M0, %M0, 32\n\t" \
643 "or\t%L0, %L0, %M0\n\t" \
644 "dmtc0\t%L0, " #source "\n\t" \
645 ".set\tmips0" \
646 : : "r" (val)); \
647 else \
648 __asm__ __volatile__( \
649 ".set\tmips64\n\t" \
650 "dsll\t%L0, %L0, 32\n\t" \
651 "dsrl\t%L0, %L0, 32\n\t" \
652 "dsll\t%M0, %M0, 32\n\t" \
653 "or\t%L0, %L0, %M0\n\t" \
654 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
655 ".set\tmips0" \
656 : : "r" (val)); \
657 local_irq_restore(flags); \
658 } while (0)
660 #define read_c0_index() __read_32bit_c0_register($0, 0)
661 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
663 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
664 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
666 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
667 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
669 #define read_c0_conf() __read_32bit_c0_register($3, 0)
670 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
672 #define read_c0_context() __read_ulong_c0_register($4, 0)
673 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
675 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
676 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
678 #define read_c0_wired() __read_32bit_c0_register($6, 0)
679 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
681 #define read_c0_info() __read_32bit_c0_register($7, 0)
683 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
684 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
686 #define read_c0_badvaddr() __read_32bit_c0_register($8, 0)
688 #define read_c0_count() __read_32bit_c0_register($9, 0)
689 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
691 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
692 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
694 #define read_c0_compare() __read_32bit_c0_register($11, 0)
695 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
697 #define read_c0_status() __read_32bit_c0_register($12, 0)
698 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
700 #define read_c0_cause() __read_32bit_c0_register($13, 0)
701 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
703 #define read_c0_prid() __read_32bit_c0_register($15, 0)
705 #define read_c0_config() __read_32bit_c0_register($16, 0)
706 #define read_c0_config1() __read_32bit_c0_register($16, 1)
707 #define read_c0_config2() __read_32bit_c0_register($16, 2)
708 #define read_c0_config3() __read_32bit_c0_register($16, 3)
709 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
710 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
711 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
712 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
715 * The WatchLo register. There may be upto 8 of them.
717 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
718 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
719 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
720 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
721 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
722 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
723 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
724 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
725 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
726 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
727 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
728 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
729 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
730 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
731 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
732 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
735 * The WatchHi register. There may be upto 8 of them.
737 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
738 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
739 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
740 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
741 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
742 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
743 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
744 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
746 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
747 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
748 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
749 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
750 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
751 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
752 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
753 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
755 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
756 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
758 #define read_c0_intcontrol() __read_32bit_c0_register($20, 1)
759 #define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val)
761 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
762 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
764 #define read_c0_debug() __read_32bit_c0_register($23, 0)
765 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
767 #define read_c0_depc() __read_ulong_c0_register($24, 0)
768 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
770 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
771 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
773 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
774 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
776 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
778 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
779 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
781 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
782 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
784 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
785 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
787 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
788 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
790 #define read_c0_epc() __read_ulong_c0_register($14, 0)
791 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
793 #if 1
795 * Macros to access the system control coprocessor
797 #define read_32bit_cp0_register(source) \
798 ({ int __res; \
799 __asm__ __volatile__( \
800 ".set\tpush\n\t" \
801 ".set\treorder\n\t" \
802 "mfc0\t%0,"STR(source)"\n\t" \
803 ".set\tpop" \
804 : "=r" (__res)); \
805 __res;})
807 #define read_32bit_cp0_set1_register(source) \
808 ({ int __res; \
809 __asm__ __volatile__( \
810 ".set\tpush\n\t" \
811 ".set\treorder\n\t" \
812 "cfc0\t%0,"STR(source)"\n\t" \
813 ".set\tpop" \
814 : "=r" (__res)); \
815 __res;})
818 * For now use this only with interrupts disabled!
820 #define read_64bit_cp0_register(source) \
821 ({ int __res; \
822 __asm__ __volatile__( \
823 ".set\tmips3\n\t" \
824 "dmfc0\t%0,"STR(source)"\n\t" \
825 ".set\tmips0" \
826 : "=r" (__res)); \
827 __res;})
829 #define write_32bit_cp0_register(register,value) \
830 __asm__ __volatile__( \
831 "mtc0\t%0,"STR(register)"\n\t" \
832 "nop" \
833 : : "r" (value));
835 #define write_32bit_cp0_set1_register(register,value) \
836 __asm__ __volatile__( \
837 "ctc0\t%0,"STR(register)"\n\t" \
838 "nop" \
839 : : "r" (value));
841 #define write_64bit_cp0_register(register,value) \
842 __asm__ __volatile__( \
843 ".set\tmips3\n\t" \
844 "dmtc0\t%0,"STR(register)"\n\t" \
845 ".set\tmips0" \
846 : : "r" (value))
849 * This should be changed when we get a compiler that support the MIPS32 ISA.
851 #define read_mips32_cp0_config1() \
852 ({ int __res; \
853 __asm__ __volatile__( \
854 ".set\tnoreorder\n\t" \
855 ".set\tnoat\n\t" \
856 "#.set\tmips64\n\t" \
857 "#mfc0\t$1, $16, 1\n\t" \
858 "#.set\tmips0\n\t" \
859 ".word\t0x40018001\n\t" \
860 "move\t%0,$1\n\t" \
861 ".set\tat\n\t" \
862 ".set\treorder" \
863 :"=r" (__res)); \
864 __res;})
866 #endif
868 * Macros to access the floating point coprocessor control registers
870 #define read_32bit_cp1_register(source) \
871 ({ int __res; \
872 __asm__ __volatile__( \
873 ".set\tpush\n\t" \
874 ".set\treorder\n\t" \
875 "cfc1\t%0,"STR(source)"\n\t" \
876 ".set\tpop" \
877 : "=r" (__res)); \
878 __res;})
880 /* TLB operations. */
881 static inline void tlb_probe(void)
883 __asm__ __volatile__(
884 ".set noreorder\n\t"
885 "tlbp\n\t"
886 ".set reorder");
889 static inline void tlb_read(void)
891 __asm__ __volatile__(
892 ".set noreorder\n\t"
893 "tlbr\n\t"
894 ".set reorder");
897 static inline void tlb_write_indexed(void)
899 __asm__ __volatile__(
900 ".set noreorder\n\t"
901 "tlbwi\n\t"
902 ".set reorder");
905 static inline void tlb_write_random(void)
907 __asm__ __volatile__(
908 ".set noreorder\n\t"
909 "tlbwr\n\t"
910 ".set reorder");
914 * Manipulate bits in a c0 register.
916 #define __BUILD_SET_C0(name,register) \
917 static inline unsigned int \
918 set_c0_##name(unsigned int set) \
920 unsigned int res; \
922 res = read_c0_##name(); \
923 res |= set; \
924 write_c0_##name(res); \
926 return res; \
929 static inline unsigned int \
930 clear_c0_##name(unsigned int clear) \
932 unsigned int res; \
934 res = read_c0_##name(); \
935 res &= ~clear; \
936 write_c0_##name(res); \
938 return res; \
941 static inline unsigned int \
942 change_c0_##name(unsigned int change, unsigned int new) \
944 unsigned int res; \
946 res = read_c0_##name(); \
947 res &= ~change; \
948 res |= (new & change); \
949 write_c0_##name(res); \
951 return res; \
954 __BUILD_SET_C0(status,CP0_STATUS)
955 __BUILD_SET_C0(cause,CP0_CAUSE)
956 __BUILD_SET_C0(config,CP0_CONFIG)
958 #define set_cp0_status(x) set_c0_status(x)
959 #define set_cp0_cause(x) set_c0_cause(x)
960 #define set_cp0_config(x) set_c0_config(x)
962 #endif /* !__ASSEMBLY__ */
964 #endif /* _ASM_MIPSREGS_H */