firmware/rolo.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 Randy D. Wood
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "config.h"
  23 #include "lcd.h"
  24 #include "lcd-remote.h"
  25 #include "thread.h"
  26 #include "kernel.h"
  27 #include "sprintf.h"
  28 #include "button.h"
  29 #include "file.h"
  30 #include "audio.h"
  31 #include "system.h"
  32 #include "i2c.h"
  33 #include "adc.h"
  34 #include "string.h"
  35 #include "buffer.h"
  36 #include "rolo.h"
  37
  38 #ifdef MI4_FORMAT
  39 #include "crc32-mi4.h"
  40 #undef FIRMWARE_OFFSET_FILE_CRC
  41 #undef FIRMWARE_OFFSET_FILE_DATA
  42 #define FIRMWARE_OFFSET_FILE_CRC     0xC
  43 #define FIRMWARE_OFFSET_FILE_DATA    0x200
  44 #endif
  45
  46 #if !defined(IRIVER_IFP7XX_SERIES) && \
  47     (CONFIG_CPU != PP5002)
  48 /* FIX: this doesn't work on iFP, 3rd Gen ipods */
  49
  50 #define IRQ0_EDGE_TRIGGER 0x80
  51
  52 #ifdef CPU_PP
  53 /* Handle the COP properly - it needs to jump to a function outside SDRAM while
  54  * the new firmware is being loaded, and then jump to the start of SDRAM
  55  * TODO: Use the mailboxes built into the PP processor for this
  56  */
  57
  58 #if NUM_CORES > 1
  59 volatile unsigned char IDATA_ATTR cpu_message = 0;
  60 volatile unsigned char IDATA_ATTR cpu_reply = 0;
  61 extern int cop_idlestackbegin[];
  62
  63 void rolo_restart_cop(void) ICODE_ATTR;
  64 void rolo_restart_cop(void)
  65 {
  66     if (CURRENT_CORE == CPU)
  67     {
  68         /* There should be free thread slots aplenty */
  69         create_thread(rolo_restart_cop, cop_idlestackbegin, IDLE_STACK_SIZE,
  70                       0, "rolo COP" IF_PRIO(, PRIORITY_REALTIME)
  71                       IF_COP(, COP));
  72         return;
  73     }
  74
  75     COP_INT_DIS = -1;
  76
  77     /* Invalidate cache */
  78     invalidate_icache();
  79
  80     /* Disable cache */
  81     CACHE_CTL = CACHE_CTL_DISABLE;
  82
  83     /* Tell the main core that we're ready to reload */
  84     cpu_reply = 1;
  85
  86     /* Wait while RoLo loads the image into SDRAM */
  87     /* TODO: Accept checksum failure gracefully */
  88     while(cpu_message != 1);
  89
  90     /* Acknowledge the CPU and then reload */
  91     cpu_reply = 2;
  92
  93     asm volatile(
  94         "mov   r0, #0x10000000   \n"
  95         "mov   pc, r0            \n"
  96     );
  97 }
  98 #endif /* NUM_CORES > 1 */
  99 #endif /* CPU_PP */
 100
 101 static void rolo_error(const char *text)
 102 {
 103     lcd_clear_display();
 104     lcd_puts(0, 0, "ROLO error:");
 105     lcd_puts_scroll(0, 1, text);
 106     lcd_update();
 107     button_get(true);
 108     button_get(true);
 109     button_get(true);
 110     lcd_stop_scroll();
 111 }
 112
 113 #if CONFIG_CPU == SH7034 || CONFIG_CPU == IMX31L
 114 /* these are in assembler file "descramble.S" for SH7034 */
 115 extern unsigned short descramble(const unsigned char* source,
 116                                  unsigned char* dest, int length);
 117 /* this is in firmware/target/arm/imx31/rolo_restart.S for IMX31 */
 118 extern void rolo_restart(const unsigned char* source, unsigned char* dest,
 119                          int length);
 120 #else
 121
 122 /* explicitly put this code in iram, ICODE_ATTR is defined to be null for some
 123    targets that are low on iram, like the gigabeat F/X */
 124 void rolo_restart(const unsigned char* source, unsigned char* dest,
 125                   long length) __attribute__ ((section(".icode")));
 126 void rolo_restart(const unsigned char* source, unsigned char* dest,
 127                   long length)
 128 {
 129     long i;
 130     unsigned char* localdest = dest;
 131
 132     /* This is the equivalent of a call to memcpy() but this must be done from
 133        iram to avoid overwriting itself and we don't want to depend on memcpy()
 134        always being in iram */
 135     for(i = 0;i < length;i++)
 136         *localdest++ = *source++;
 137
 138 #if defined(CPU_COLDFIRE)
 139     asm (
 140         "movec.l %0,%%vbr    \n"
 141         "move.l  (%0)+,%%sp  \n"
 142         "move.l  (%0),%0     \n"
 143         "jmp     (%0)        \n"
 144         : : "a"(dest)
 145     );
 146 #elif defined(CPU_PP502x)
 147     CPU_INT_DIS = -1;
 148
 149     /* Flush cache */
 150     flush_icache();
 151
 152     /* Disable cache */
 153     CACHE_CTL = CACHE_CTL_DISABLE;
 154
 155     /* Reset the memory mapping registers to zero */
 156     {
 157         volatile unsigned long *mmap_reg;
 158         for (mmap_reg = &MMAP_FIRST; mmap_reg <= &MMAP_LAST; mmap_reg++)
 159             *mmap_reg = 0;
 160     }
 161
 162 #if NUM_CORES > 1
 163     /* Tell the COP it's safe to continue rebooting */
 164     cpu_message = 1;
 165
 166     /* Wait for the COP to tell us it is rebooting */
 167     while(cpu_reply != 2);
 168 #endif
 169
 170     asm volatile(
 171         "mov   r0, #0x10000000   \n"
 172         "mov   pc, r0            \n"
 173     );
 174
 175 #elif defined(CPU_TCC780X) || (CONFIG_CPU == S3C2440)
 176     /* Flush and invalidate caches */
 177     invalidate_icache();
 178
 179     asm volatile(
 180         "mov   pc, %0            \n"
 181         : : "r"(dest)
 182     );
 183 #endif
 184 }
 185 #endif
 186
 187 /* This is assigned in the linker control file */
 188 extern unsigned long loadaddress;
 189
 190 /***************************************************************************
 191  *
 192  * Name: rolo_load_app(char *filename,int scrambled)
 193  * Filename must be a fully defined filename including the path and extension
 194  *
 195  ***************************************************************************/
 196 int rolo_load(const char* filename)
 197 {
 198     int fd;
 199     long length;
 200 #if defined(CPU_COLDFIRE) || defined(CPU_ARM)
 201 #if !defined(MI4_FORMAT)
 202     int i;
 203 #endif
 204     unsigned long checksum,file_checksum;
 205 #else
 206     long file_length;
 207     unsigned short checksum,file_checksum;
 208 #endif
 209     unsigned char* ramstart = (void*)&loadaddress;
 210
 211     lcd_clear_display();
 212     lcd_puts(0, 0, "ROLO...");
 213     lcd_puts(0, 1, "Loading");
 214     lcd_update();
 215 #ifdef HAVE_REMOTE_LCD
 216     lcd_remote_clear_display();
 217     lcd_remote_puts(0, 0, "ROLO...");
 218     lcd_remote_puts(0, 1, "Loading");
 219     lcd_remote_update();
 220 #endif
 221
 222     audio_stop();
 223
 224     fd = open(filename, O_RDONLY);
 225     if(-1 == fd) {
 226         rolo_error("File not found");
 227         return -1;
 228     }
 229
 230     length = filesize(fd) - FIRMWARE_OFFSET_FILE_DATA;
 231
 232 #if defined(CPU_COLDFIRE) || defined(CPU_PP) || (CONFIG_CPU==DM320) \
 233      || defined(CPU_TCC780X) || (CONFIG_CPU==IMX31L) || (CONFIG_CPU == S3C2440)
 234     /* Read and save checksum */
 235     lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
 236     if (read(fd, &file_checksum, 4) != 4) {
 237         rolo_error("Error Reading checksum");
 238         return -1;
 239     }
 240
 241 #if !defined(MI4_FORMAT)
 242     /* Rockbox checksums are big-endian */
 243     file_checksum = betoh32(file_checksum);
 244 #endif
 245
 246 #if defined(CPU_PP) && NUM_CORES > 1
 247     lcd_puts(0, 2, "Waiting for coprocessor...");
 248     lcd_update();
 249     rolo_restart_cop();
 250     /* Wait for COP to be in safe code */
 251     while(cpu_reply != 1);
 252     lcd_puts(0, 2, "                          ");
 253     lcd_update();
 254 #endif
 255
 256     lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
 257
 258     if (read(fd, audiobuf, length) != length) {
 259         rolo_error("Error Reading File");
 260         return -1;
 261     }
 262
 263 #ifdef MI4_FORMAT
 264     /* Check CRC32 to see if we have a valid file */
 265     chksum_crc32gentab();
 266     checksum = chksum_crc32 (audiobuf, length);
 267 #else
 268     checksum = MODEL_NUMBER;
 269
 270     for(i = 0;i < length;i++) {
 271         checksum += audiobuf[i];
 272     }
 273 #endif
 274
 275     /* Verify checksum against file header */
 276     if (checksum != file_checksum) {
 277         rolo_error("Checksum Error");
 278         return -1;
 279     }
 280
 281     lcd_puts(0, 1, "Executing");
 282     lcd_update();
 283 #ifdef HAVE_REMOTE_LCD
 284     lcd_remote_puts(0, 1, "Executing");
 285     lcd_remote_update();
 286 #endif
 287     adc_close();
 288
 289 #ifdef CPU_ARM
 290     /* Should do these together since some ARM version should never have
 291      * FIQ disabled and not IRQ (imx31 errata). */
 292     disable_interrupt(IRQ_FIQ_STATUS);
 293 #else
 294     /* Some targets have a higher disable level than HIGEST_IRQ_LEVEL */
 295     set_irq_level(DISABLE_INTERRUPTS);
 296 #endif
 297
 298 #elif CONFIG_CPU == SH7034
 299     /* Read file length from header and compare to real file length */
 300     lseek(fd, FIRMWARE_OFFSET_FILE_LENGTH, SEEK_SET);
 301     if(read(fd, &file_length, 4) != 4) {
 302         rolo_error("Error Reading File Length");
 303         return -1;
 304     }
 305     if (length != file_length) {
 306         rolo_error("File length mismatch");
 307         return -1;
 308     }
 309
 310     /* Read and save checksum */
 311     lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
 312     if (read(fd, &file_checksum, 2) != 2) {
 313         rolo_error("Error Reading checksum");
 314         return -1;
 315     }
 316     lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
 317
 318     /* verify that file can be read and descrambled */
 319     if ((audiobuf + (2*length)+4) >= audiobufend) {
 320         rolo_error("Not enough room to load file");
 321         return -1;
 322     }
 323
 324     if (read(fd, &audiobuf[length], length) != (int)length) {
 325         rolo_error("Error Reading File");
 326         return -1;
 327     }
 328
 329     lcd_puts(0, 1, "Descramble");
 330     lcd_update();
 331
 332     checksum = descramble(audiobuf + length, audiobuf, length);
 333
 334     /* Verify checksum against file header */
 335     if (checksum != file_checksum) {
 336         rolo_error("Checksum Error");
 337         return -1;
 338     }
 339
 340     lcd_puts(0, 1, "Executing     ");
 341     lcd_update();
 342
 343     set_irq_level(HIGHEST_IRQ_LEVEL);
 344
 345     /* Calling these 2 initialization routines was necessary to get the
 346        the origional Archos version of the firmware to load and execute. */
 347     system_init();           /* Initialize system for restart */
 348     i2c_init();              /* Init i2c bus - it seems like a good idea */
 349     ICR = IRQ0_EDGE_TRIGGER; /* Make IRQ0 edge triggered */
 350     TSTR = 0xE0;             /* disable all timers */
 351     /* model-specific de-init, needed when flashed */
 352     /* Especially the Archos software is picky about this */
 353 #if defined(ARCHOS_RECORDER) || defined(ARCHOS_RECORDERV2) || \
 354     defined(ARCHOS_FMRECORDER)
 355     PAIOR = 0x0FA0;
 356 #endif
 357 #endif
 358     rolo_restart(audiobuf, ramstart, length);
 359
 360     return 0; /* this is never reached */
 361     (void)checksum; (void)file_checksum;
 362 }
 363 #else  /* !defined(IRIVER_IFP7XX_SERIES) */
 364 int rolo_load(const char* filename)
 365 {
 366     /* dummy */
 367     (void)filename;
 368     return 0;
 369 }
 370
 371 #endif /* !defined(IRIVER_IFP7XX_SERIES) */