firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2009 by Michael Sparmann
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22
  23 #include "config.h"
  24 #include "panic.h"
  25 #include "system.h"
  26 #include "kernel.h"
  27 #include "cpu.h"
  28 #include "inttypes.h"
  29 #include "nand-target.h"
  30 #include <pmu-target.h>
  31 #include <mmu-arm.h>
  32 #include <string.h>
  33 #include "led.h"
  34
  35
  36 #define NAND_CMD_READ       0x00
  37 #define NAND_CMD_PROGCNFRM  0x10
  38 #define NAND_CMD_READ2      0x30
  39 #define NAND_CMD_BLOCKERASE 0x60
  40 #define NAND_CMD_GET_STATUS 0x70
  41 #define NAND_CMD_PROGRAM    0x80
  42 #define NAND_CMD_ERASECNFRM 0xD0
  43 #define NAND_CMD_RESET      0xFF
  44
  45 #define NAND_STATUS_READY   0x40
  46
  47 #define NAND_DEVICEINFOTABLE_ENTRIES 33
  48
  49 static const struct nand_device_info_type nand_deviceinfotable[] =
  50 {
  51     {0x1580F1EC, 1024, 968, 0x40, 6, 2, 1, 2, 1},
  52     {0x1580DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
  53     {0x15C1DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
  54     {0x1510DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  55     {0x95C1DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  56     {0x2514DCEC, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
  57     {0x2514D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
  58     {0x2555D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
  59     {0x2555D5EC, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
  60     {0x2585D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
  61     {0x9580DCAD, 4096, 3872, 0x40, 6, 3, 2, 3, 2},
  62     {0xA514D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
  63     {0xA550D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
  64     {0xA560D5AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
  65     {0xA555D5AD, 8192, 7744, 0x80, 7, 3, 2, 3, 2},
  66     {0xA585D598, 8320, 7744, 0x80, 7, 3, 1, 2, 1},
  67     {0xA584D398, 4160, 3872, 0x80, 7, 3, 1, 2, 1},
  68     {0x95D1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
  69     {0x1580DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  70     {0x15C1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
  71     {0x9590DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  72     {0xA594D32C, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
  73     {0x2584DC2C, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
  74     {0xA5D5D52C, 8192, 7744, 0x80, 7, 3, 2, 2, 1},
  75     {0x95D1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
  76     {0x1580DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  77     {0x15C1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
  78     {0x9590DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
  79     {0xA594D389, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
  80     {0x2584DC89, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
  81     {0xA5D5D589, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
  82     {0xA514D320, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
  83     {0xA555D520, 8192, 3872, 0x80, 7, 2, 1, 2, 1}
  84 };
  85
  86 uint8_t nand_tunk1[4];
  87 uint8_t nand_twp[4];
  88 uint8_t nand_tunk2[4];
  89 uint8_t nand_tunk3[4];
  90 uint32_t nand_type[4];
  91 int nand_powered = 0;
  92 int nand_interleaved = 0;
  93 int nand_cached = 0;
  94 long nand_last_activity_value = -1;
  95 static long nand_stack[32];
  96
  97 static struct mutex nand_mtx;
  98 static struct wakeup nand_wakeup;
  99 static struct mutex ecc_mtx;
 100 static struct wakeup ecc_wakeup;
 101
 102 static uint8_t nand_data[0x800] __attribute__((aligned(16)));
 103 static uint8_t nand_ctrl[0x200] __attribute__((aligned(16)));
 104 static uint8_t nand_spare[0x40] __attribute__((aligned(16)));
 105 static uint8_t nand_ecc[0x30] __attribute__((aligned(16)));
 106
 107
 108 uint32_t nand_unlock(uint32_t rc)
 109 {
 110     led(false);
 111     nand_last_activity_value = current_tick;
 112     mutex_unlock(&nand_mtx);
 113     return rc;
 114 }
 115
 116 uint32_t ecc_unlock(uint32_t rc)
 117 {
 118     mutex_unlock(&ecc_mtx);
 119     return rc;
 120 }
 121
 122 uint32_t nand_timeout(long timeout)
 123 {
 124     if (TIME_AFTER(current_tick, timeout)) return 1;
 125     else
 126     {
 127         yield();
 128         return 0;
 129     }
 130 }
 131
 132 uint32_t nand_wait_rbbdone(void)
 133 {
 134     long timeout = current_tick + HZ / 50;
 135     while (!(FMCSTAT & FMCSTAT_RBBDONE))
 136         if (nand_timeout(timeout)) return 1;
 137     FMCSTAT = FMCSTAT_RBBDONE;
 138     return 0;
 139 }
 140
 141 uint32_t nand_wait_cmddone(void)
 142 {
 143     long timeout = current_tick + HZ / 50;
 144     while (!(FMCSTAT & FMCSTAT_CMDDONE))
 145         if (nand_timeout(timeout)) return 1;
 146     FMCSTAT = FMCSTAT_CMDDONE;
 147     return 0;
 148 }
 149
 150 uint32_t nand_wait_addrdone(void)
 151 {
 152     long timeout = current_tick + HZ / 50;
 153     while (!(FMCSTAT & FMCSTAT_ADDRDONE))
 154         if (nand_timeout(timeout)) return 1;
 155     FMCSTAT = FMCSTAT_ADDRDONE;
 156     return 0;
 157 }
 158
 159 uint32_t nand_wait_chip_ready(uint32_t bank)
 160 {
 161     long timeout = current_tick + HZ / 50;
 162     while (!(FMCSTAT & (FMCSTAT_BANK0READY << bank)))
 163         if (nand_timeout(timeout)) return 1;
 164     FMCSTAT = (FMCSTAT_BANK0READY << bank);
 165     return 0;
 166 }
 167
 168 void nand_set_fmctrl0(uint32_t bank, uint32_t flags)
 169 {
 170     FMCTRL0 = (nand_tunk1[bank] << 16) | (nand_twp[bank] << 12)
 171             | (1 << 11) | 1 | (1 << (bank + 1)) | flags;
 172 }
 173
 174 uint32_t nand_send_cmd(uint32_t cmd)
 175 {
 176     FMCMD = cmd;
 177     return nand_wait_rbbdone();
 178 }
 179
 180 uint32_t nand_send_address(uint32_t page, uint32_t offset)
 181 {
 182     FMANUM = 4;
 183     FMADDR0 = (page << 16) | offset;
 184     FMADDR1 = (page >> 16) & 0xFF;
 185     FMCTRL1 = FMCTRL1_DOTRANSADDR;
 186     return nand_wait_cmddone();
 187 }
 188
 189 uint32_t nand_reset(uint32_t bank)
 190 {
 191     nand_set_fmctrl0(bank, 0);
 192     if (nand_send_cmd(NAND_CMD_RESET)) return 1;
 193     if (nand_wait_chip_ready(bank)) return 1;
 194     FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
 195     sleep(0);
 196     return 0;
 197 }
 198
 199 uint32_t nand_wait_status_ready(uint32_t bank)
 200 {
 201     long timeout = current_tick + HZ / 50;
 202     nand_set_fmctrl0(bank, 0);
 203     if ((FMCSTAT & (FMCSTAT_BANK0READY << bank)))
 204         FMCSTAT = (FMCSTAT_BANK0READY << bank);
 205     FMCTRL1 = FMCTRL1_CLEARRFIFO;
 206     if (nand_send_cmd(NAND_CMD_GET_STATUS)) return 1;
 207     while (1)
 208     {
 209         if (nand_timeout(timeout)) return 1;
 210         FMDNUM = 0;
 211         FMCTRL1 = FMCTRL1_DOREADDATA;
 212         if (nand_wait_addrdone()) return 1;
 213         if ((FMFIFO & NAND_STATUS_READY)) break;
 214         FMCTRL1 = FMCTRL1_CLEARRFIFO;
 215     }
 216     FMCTRL1 = FMCTRL1_CLEARRFIFO;
 217     return nand_send_cmd(NAND_CMD_READ);
 218 }
 219
 220 void nand_transfer_data_start(uint32_t bank, uint32_t direction,
 221                               void* buffer, uint32_t size)
 222 {
 223     nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
 224     FMDNUM = size - 1;
 225     FMCTRL1 = FMCTRL1_DOREADDATA << direction;
 226     DMACON3 = (2 << DMACON_DEVICE_SHIFT)
 227             | (direction << DMACON_DIRECTION_SHIFT)
 228             | (2 << DMACON_DATA_SIZE_SHIFT)
 229             | (3 << DMACON_BURST_LEN_SHIFT);
 230     while ((DMAALLST & DMAALLST_CHAN3_MASK))
 231         DMACOM3 = DMACOM_CLEARBOTHDONE;
 232     DMABASE3 = (uint32_t)buffer;
 233     DMATCNT3 = (size >> 4) - 1;
 234     clean_dcache();
 235     DMACOM3 = 4;
 236 }
 237
 238 uint32_t nand_transfer_data_collect(uint32_t direction)
 239 {
 240     long timeout = current_tick + HZ / 50;
 241     while ((DMAALLST & DMAALLST_DMABUSY3))
 242         if (nand_timeout(timeout)) return 1;
 243     if (!direction) invalidate_dcache();
 244     if (nand_wait_addrdone()) return 1;
 245     if (!direction) FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
 246     else FMCTRL1 = FMCTRL1_CLEARRFIFO;
 247     return 0;
 248 }
 249
 250 uint32_t nand_transfer_data(uint32_t bank, uint32_t direction,
 251                             void* buffer, uint32_t size)
 252 {
 253     nand_transfer_data_start(bank, direction, buffer, size);
 254     uint32_t rc = nand_transfer_data_collect(direction);
 255     return rc;
 256 }
 257
 258 void ecc_start(uint32_t size, void* databuffer, void* sparebuffer, uint32_t type)
 259 {
 260     mutex_lock(&ecc_mtx);
 261     ECC_INT_CLR = 1;
 262     SRCPND = INTMSK_ECC;
 263     ECC_UNK1 = size;
 264     ECC_DATA_PTR = (uint32_t)databuffer;
 265     ECC_SPARE_PTR = (uint32_t)sparebuffer;
 266     clean_dcache();
 267     ECC_CTRL = type;
 268 }
 269
 270 uint32_t ecc_collect(void)
 271 {
 272     long timeout = current_tick + HZ / 50;
 273     while (!(SRCPND & INTMSK_ECC))
 274         if (nand_timeout(timeout)) return ecc_unlock(1);
 275     invalidate_dcache();
 276     ECC_INT_CLR = 1;
 277     SRCPND = INTMSK_ECC;
 278     return ecc_unlock(ECC_RESULT);
 279 }
 280
 281 uint32_t ecc_decode(uint32_t size, void* databuffer, void* sparebuffer)
 282 {
 283     ecc_start(size, databuffer, sparebuffer, ECCCTRL_STARTDECODING);
 284     uint32_t rc = ecc_collect();
 285     return rc;
 286 }
 287
 288 uint32_t ecc_encode(uint32_t size, void* databuffer, void* sparebuffer)
 289 {
 290     ecc_start(size, databuffer, sparebuffer, ECCCTRL_STARTENCODING);
 291     ecc_collect();
 292     return 0;
 293 }
 294
 295 uint32_t nand_check_empty(uint8_t* buffer)
 296 {
 297     uint32_t i, count;
 298     count = 0;
 299     for (i = 0; i < 0x40; i++) if (buffer[i] != 0xFF) count++;
 300     if (count < 2) return 1;
 301     return 0;
 302 }
 303
 304 uint32_t nand_get_chip_type(uint32_t bank)
 305 {
 306     mutex_lock(&nand_mtx);
 307     uint32_t result;
 308     if (nand_reset(bank)) return nand_unlock(0xFFFFFFFF);
 309     if (nand_send_cmd(0x90)) return nand_unlock(0xFFFFFFFF);
 310     FMANUM = 0;
 311     FMADDR0 = 0;
 312     FMCTRL1 = FMCTRL1_DOTRANSADDR;
 313     if (nand_wait_cmddone()) return nand_unlock(0xFFFFFFFF);
 314     FMDNUM = 4;
 315     FMCTRL1 = FMCTRL1_DOREADDATA;
 316     if (nand_wait_addrdone()) return nand_unlock(0xFFFFFFFF);
 317     result = FMFIFO;
 318     FMCTRL1 = FMCTRL1_CLEARRFIFO;
 319     return nand_unlock(result);
 320 }
 321
 322 void nand_set_active(void)
 323 {
 324     nand_last_activity_value = current_tick;
 325 }
 326
 327 long nand_last_activity(void)
 328 {
 329     return nand_last_activity_value;
 330 }
 331
 332 void nand_power_up(void)
 333 {
 334     uint32_t i;
 335     mutex_lock(&nand_mtx);
 336     nand_last_activity_value = current_tick;
 337     PWRCONEXT &= ~0x40;
 338     PWRCON &= ~0x100000;
 339     PCON2 = 0x33333333;
 340     PDAT2 = 0;
 341     PCON3 = 0x11113333;
 342     PDAT3 = 0;
 343     PCON4 = 0x33333333;
 344     PDAT4 = 0;
 345     PCON5 = (PCON5 & ~0xF) | 3;
 346     PUNK5 = 1;
 347     pmu_ldo_set_voltage(4, 0x15);
 348     pmu_ldo_power_on(4);
 349     sleep(HZ / 20);
 350     nand_last_activity_value = current_tick;
 351     for (i = 0; i < 4; i++)
 352     {
 353         if(nand_type[i] != 0xFFFFFFFF)
 354         {
 355             if(nand_reset(i))
 356                 panicf("nand_power_up: nand_reset(bank=%d) failed.",(unsigned int)i);
 357         }
 358     }
 359     nand_powered = 1;
 360     nand_last_activity_value = current_tick;
 361     mutex_unlock(&nand_mtx);
 362 }
 363
 364 void nand_power_down(void)
 365 {
 366     if (!nand_powered) return;
 367     mutex_lock(&nand_mtx);
 368     pmu_ldo_power_off(4);
 369     PCON2 = 0x11111111;
 370     PDAT2 = 0;
 371     PCON3 = 0x11111111;
 372     PDAT3 = 0;
 373     PCON4 = 0x11111111;
 374     PDAT4 = 0;
 375     PCON5 = (PCON5 & ~0xF) | 1;
 376     PUNK5 = 1;
 377     PWRCONEXT |= 0x40;
 378     PWRCON |= 0x100000;
 379     nand_powered = 0;
 380     mutex_unlock(&nand_mtx);
 381 }
 382
 383 uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
 384                         void* sparebuffer, uint32_t doecc,
 385                         uint32_t checkempty)
 386 {
 387     uint8_t* data = nand_data;
 388     uint8_t* spare = nand_spare;
 389     if (databuffer && !((uint32_t)databuffer & 0xf))
 390         data = (uint8_t*)databuffer;
 391     if (sparebuffer && !((uint32_t)sparebuffer & 0xf))
 392         spare = (uint8_t*)sparebuffer;
 393     mutex_lock(&nand_mtx);
 394     nand_last_activity_value = current_tick;
 395     led(true);
 396     if (!nand_powered) nand_power_up();
 397     uint32_t rc, eccresult;
 398     nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
 399     if (nand_send_cmd(NAND_CMD_READ)) return nand_unlock(1);
 400     if (nand_send_address(page, databuffer ? 0 : 0x800))
 401         return nand_unlock(1);
 402     if (nand_send_cmd(NAND_CMD_READ2)) return nand_unlock(1);
 403     if (nand_wait_status_ready(bank)) return nand_unlock(1);
 404     if (databuffer)
 405         if (nand_transfer_data(bank, 0, data, 0x800))
 406             return nand_unlock(1);
 407     rc = 0;
 408     if (!doecc)
 409     {
 410         if (databuffer && data != databuffer) memcpy(databuffer, data, 0x800);
 411         if (sparebuffer)
 412         {
 413             if (nand_transfer_data(bank, 0, spare, 0x40))
 414                 return nand_unlock(1);
 415             if (sparebuffer && spare != sparebuffer)
 416                 memcpy(sparebuffer, spare, 0x800);
 417             if (checkempty)
 418                 rc = nand_check_empty((uint8_t*)sparebuffer) << 1;
 419         }
 420         return nand_unlock(rc);
 421     }
 422     if (nand_transfer_data(bank, 0, spare, 0x40)) return nand_unlock(1);
 423     if (databuffer)
 424     {
 425         memcpy(nand_ecc, &spare[0xC], 0x28);
 426         rc |= (ecc_decode(3, data, nand_ecc) & 0xF) << 4;
 427         if (data != databuffer) memcpy(databuffer, data, 0x800);
 428     }
 429     memset(nand_ctrl, 0xFF, 0x200);
 430     memcpy(nand_ctrl, spare, 0xC);
 431     memcpy(nand_ecc, &spare[0x34], 0xC);
 432     eccresult = ecc_decode(0, nand_ctrl, nand_ecc);
 433     rc |= (eccresult & 0xF) << 8;
 434     if (sparebuffer)
 435     {
 436         if (spare != sparebuffer) memcpy(sparebuffer, spare, 0x40);
 437         if (eccresult & 1) memset(sparebuffer, 0xFF, 0xC);
 438         else memcpy(sparebuffer, nand_ctrl, 0xC);
 439     }
 440     if (checkempty) rc |= nand_check_empty(spare) << 1;
 441
 442     return nand_unlock(rc);
 443 }
 444
 445 uint32_t nand_write_page_int(uint32_t bank, uint32_t page, void* databuffer,
 446                              void* sparebuffer, uint32_t doecc, uint32_t wait)
 447 {
 448     uint8_t* data = nand_data;
 449     uint8_t* spare = nand_spare;
 450     if (databuffer && !((uint32_t)databuffer & 0xf))
 451         data = (uint8_t*)databuffer;
 452     if (sparebuffer && !((uint32_t)sparebuffer & 0xf))
 453         spare = (uint8_t*)sparebuffer;
 454     mutex_lock(&nand_mtx);
 455     nand_last_activity_value = current_tick;
 456     led(true);
 457     if (!nand_powered) nand_power_up();
 458     if (sparebuffer)
 459     {
 460         if (spare != sparebuffer) memcpy(spare, sparebuffer, 0x40);
 461     }
 462     else memset(spare, 0xFF, 0x40);
 463     nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
 464     if (nand_send_cmd(NAND_CMD_PROGRAM)) return nand_unlock(1);
 465     if (nand_send_address(page, databuffer ? 0 : 0x800))
 466         return nand_unlock(1);
 467     if (databuffer && data != databuffer) memcpy(data, databuffer, 0x800);
 468     if (databuffer) nand_transfer_data_start(bank, 1, data, 0x800);
 469     if (doecc)
 470     {
 471         if (ecc_encode(3, data, nand_ecc)) return nand_unlock(1);
 472         memcpy(&spare[0xC], nand_ecc, 0x28);
 473         memset(nand_ctrl, 0xFF, 0x200);
 474         memcpy(nand_ctrl, spare, 0xC);
 475         if (ecc_encode(0, nand_ctrl, nand_ecc)) return nand_unlock(1);
 476         memcpy(&spare[0x34], nand_ecc, 0xC);
 477     }
 478     if (databuffer)
 479         if (nand_transfer_data_collect(1))
 480             return nand_unlock(1);
 481     if (sparebuffer || doecc)
 482         if (nand_transfer_data(bank, 1, spare, 0x40))
 483             return nand_unlock(1);
 484     if (nand_send_cmd(NAND_CMD_PROGCNFRM)) return nand_unlock(1);
 485     if (wait) if (nand_wait_status_ready(bank)) return nand_unlock(1);
 486     return nand_unlock(0);
 487 }
 488
 489 uint32_t nand_block_erase(uint32_t bank, uint32_t page)
 490 {
 491     mutex_lock(&nand_mtx);
 492     nand_last_activity_value = current_tick;
 493     led(true);
 494     if (!nand_powered) nand_power_up();
 495     nand_set_fmctrl0(bank, 0);
 496     if (nand_send_cmd(NAND_CMD_BLOCKERASE)) return nand_unlock(1);
 497     FMANUM = 2;
 498     FMADDR0 = page;
 499     FMCTRL1 = FMCTRL1_DOTRANSADDR;
 500     if (nand_wait_cmddone()) return nand_unlock(1);
 501     if (nand_send_cmd(NAND_CMD_ERASECNFRM)) return nand_unlock(1);
 502     if (nand_wait_status_ready(bank)) return nand_unlock(1);
 503     return nand_unlock(0);
 504 }
 505
 506 uint32_t nand_read_page_fast(uint32_t page, void* databuffer,
 507                              void* sparebuffer, uint32_t doecc,
 508                              uint32_t checkempty)
 509 {
 510     uint32_t i, rc = 0;
 511     if (((uint32_t)databuffer & 0xf) || ((uint32_t)sparebuffer & 0xf)
 512      || !databuffer || !sparebuffer || !doecc)
 513     {
 514         for (i = 0; i < 4; i++)
 515         {
 516             if (nand_type[i] == 0xFFFFFFFF) continue;
 517             void* databuf = (void*)0;
 518             void* sparebuf = (void*)0;
 519             if (databuffer) databuf = (void*)((uint32_t)databuffer + 0x800 * i);
 520             if (sparebuffer) sparebuf = (void*)((uint32_t)sparebuffer + 0x40 * i);
 521             uint32_t ret = nand_read_page(i, page, databuf, sparebuf, doecc, checkempty);
 522             if (ret & 1) rc |= 1 << (i << 2);
 523             if (ret & 2) rc |= 2 << (i << 2);
 524             if (ret & 0x10) rc |= 4 << (i << 2);
 525             if (ret & 0x100) rc |= 8 << (i << 2);
 526         }
 527         return rc;
 528     }
 529     mutex_lock(&nand_mtx);
 530     nand_last_activity_value = current_tick;
 531     led(true);
 532     if (!nand_powered) nand_power_up();
 533     uint8_t status[4];
 534     for (i = 0; i < 4; i++) status[i] = (nand_type[i] == 0xFFFFFFFF);
 535     for (i = 0; i < 4; i++)
 536     {
 537         if (!status[i])
 538         {
 539             nand_set_fmctrl0(i, FMCTRL0_ENABLEDMA);
 540             if (nand_send_cmd(NAND_CMD_READ))
 541                 status[i] = 1;
 542         }
 543         if (!status[i])
 544             if (nand_send_address(page, 0))
 545                 status[i] = 1;
 546         if (!status[i])
 547             if (nand_send_cmd(NAND_CMD_READ2))
 548                 status[i] = 1;
 549     }
 550     if (!status[0])
 551         if (nand_wait_status_ready(0))
 552             status[0] = 1;
 553     if (!status[0])
 554         if (nand_transfer_data(0, 0, databuffer, 0x800))
 555             status[0] = 1;
 556     if (!status[0])
 557         if (nand_transfer_data(0, 0, sparebuffer, 0x40))
 558             status[0] = 1;
 559     for (i = 1; i < 4; i++)
 560     {
 561         if (!status[i])
 562             if (nand_wait_status_ready(i))
 563                 status[i] = 1;
 564         if (!status[i])
 565             nand_transfer_data_start(i, 0, (void*)((uint32_t)databuffer
 566                                                  + 0x800 * i), 0x800);
 567         if (!status[i - 1])
 568         {
 569             memcpy(nand_ecc, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0xC), 0x28);
 570             ecc_start(3, (void*)((uint32_t)databuffer
 571                                + 0x800 * (i - 1)), nand_ecc, ECCCTRL_STARTDECODING);
 572         }
 573         if (!status[i])
 574             if (nand_transfer_data_collect(0))
 575                 status[i] = 1;
 576         if (!status[i])
 577             nand_transfer_data_start(i, 0, (void*)((uint32_t)sparebuffer
 578                                                  + 0x40 * i), 0x40);
 579         if (!status[i - 1])
 580             if (ecc_collect() & 1)
 581                 status[i - 1] = 4;
 582         if (!status[i - 1])
 583         {
 584             memset(nand_ctrl, 0xFF, 0x200);
 585             memcpy(nand_ctrl, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xC);
 586             memcpy(nand_ecc, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0x34), 0xC);
 587             ecc_start(0, nand_ctrl, nand_ecc, ECCCTRL_STARTDECODING);
 588         }
 589         if (!status[i])
 590             if (nand_transfer_data_collect(0))
 591                 status[i] = 1;
 592         if (!status[i - 1])
 593         {
 594             if (ecc_collect() & 1)
 595             {
 596                 status[i - 1] |= 8;
 597                 memset((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xFF, 0xC);
 598             }
 599             else memcpy((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), nand_ctrl, 0xC);
 600             if (checkempty)
 601                 status[i - 1] |= nand_check_empty((void*)((uint32_t)sparebuffer
 602                                                         + 0x40 * (i - 1))) << 1;
 603         }
 604     }
 605     if (!status[i - 1])
 606     {
 607         memcpy(nand_ecc,(void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0xC), 0x28);
 608         if (ecc_decode(3, (void*)((uint32_t)databuffer
 609                                 + 0x800 * (i - 1)), nand_ecc) & 1)
 610             status[i - 1] = 4;
 611     }
 612     if (!status[i - 1])
 613     {
 614         memset(nand_ctrl, 0xFF, 0x200);
 615         memcpy(nand_ctrl, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xC);
 616         memcpy(nand_ecc, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0x34), 0xC);
 617         if (ecc_decode(0, nand_ctrl, nand_ecc) & 1)
 618         {
 619             status[i - 1] |= 8;
 620             memset((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xFF, 0xC);
 621         }
 622         else memcpy((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), nand_ctrl, 0xC);
 623         if (checkempty)
 624             status[i - 1] |= nand_check_empty((void*)((uint32_t)sparebuffer
 625                                                     + 0x40 * (i - 1))) << 1;
 626     }
 627     for (i = 0; i < 4; i++)
 628         if (nand_type[i] != 0xFFFFFFFF)
 629             rc |= status[i] << (i << 2);
 630     return nand_unlock(rc);
 631 }
 632
 633 uint32_t nand_write_page(uint32_t bank, uint32_t page, void* databuffer,
 634                          void* sparebuffer, uint32_t doecc)
 635 {
 636     return nand_write_page_int(bank, page, databuffer, sparebuffer, doecc, 1);
 637 }
 638
 639 uint32_t nand_write_page_start(uint32_t bank, uint32_t page, void* databuffer,
 640                                void* sparebuffer, uint32_t doecc)
 641 {
 642     if (((uint32_t)databuffer & 0xf) || ((uint32_t)sparebuffer & 0xf)
 643      || !databuffer || !sparebuffer || !doecc || !nand_interleaved)
 644         return nand_write_page_int(bank, page, databuffer, sparebuffer, doecc, !nand_interleaved);
 645
 646     mutex_lock(&nand_mtx);
 647     nand_last_activity_value = current_tick;
 648     led(true);
 649     if (!nand_powered) nand_power_up();
 650     nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
 651     if (nand_send_cmd(NAND_CMD_PROGRAM))
 652         return nand_unlock(1);
 653     if (nand_send_address(page, 0))
 654         return nand_unlock(1);
 655     nand_transfer_data_start(bank, 1, databuffer, 0x800);
 656     if (ecc_encode(3, databuffer, nand_ecc))
 657         return nand_unlock(1);
 658     memcpy((void*)((uint32_t)sparebuffer + 0xC), nand_ecc, 0x28);
 659     memset(nand_ctrl, 0xFF, 0x200);
 660     memcpy(nand_ctrl, sparebuffer, 0xC);
 661     if (ecc_encode(0, nand_ctrl, nand_ecc))
 662         return nand_unlock(1);
 663     memcpy((void*)((uint32_t)sparebuffer + 0x34), nand_ecc, 0xC);
 664     if (nand_transfer_data_collect(0))
 665         return nand_unlock(1);
 666     if (nand_transfer_data(bank, 1, sparebuffer, 0x40))
 667         return nand_unlock(1);
 668     return nand_unlock(nand_send_cmd(NAND_CMD_PROGCNFRM));
 669 }
 670
 671 uint32_t nand_write_page_collect(uint32_t bank)
 672 {
 673     return nand_wait_status_ready(bank);
 674 }
 675
 676 uint32_t nand_block_erase_fast(uint32_t page)
 677 {
 678     uint32_t i, rc = 0;
 679     mutex_lock(&nand_mtx);
 680     nand_last_activity_value = current_tick;
 681     led(true);
 682     if (!nand_powered) nand_power_up();
 683     for (i = 0; i < 4; i++)
 684     {
 685         if (nand_type[i] == 0xFFFFFFFF) continue;
 686         nand_set_fmctrl0(i, 0);
 687         if (nand_send_cmd(NAND_CMD_BLOCKERASE))
 688         {
 689             rc |= 1 << i;
 690             continue;
 691         }
 692         FMANUM = 2;
 693         FMADDR0 = page;
 694         FMCTRL1 = FMCTRL1_DOTRANSADDR;
 695         if (nand_wait_cmddone())
 696         {
 697             rc |= 1 << i;
 698             continue;
 699         }
 700         if (nand_send_cmd(NAND_CMD_ERASECNFRM)) rc |= 1 << i;
 701     }
 702     for (i = 0; i < 4; i++)
 703     {
 704         if (nand_type[i] == 0xFFFFFFFF) continue;
 705         if (rc & (1 << i)) continue;
 706         if (nand_wait_status_ready(i)) rc |= 1 << i;
 707     }
 708     return nand_unlock(rc);
 709 }
 710
 711 const struct nand_device_info_type* nand_get_device_type(uint32_t bank)
 712 {
 713     if (nand_type[bank] == 0xFFFFFFFF)
 714         return (struct nand_device_info_type*)0;
 715     return &nand_deviceinfotable[nand_type[bank]];
 716 }
 717
 718 static void nand_thread(void)
 719 {
 720     while (1)
 721     {
 722         if (TIME_AFTER(current_tick, nand_last_activity_value + HZ / 5)
 723          && nand_powered)
 724             nand_power_down();
 725         sleep(HZ / 10);
 726     }
 727 }
 728
 729 uint32_t nand_device_init(void)
 730 {
 731     mutex_init(&nand_mtx);
 732     wakeup_init(&nand_wakeup);
 733     mutex_init(&ecc_mtx);
 734     wakeup_init(&ecc_wakeup);
 735
 736     uint32_t type;
 737     uint32_t i, j;
 738
 739     /* Assume there are 0 banks, to prevent
 740        nand_power_up from talking with them yet. */
 741     for(i = 0; i < 4; i++) nand_type[i] = 0xFFFFFFFF;
 742     nand_power_up();
 743
 744     /* Now that the flash is powered on, detect how
 745        many banks we really have and initialize them. */
 746     for (i = 0; i < 4; i++)
 747     {
 748         nand_tunk1[i] = 7;
 749         nand_twp[i] = 7;
 750         nand_tunk2[i] = 7;
 751         nand_tunk3[i] = 7;
 752         type = nand_get_chip_type(i);
 753         if (type == 0xFFFFFFFF) continue;
 754         for (j = 0; ; j++)
 755         {
 756             if (j == ARRAYLEN(nand_deviceinfotable)) break;
 757             else if (nand_deviceinfotable[j].id == type)
 758             {
 759                 nand_type[i] = j;
 760                 break;
 761             }
 762         }
 763         nand_tunk1[i] = nand_deviceinfotable[nand_type[i]].tunk1;
 764         nand_twp[i] = nand_deviceinfotable[nand_type[i]].twp;
 765         nand_tunk2[i] = nand_deviceinfotable[nand_type[i]].tunk2;
 766         nand_tunk3[i] = nand_deviceinfotable[nand_type[i]].tunk3;
 767     }
 768     if (nand_type[0] == 0xFFFFFFFF) return 1;
 769     nand_interleaved = ((nand_type[0] >> 22) & 1);
 770     nand_cached = ((nand_type[0] >> 23) & 1);
 771
 772     nand_last_activity_value = current_tick;
 773     create_thread(nand_thread, nand_stack,
 774                   sizeof(nand_stack), 0, "nand"
 775                   IF_PRIO(, PRIORITY_USER_INTERFACE)
 776                   IF_COP(, CPU));
 777
 778     return 0;
 779 }