1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2006 Daniel Ankers
11 * Copyright © 2008-2009 Rafaël Carré
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
21 ****************************************************************************/
23 #include "config.h" /* for HAVE_MULTIVOLUME */
35 #include "pl081.h" /* DMA controller */
36 #include "dma-target.h" /* DMA request lines */
37 #include "clock-target.h"
40 #include "ata_idle_notify.h"
51 #define INTERNAL_AS3525 0 /* embedded SD card */
52 #define SD_SLOT_AS3525 1 /* SD slot if present */
55 #define MCI_NO_RESP (0<<0)
56 #define MCI_RESP (1<<0)
57 #define MCI_LONG_RESP (1<<1)
59 /* controller registers */
60 #define SD_BASE 0xC6070000
62 #define SD_REG(x) (*(volatile unsigned long *) (SD_BASE+x))
64 #define MCI_CTRL SD_REG(0x00)
67 #define CTRL_RESET (1<<0)
68 #define FIFO_RESET (1<<1)
69 #define DMA_RESET (1<<2)
70 #define INT_ENABLE (1<<4)
71 #define DMA_ENABLE (1<<5)
72 #define READ_WAIT (1<<6)
73 #define SEND_IRQ_RESP (1<<7)
74 #define ABRT_READ_DATA (1<<8)
75 #define SEND_CCSD (1<<9)
76 #define SEND_AS_CCSD (1<<10)
77 #define EN_OD_PULLUP (1<<24)
80 #define MCI_PWREN SD_REG(0x04) /* power enable */
82 #define PWR_CRD_0 (1<<0)
83 #define PWR_CRD_1 (1<<1)
84 #define PWR_CRD_2 (1<<2)
85 #define PWR_CRD_3 (1<<3)
87 #define MCI_CLKDIV SD_REG(0x08) /* clock divider */
88 /* CLK_DIV_0 : bits 7:0
89 * CLK_DIV_1 : bits 15:8
90 * CLK_DIV_2 : bits 23:16
91 * CLK_DIV_3 : bits 31:24
94 #define MCI_CLKSRC SD_REG(0x0C) /* clock source */
95 /* CLK_SRC_CRD0: bits 1:0
96 * CLK_SRC_CRD1: bits 3:2
97 * CLK_SRC_CRD2: bits 5:4
98 * CLK_SRC_CRD3: bits 7:6
101 #define MCI_CLKENA SD_REG(0x10) /* clock enable */
103 #define CCLK_ENA_CRD0 (1<<0)
104 #define CCLK_ENA_CRD1 (1<<1)
105 #define CCLK_ENA_CRD2 (1<<2)
106 #define CCLK_ENA_CRD3 (1<<3)
107 #define CCLK_LP_CRD0 (1<<16) /* LP --> Low Power Mode? */
108 #define CCLK_LP_CRD1 (1<<17)
109 #define CCLK_LP_CRD2 (1<<18)
110 #define CCLK_LP_CRD3 (1<<19)
112 #define MCI_TMOUT SD_REG(0x14) /* timeout */
113 /* response timeout bits 0:7
114 * data timeout bits 8:31
117 #define MCI_CTYPE SD_REG(0x18) /* card type */
118 /* 1 bit per card, set = wide bus */
119 #define WIDTH4_CRD0 (1<<0)
120 #define WIDTH4_CRD1 (1<<1)
121 #define WIDTH4_CRD2 (1<<2)
122 #define WIDTH4_CRD3 (1<<3)
124 #define MCI_BLKSIZ SD_REG(0x1C) /* block size bits 0:15*/
125 #define MCI_BYTCNT SD_REG(0x20) /* byte count bits 0:31*/
126 #define MCI_MASK SD_REG(0x24) /* interrupt mask */
130 #define MCI_ARGUMENT SD_REG(0x28)
131 #define MCI_COMMAND SD_REG(0x2C)
133 /* command bits (bits 5:0 are the command index) */
134 #define CMD_RESP_EXP_BIT (1<<6)
135 #define CMD_RESP_LENGTH_BIT (1<<7)
136 #define CMD_CHECK_CRC_BIT (1<<8)
137 #define CMD_DATA_EXP_BIT (1<<9)
138 #define CMD_RW_BIT (1<<10)
139 #define CMD_TRANSMODE_BIT (1<<11)
140 #define CMD_SENT_AUTO_STOP_BIT (1<<12)
141 #define CMD_WAIT_PRV_DAT_BIT (1<<13)
142 #define CMD_ABRT_CMD_BIT (1<<14)
143 #define CMD_SEND_INIT_BIT (1<<15)
144 #define CMD_CARD_NO(x) ((x)<<16) /* 5 bits wide */
145 #define CMD_SEND_CLK_ONLY (1<<21)
146 #define CMD_READ_CEATA (1<<22)
147 #define CMD_CCS_EXPECTED (1<<23)
148 #define CMD_DONE_BIT (1<<31)
151 #define MCI_RESP0 SD_REG(0x30)
152 #define MCI_RESP1 SD_REG(0x34)
153 #define MCI_RESP2 SD_REG(0x38)
154 #define MCI_RESP3 SD_REG(0x3C)
156 #define MCI_MASK_STATUS SD_REG(0x40) /* masked interrupt status */
157 #define MCI_RAW_STATUS SD_REG(0x44) /* raw interrupt status, also used as
160 /* interrupt bits */ /* C D E (Cmd) (Data) (End) */
161 #define MCI_INT_CRDDET (1<<0) /* card detect */
162 #define MCI_INT_RE (1<<1) /* x response error */
163 #define MCI_INT_CD (1<<2) /* x command done */
164 #define MCI_INT_DTO (1<<3) /* x data transfer over */
165 #define MCI_INT_TXDR (1<<4) /* tx fifo data request */
166 #define MCI_INT_RXDR (1<<5) /* rx fifo data request */
167 #define MCI_INT_RCRC (1<<6) /* x response crc error */
168 #define MCI_INT_DCRC (1<<7) /* x data crc error */
169 #define MCI_INT_RTO (1<<8) /* x response timeout */
170 #define MCI_INT_DRTO (1<<9) /* x data read timeout */
171 #define MCI_INT_HTO (1<<10) /* x data starv timeout */
172 #define MCI_INT_FRUN (1<<11) /* x fifo over/underrun */
173 #define MCI_INT_HLE (1<<12) /* x x hw locked while error */
174 #define MCI_INT_SBE (1<<13) /* x start bit error */
175 #define MCI_INT_ACD (1<<14) /* auto command done */
176 #define MCI_INT_EBE (1<<15) /* x end bit error */
177 #define MCI_INT_SDIO (0xf<<16)
181 * & 0xBA80 = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
182 * MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
184 * & 0x428 = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
185 * & 0x418 = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
188 #define MCI_CMD_ERROR \
194 #define MCI_DATA_ERROR \
203 #define MCI_STATUS SD_REG(0x48)
205 #define FIFO_RX_WM (1<<0)
206 #define FIFO_TX_WM (1<<1)
207 #define FIFO_EMPTY (1<<2)
208 #define FIFO_FULL (1<<3)
209 #define CMD_FSM_STATE_B0 (1<<4)
210 #define CMD_FSM_STATE_B1 (1<<5)
211 #define CMD_FSM_STATE_B2 (1<<6)
212 #define CMD_FSM_STATE_B3 (1<<7)
213 #define DATA_3_STAT (1<<8)
214 #define DATA_BUSY (1<<9)
215 #define DATA_STAT_MC_BUSY (1<<10)
216 #define RESP_IDX_B0 (1<<11)
217 #define RESP_IDX_B1 (1<<12)
218 #define RESP_IDX_B2 (1<<13)
219 #define RESP_IDX_B3 (1<<14)
220 #define RESP_IDX_B4 (1<<15)
221 #define RESP_IDX_B5 (1<<16)
222 #define FIFO_CNT_B00 (1<<17)
223 #define FIFO_CNT_B01 (1<<18)
224 #define FIFO_CNT_B02 (1<<19)
225 #define FIFO_CNT_B03 (1<<20)
226 #define FIFO_CNT_B04 (1<<21)
227 #define FIFO_CNT_B05 (1<<22)
228 #define FIFO_CNT_B06 (1<<23)
229 #define FIFO_CNT_B07 (1<<24)
230 #define FIFO_CNT_B08 (1<<25)
231 #define FIFO_CNT_B09 (1<<26)
232 #define FIFO_CNT_B10 (1<<27)
233 #define FIFO_CNT_B11 (1<<28)
234 #define FIFO_CNT_B12 (1<<29)
235 #define DMA_ACK (1<<30)
236 #define START_CMD (1<<31)
238 #define MCI_FIFOTH SD_REG(0x4C) /* FIFO threshold */
239 /* TX watermark : bits 11:0
240 * RX watermark : bits 27:16
241 * DMA MTRANS SIZE : bits 30:28
242 * bits 31, 15:12 : unused
244 #define MCI_FIFOTH_MASK 0x8000f000
246 #define MCI_CDETECT SD_REG(0x50) /* card detect */
248 #define CDETECT_CRD_0 (1<<0)
249 #define CDETECT_CRD_1 (1<<1)
250 #define CDETECT_CRD_2 (1<<2)
251 #define CDETECT_CRD_3 (1<<3)
253 #define MCI_WRTPRT SD_REG(0x54) /* write protect */
254 #define MCI_GPIO SD_REG(0x58)
255 #define MCI_TCBCNT SD_REG(0x5C) /* transferred CIU byte count (card)*/
256 #define MCI_TBBCNT SD_REG(0x60) /* transferred host/DMA to/from bytes (FIFO)*/
257 #define MCI_DEBNCE SD_REG(0x64) /* card detect debounce bits 23:0*/
258 #define MCI_USRID SD_REG(0x68) /* user id */
259 #define MCI_VERID SD_REG(0x6C) /* version id */
261 #define MCI_HCON SD_REG(0x70) /* hardware config */
263 * bits 5:1 : maximum card index
265 * bits 9:7 : DATA WIDTH
266 * bits 15:10 : ADDR WIDTH
267 * bits 17:16 : DMA IF
268 * bits 20:18 : DMA WIDTH
269 * bit 21 : FIFO RAM INSIDE
270 * bit 22 : IMPL HOLD REG
271 * bit 23 : SET CLK FALSE
272 * bits 25:24 : MAX CLK DIV IDX
273 * bit 26 : AREA OPTIM
276 #define MCI_BMOD SD_REG(0x80) /* bus mode */
284 #define MCI_PLDMND SD_REG(0x84) /* poll demand */
285 #define MCI_DBADDR SD_REG(0x88) /* descriptor base address */
286 #define MCI_IDSTS SD_REG(0x8C) /* internal DMAC status */
300 #define MCI_IDINTEN SD_REG(0x90) /* internal DMAC interrupt enable */
311 #define MCI_DSCADDR SD_REG(0x94) /* current host descriptor address */
312 #define MCI_BUFADDR SD_REG(0x98) /* current host buffer address */
314 #define MCI_FIFO ((unsigned long *) (SD_BASE+0x100))
316 #define UNALIGNED_NUM_SECTORS 10
317 static unsigned char aligned_buffer
[UNALIGNED_NUM_SECTORS
* SD_BLOCK_SIZE
] __attribute__((aligned(32))); /* align on cache line size */
318 static unsigned char *uncached_buffer
= UNCACHED_ADDR(&aligned_buffer
[0]);
320 static void init_controller(void);
321 static int sd_wait_for_state(const int drive
, unsigned int state
);
323 static tCardInfo card_info
[NUM_DRIVES
];
325 /* for compatibility */
326 static long last_disk_activity
= -1;
328 #define MIN_YIELD_PERIOD 5 /* ticks */
329 static long next_yield
= 0;
331 static long sd_stack
[(DEFAULT_STACK_SIZE
*2 + 0x200)/sizeof(long)];
332 static const char sd_thread_name
[] = "ata/sd";
333 static struct mutex sd_mtx SHAREDBSS_ATTR
;
334 static struct event_queue sd_queue
;
336 bool sd_enabled
= false;
339 static struct wakeup transfer_completion_signal
;
340 static volatile bool retry
;
342 #if defined(HAVE_MULTIDRIVE)
346 static inline void mci_delay(void) { int i
= 0xffff; while(i
--) ; }
350 MCI_CTRL
&= ~INT_ENABLE
;
351 const int status
= MCI_MASK_STATUS
;
353 MCI_RAW_STATUS
= status
; /* clear status */
355 if(status
& MCI_DATA_ERROR
)
358 if( status
& (MCI_INT_DTO
|MCI_DATA_ERROR
))
359 wakeup_signal(&transfer_completion_signal
);
361 MCI_CTRL
|= INT_ENABLE
;
364 static inline bool card_detect_target(void)
366 #if defined(HAVE_MULTIDRIVE)
367 #if defined(SANSA_FUZEV2)
369 #elif defined(SANSA_CLIPPLUS)
370 return !(GPIOA_PIN(2));
372 #error "microSD pin not defined for your target"
379 static bool send_cmd(const int drive
, const int cmd
, const int arg
, const int flags
,
380 unsigned long *response
)
382 #if defined(HAVE_MULTIDRIVE)
383 /* Check to see if we need to switch cards */
384 if(sd_present(SD_SLOT_AS3525
))
385 if(active_card
!= drive
)
387 GPIOB_PIN(5) = (1-drive
) << 5;
392 #define TRANSFER_CMD (cmd == SD_READ_MULTIPLE_BLOCK || \
393 cmd == SD_WRITE_MULTIPLE_BLOCK)
397 /* Construct MCI_COMMAND */
400 /*b6 */ | ((flags
& MCI_RESP
) ? CMD_RESP_EXP_BIT
: 0)
401 /*b7 */ | ((flags
& MCI_LONG_RESP
) ? CMD_RESP_LENGTH_BIT
: 0)
402 /*b8 | CMD_CHECK_CRC_BIT unused */
403 /*b9 */ | (TRANSFER_CMD
? CMD_DATA_EXP_BIT
: 0)
404 /*b10 */ | ((cmd
== SD_WRITE_MULTIPLE_BLOCK
) ? CMD_RW_BIT
: 0)
405 /*b11 | CMD_TRANSMODE_BIT unused */
406 /*b12 | CMD_SENT_AUTO_STOP_BIT unused */
407 /*b13 */ | (TRANSFER_CMD
? CMD_WAIT_PRV_DAT_BIT
: 0)
408 /*b14 | CMD_ABRT_CMD_BIT unused */
409 /*b15 | CMD_SEND_INIT_BIT unused */
410 /*b20:16 */ | CMD_CARD_NO(drive
)
411 /*b21 | CMD_SEND_CLK_ONLY unused */
412 /*b22 | CMD_READ_CEATA unused */
413 /*b23 | CMD_CCS_EXPECTED unused */
414 /*b31 */ | CMD_DONE_BIT
;
417 while(MCI_COMMAND
& CMD_DONE_BIT
)
419 if(--max
== 0) /* timeout */
423 /* TODO Check crc values to determine if the response was valid */
426 int i
= 0xff; while(i
--) ;
427 /* if we read the response too fast we might read the response
428 * of the previous command instead */
430 if(flags
& MCI_LONG_RESP
)
432 response
[0] = MCI_RESP3
;
433 response
[1] = MCI_RESP2
;
434 response
[2] = MCI_RESP1
;
435 response
[3] = MCI_RESP0
;
438 response
[0] = MCI_RESP0
;
443 static int sd_init_card(const int drive
)
445 unsigned long response
;
449 /* assume 24 MHz clock / 60 = 400 kHz */
450 MCI_CLKDIV
= (MCI_CLKDIV
& ~(0xFF)) | 0x3C; /* CLK_DIV_0 : bits 7:0 */
452 /* 100 - 400kHz clock required for Identification Mode */
453 /* Start of Card Identification Mode ************************************/
456 if(!send_cmd(drive
, SD_GO_IDLE_STATE
, 0, MCI_NO_RESP
, NULL
))
460 /* CMD8 Check for v2 sd card. Must be sent before using ACMD41
461 Non v2 cards will not respond to this command*/
462 if(send_cmd(drive
, SD_SEND_IF_COND
, 0x1AA, MCI_RESP
, &response
))
463 if((response
& 0xFFF) == 0x1AA)
466 /* timeout for initialization is 1sec, from SD Specification 2.00 */
467 init_timeout
= current_tick
+ HZ
;
470 /* this timeout is the only valid error for this loop*/
471 if(TIME_AFTER(current_tick
, init_timeout
))
475 send_cmd(drive
, SD_APP_CMD
, 0, MCI_RESP
, &response
);
477 /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
478 if(!send_cmd(drive
, SD_APP_OP_COND
, (0x00FF8000 | (sd_v2
? 1<<30 : 0)),
479 MCI_RESP
, &card_info
[drive
].ocr
))
481 } while(!(card_info
[drive
].ocr
& (1<<31)) );
484 if(!send_cmd(drive
, SD_ALL_SEND_CID
, 0, MCI_RESP
|MCI_LONG_RESP
, card_info
[drive
].cid
))
488 if(!send_cmd(drive
, SD_SEND_RELATIVE_ADDR
, 0, MCI_RESP
, &card_info
[drive
].rca
))
491 #ifdef HAVE_MULTIDRIVE
492 /* Make sure we have 2 unique rca numbers */
493 if(card_info
[INTERNAL_AS3525
].rca
== card_info
[SD_SLOT_AS3525
].rca
)
494 if(!send_cmd(drive
, SD_SEND_RELATIVE_ADDR
, 0, MCI_RESP
, &card_info
[drive
].rca
))
497 /* End of Card Identification Mode ************************************/
499 /* Attempt to switch cards to HS timings, non HS cards just ignore this */
500 /* CMD7 w/rca: Select card to put it in TRAN state */
501 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_RESP
, &response
))
504 if(sd_wait_for_state(drive
, SD_TRAN
))
508 if(!send_cmd(drive
, SD_SWITCH_FUNC
, 0x80fffff1, MCI_NO_RESP
, NULL
))
512 /* We need to go back to STBY state now so we can read csd */
513 /* CMD7 w/rca=0: Deselect card to put it in STBY state */
514 if(!send_cmd(drive
, SD_DESELECT_CARD
, 0, MCI_RESP
, &response
))
518 if(!send_cmd(drive
, SD_SEND_CSD
, card_info
[drive
].rca
,
519 MCI_RESP
|MCI_LONG_RESP
, card_info
[drive
].csd
))
522 sd_parse_csd(&card_info
[drive
]);
524 /* Card back to full speed */
525 MCI_CLKDIV
&= ~(0xFF); /* CLK_DIV_0 : bits 7:0 = 0x00 */
527 #ifndef HAVE_MULTIDRIVE
528 /* CMD7 w/rca: Select card to put it in TRAN state */
529 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_NO_RESP
, NULL
))
533 card_info
[drive
].initialized
= 1;
538 static void sd_thread(void) __attribute__((noreturn
));
539 static void sd_thread(void)
541 struct queue_event ev
;
542 bool idle_notified
= false;
546 queue_wait_w_tmo(&sd_queue
, &ev
, HZ
);
551 case SYS_HOTSWAP_INSERTED
:
552 case SYS_HOTSWAP_EXTRACTED
:
554 int microsd_init
= 1;
555 fat_lock(); /* lock-out FAT activity first -
556 prevent deadlocking via disk_mount that
557 would cause a reverse-order attempt with
559 mutex_lock(&sd_mtx
); /* lock-out card activity - direct calls
560 into driver that bypass the fat cache */
562 /* We now have exclusive control of fat cache and ata */
564 disk_unmount(SD_SLOT_AS3525
); /* release "by force", ensure file
565 descriptors aren't leaked and any busy
566 ones are invalid if mounting */
567 /* Force card init for new card, re-init for re-inserted one or
568 * clear if the last attempt to init failed with an error. */
569 card_info
[SD_SLOT_AS3525
].initialized
= 0;
571 if (ev
.id
== SYS_HOTSWAP_INSERTED
)
574 microsd_init
= sd_init_card(SD_SLOT_AS3525
);
575 if (microsd_init
< 0) /* initialisation failed */
576 panicf("microSD init failed : %d", microsd_init
);
578 microsd_init
= disk_mount(SD_SLOT_AS3525
); /* 0 if fail */
582 * Mount succeeded, or this was an EXTRACTED event,
583 * in both cases notify the system about the changed filesystems
586 queue_broadcast(SYS_FS_CHANGED
, 0);
587 /* Access is now safe */
588 mutex_unlock(&sd_mtx
);
595 if (TIME_BEFORE(current_tick
, last_disk_activity
+(3*HZ
)))
597 idle_notified
= false;
601 /* never let a timer wrap confuse us */
602 next_yield
= current_tick
;
606 call_storage_idle_notifys(false);
607 idle_notified
= true;
612 case SYS_USB_CONNECTED
:
613 usb_acknowledge(SYS_USB_CONNECTED_ACK
);
614 /* Wait until the USB cable is extracted again */
615 usb_wait_for_disconnect(&sd_queue
);
618 case SYS_USB_DISCONNECTED
:
619 usb_acknowledge(SYS_USB_DISCONNECTED_ACK
);
626 static void init_controller(void)
628 int hcon_numcards
= ((MCI_HCON
>>1) & 0x1F) + 1;
629 int card_mask
= (1 << hcon_numcards
) - 1;
631 MCI_PWREN
&= ~card_mask
; /* power off all cards */
633 MCI_CLKSRC
= 0x00; /* All CLK_SRC_CRD set to 0*/
634 MCI_CLKDIV
= 0x00; /* CLK_DIV_0 : bits 7:0 */
636 MCI_PWREN
|= card_mask
; /* power up cards */
639 MCI_CTRL
|= CTRL_RESET
;
640 while(MCI_CTRL
& CTRL_RESET
)
643 MCI_RAW_STATUS
= 0xffffffff;
645 MCI_TMOUT
= 0xffffffff; /* data b31:8, response b7:0 */
647 MCI_CTYPE
= 0x0; /* all cards 1 bit bus for now */
649 MCI_CLKENA
= card_mask
;
652 MCI_COMMAND
= CMD_DONE_BIT
|CMD_SEND_CLK_ONLY
|CMD_WAIT_PRV_DAT_BIT
;
653 while(MCI_COMMAND
& CMD_DONE_BIT
)
656 MCI_DEBNCE
= 0xfffff; /* default value */
658 MCI_FIFOTH
&= MCI_FIFOTH_MASK
;
659 MCI_FIFOTH
|= 0x503f0080;
661 MCI_MASK
= 0xffff & ~(MCI_INT_ACD
|MCI_INT_CRDDET
|MCI_INT_RXDR
|MCI_INT_TXDR
);
663 GPIOB_DIR
|= (1<<5); /* Pin B5 output */
665 MCI_CTRL
|= INT_ENABLE
;
672 CGU_PERI
|= CGU_MCI_CLOCK_ENABLE
;
674 CGU_IDE
= (1<<7) /* AHB interface enable */
675 | (AS3525_IDE_DIV
<< 2)
676 | 1; /* clock source = PLLA */
678 CGU_MEMSTICK
= (1<<7) /* interface enable */
679 | (AS3525_MS_DIV
<< 2)
680 | 1; /* clock source = PLLA */
682 CGU_SDSLOT
= (1<<7) /* interface enable */
683 | (AS3525_SDSLOT_DIV
<< 2)
684 | 1; /* clock source = PLLA */
686 wakeup_init(&transfer_completion_signal
);
688 #ifdef HAVE_MULTIDRIVE
689 /* setup isr for microsd monitoring */
690 VIC_INT_ENABLE
= (INTERRUPT_GPIOA
);
691 /* clear previous irq */
693 /* enable edge detecting */
695 /* detect both raising and falling edges */
699 VIC_INT_ENABLE
= INTERRUPT_NAND
;
702 ret
= sd_init_card(INTERNAL_AS3525
);
709 queue_init(&sd_queue
, true);
710 create_thread(sd_thread
, sd_stack
, sizeof(sd_stack
), 0,
711 sd_thread_name
IF_PRIO(, PRIORITY_USER_INTERFACE
) IF_COP(, CPU
));
720 static int sd_wait_for_state(const int drive
, unsigned int state
)
722 unsigned long response
;
723 unsigned int timeout
= 100; /* ticks */
724 long t
= current_tick
;
730 if(!send_cmd(drive
, SD_SEND_STATUS
, card_info
[drive
].rca
,
731 MCI_RESP
, &response
))
734 if (((response
>> 9) & 0xf) == state
)
737 if(TIME_AFTER(current_tick
, t
+ timeout
))
738 return -10 * ((response
>> 9) & 0xf);
740 if (TIME_AFTER((tick
= current_tick
), next_yield
))
743 timeout
+= current_tick
- tick
;
744 next_yield
= tick
+ MIN_YIELD_PERIOD
;
749 static int sd_transfer_sectors(IF_MD2(int drive
,) unsigned long start
,
750 int count
, void* buf
, bool write
)
753 #ifndef HAVE_MULTIDRIVE
757 /* skip SanDisk OF */
758 if (drive
== INTERNAL_AS3525
)
767 if (card_info
[drive
].initialized
<= 0)
769 ret
= sd_init_card(drive
);
770 if (!(card_info
[drive
].initialized
))
772 panicf("card not initialised (%d)", ret
);
773 goto sd_transfer_error
;
777 #ifdef HAVE_MULTIDRIVE
778 /* CMD7 w/rca: Select card to put it in TRAN state */
779 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_NO_RESP
, NULL
))
783 last_disk_activity
= current_tick
;
786 const int cmd
= write
? SD_WRITE_MULTIPLE_BLOCK
: SD_READ_MULTIPLE_BLOCK
;
790 void *dma_buf
= aligned_buffer
;
791 unsigned int transfer
= count
;
792 if(transfer
> UNALIGNED_NUM_SECTORS
)
793 transfer
= UNALIGNED_NUM_SECTORS
;
796 memcpy(uncached_buffer
, buf
, transfer
* SD_BLOCK_SIZE
);
798 /* Interrupt handler might set this to true during transfer */
801 MCI_BLKSIZ
= SD_BLOCK_SIZE
;
802 MCI_BYTCNT
= transfer
* SD_BLOCK_SIZE
;
804 ret
= sd_wait_for_state(drive
, SD_TRAN
);
807 static const char *st
[9] = {
808 "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV",
811 panicf("wait for TRAN state failed (%s) %d",
812 st
[(-ret
/ 10) % 9], drive
);
814 panicf("wait for state failed");
815 goto sd_transfer_error
;
818 MCI_MASK
|= (MCI_DATA_ERROR
| MCI_INT_DTO
);
819 MCI_CTRL
|= DMA_ENABLE
;
821 MCI_FIFOTH
&= MCI_FIFOTH_MASK
;
822 MCI_FIFOTH
|= 0x503f0080;
825 if(!(card_info
[drive
].ocr
& (1<<30))) /* not SDHC */
826 arg
*= SD_BLOCK_SIZE
;
828 if(!send_cmd(drive
, cmd
, arg
, MCI_NO_RESP
, NULL
))
829 panicf("%s multiple blocks failed", write
? "write" : "read");
832 dma_enable_channel(0, dma_buf
, MCI_FIFO
, DMA_PERI_SD
,
833 DMAC_FLOWCTRL_PERI_MEM_TO_PERI
, true, false, 0, DMA_S8
, NULL
);
835 dma_enable_channel(0, MCI_FIFO
, dma_buf
, DMA_PERI_SD
,
836 DMAC_FLOWCTRL_PERI_PERI_TO_MEM
, false, true, 0, DMA_S8
, NULL
);
838 wakeup_wait(&transfer_completion_signal
, TIMEOUT_BLOCK
);
840 MCI_MASK
&= ~(MCI_DATA_ERROR
| MCI_INT_DTO
);
842 last_disk_activity
= current_tick
;
844 if(!send_cmd(drive
, SD_STOP_TRANSMISSION
, 0, MCI_NO_RESP
, NULL
))
847 panicf("STOP TRANSMISSION failed");
848 goto sd_transfer_error
;
854 memcpy(buf
, uncached_buffer
, transfer
* SD_BLOCK_SIZE
);
855 buf
+= transfer
* SD_BLOCK_SIZE
;
859 else /* reset controller if we had an error */
861 MCI_CTRL
|= (FIFO_RESET
|DMA_RESET
);
862 while(MCI_CTRL
& (FIFO_RESET
|DMA_RESET
))
866 } while(retry
|| count
);
870 #ifdef HAVE_MULTIDRIVE
871 /* CMD lines are separate, not common, so we need to actively deselect */
872 /* CMD7 w/rca =0 : deselects card & puts it in STBY state */
873 if(!send_cmd(drive
, SD_DESELECT_CARD
, 0, MCI_NO_RESP
, NULL
))
881 mutex_unlock(&sd_mtx
);
885 panicf("transfer error : %d",ret
);
886 card_info
[drive
].initialized
= 0;
890 int sd_read_sectors(IF_MD2(int drive
,) unsigned long start
, int count
,
893 return sd_transfer_sectors(IF_MD2(drive
,) start
, count
, buf
, false);
896 int sd_write_sectors(IF_MD2(int drive
,) unsigned long start
, int count
,
899 #if 1 /* disabled until stable*/ \
900 || defined(BOOTLOADER) /* we don't need write support in bootloader */
901 #ifdef HAVE_MULTIDRIVE
909 return sd_transfer_sectors(IF_MD2(drive
,) start
, count
, (void*)buf
, true);
914 long sd_last_disk_activity(void)
916 return last_disk_activity
;
919 void sd_enable(bool on
)
923 CCU_IO
|= (1<<2); /* XPD is SD-MCI interface (b3:2 = 01) */
925 CCU_IO
&= ~(1<<2); /* XPD is general purpose IO (b3:2 = 00) */
929 tCardInfo
*card_get_info_target(int card_no
)
931 return &card_info
[card_no
];
933 #endif /* BOOTLOADER */
936 bool sd_removable(IF_MD_NONVOID(int drive
))
941 bool sd_present(IF_MD_NONVOID(int drive
))
943 return (drive
== 0) ? true : card_detect_target();
946 static int sd1_oneshot_callback(struct timeout
*tmo
)
950 /* This is called only if the state was stable for 300ms - check state
951 * * and post appropriate event. */
952 if (card_detect_target())
954 queue_broadcast(SYS_HOTSWAP_INSERTED
, 0);
957 queue_broadcast(SYS_HOTSWAP_EXTRACTED
, 0);
964 static struct timeout sd1_oneshot
;
965 /* acknowledge interrupt */
967 timeout_register(&sd1_oneshot
, sd1_oneshot_callback
, (3*HZ
/10), 0);
970 void card_enable_monitoring_target(bool on
)
972 if (on
) /* enable interrupt */
974 else /* disable interrupt */
977 #endif /* HAVE_HOTSWAP */
979 #ifdef CONFIG_STORAGE_MULTI
980 int sd_num_drives(int first_drive
)
982 /* We don't care which logical drive number(s) we have been assigned */
987 #endif /* CONFIG_STORAGE_MULTI */