firmware/target/arm/usb-drv-arc.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Driver for ARC USBOTG Device Controller
  11  *
  12  * Copyright (C) 2007 by Björn Stenberg
  13  *
  14  * All files in this archive are subject to the GNU General Public License.
  15  * See the file COPYING in the source tree root for full license agreement.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "system.h"
  23 #include "config.h"
  24 #include "string.h"
  25 #include "usb_ch9.h"
  26 #include "usb_core.h"
  27 #include "kernel.h"
  28 #include "panic.h"
  29 //#define LOGF_ENABLE
  30 #include "logf.h"
  31
  32 #if CONFIG_CPU == IMX31L
  33 #include "avic-imx31.h"
  34 static void __attribute__((interrupt("IRQ"))) USB_OTG_HANDLER(void);
  35 #endif
  36
  37 /* USB device mode registers (Little Endian) */
  38
  39 #define REG_ID               (*(volatile unsigned int *)(USB_BASE+0x000))
  40 #define REG_HWGENERAL        (*(volatile unsigned int *)(USB_BASE+0x004))
  41 #define REG_HWHOST           (*(volatile unsigned int *)(USB_BASE+0x008))
  42 #define REG_HWDEVICE         (*(volatile unsigned int *)(USB_BASE+0x00c))
  43 #define REG_TXBUF            (*(volatile unsigned int *)(USB_BASE+0x010))
  44 #define REG_RXBUF            (*(volatile unsigned int *)(USB_BASE+0x014))
  45 #define REG_CAPLENGTH        (*(volatile unsigned char*)(USB_BASE+0x100))
  46 #define REG_DCIVERSION       (*(volatile unsigned int *)(USB_BASE+0x120))
  47 #define REG_DCCPARAMS        (*(volatile unsigned int *)(USB_BASE+0x124))
  48 #define REG_USBCMD           (*(volatile unsigned int *)(USB_BASE+0x140))
  49 #define REG_USBSTS           (*(volatile unsigned int *)(USB_BASE+0x144))
  50 #define REG_USBINTR          (*(volatile unsigned int *)(USB_BASE+0x148))
  51 #define REG_FRINDEX          (*(volatile unsigned int *)(USB_BASE+0x14c))
  52 #define REG_DEVICEADDR       (*(volatile unsigned int *)(USB_BASE+0x154))
  53 #define REG_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158))
  54 #define REG_BURSTSIZE        (*(volatile unsigned int *)(USB_BASE+0x160))
  55 #define REG_ULPI             (*(volatile unsigned int *)(USB_BASE+0x170))
  56 #define REG_CONFIGFLAG       (*(volatile unsigned int *)(USB_BASE+0x180))
  57 #define REG_PORTSC1          (*(volatile unsigned int *)(USB_BASE+0x184))
  58 #define REG_OTGSC            (*(volatile unsigned int *)(USB_BASE+0x1a4))
  59 #define REG_USBMODE          (*(volatile unsigned int *)(USB_BASE+0x1a8))
  60 #define REG_ENDPTSETUPSTAT   (*(volatile unsigned int *)(USB_BASE+0x1ac))
  61 #define REG_ENDPTPRIME       (*(volatile unsigned int *)(USB_BASE+0x1b0))
  62 #define REG_ENDPTFLUSH       (*(volatile unsigned int *)(USB_BASE+0x1b4))
  63 #define REG_ENDPTSTATUS      (*(volatile unsigned int *)(USB_BASE+0x1b8))
  64 #define REG_ENDPTCOMPLETE    (*(volatile unsigned int *)(USB_BASE+0x1bc))
  65 #define REG_ENDPTCTRL0       (*(volatile unsigned int *)(USB_BASE+0x1c0))
  66 #define REG_ENDPTCTRL1       (*(volatile unsigned int *)(USB_BASE+0x1c4))
  67 #define REG_ENDPTCTRL2       (*(volatile unsigned int *)(USB_BASE+0x1c8))
  68 #define REG_ENDPTCTRL(_x_)   (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(_x_)))
  69
  70 /* Frame Index Register Bit Masks */
  71 #define USB_FRINDEX_MASKS                      (0x3fff)
  72
  73 /* USB CMD  Register Bit Masks */
  74 #define USBCMD_RUN                            (0x00000001)
  75 #define USBCMD_CTRL_RESET                     (0x00000002)
  76 #define USBCMD_PERIODIC_SCHEDULE_EN           (0x00000010)
  77 #define USBCMD_ASYNC_SCHEDULE_EN              (0x00000020)
  78 #define USBCMD_INT_AA_DOORBELL                (0x00000040)
  79 #define USBCMD_ASP                            (0x00000300)
  80 #define USBCMD_ASYNC_SCH_PARK_EN              (0x00000800)
  81 #define USBCMD_SUTW                           (0x00002000)
  82 #define USBCMD_ATDTW                          (0x00004000)
  83 #define USBCMD_ITC                            (0x00FF0000)
  84
  85 /* bit 15,3,2 are frame list size */
  86 #define USBCMD_FRAME_SIZE_1024                (0x00000000)
  87 #define USBCMD_FRAME_SIZE_512                 (0x00000004)
  88 #define USBCMD_FRAME_SIZE_256                 (0x00000008)
  89 #define USBCMD_FRAME_SIZE_128                 (0x0000000C)
  90 #define USBCMD_FRAME_SIZE_64                  (0x00008000)
  91 #define USBCMD_FRAME_SIZE_32                  (0x00008004)
  92 #define USBCMD_FRAME_SIZE_16                  (0x00008008)
  93 #define USBCMD_FRAME_SIZE_8                   (0x0000800C)
  94
  95 /* bit 9-8 are async schedule park mode count */
  96 #define USBCMD_ASP_00                         (0x00000000)
  97 #define USBCMD_ASP_01                         (0x00000100)
  98 #define USBCMD_ASP_10                         (0x00000200)
  99 #define USBCMD_ASP_11                         (0x00000300)
 100 #define USBCMD_ASP_BIT_POS                    (8)
 101
 102 /* bit 23-16 are interrupt threshold control */
 103 #define USBCMD_ITC_NO_THRESHOLD               (0x00000000)
 104 #define USBCMD_ITC_1_MICRO_FRM                (0x00010000)
 105 #define USBCMD_ITC_2_MICRO_FRM                (0x00020000)
 106 #define USBCMD_ITC_4_MICRO_FRM                (0x00040000)
 107 #define USBCMD_ITC_8_MICRO_FRM                (0x00080000)
 108 #define USBCMD_ITC_16_MICRO_FRM               (0x00100000)
 109 #define USBCMD_ITC_32_MICRO_FRM               (0x00200000)
 110 #define USBCMD_ITC_64_MICRO_FRM               (0x00400000)
 111 #define USBCMD_ITC_BIT_POS                    (16)
 112
 113 /* USB STS Register Bit Masks */
 114 #define USBSTS_INT                            (0x00000001)
 115 #define USBSTS_ERR                            (0x00000002)
 116 #define USBSTS_PORT_CHANGE                    (0x00000004)
 117 #define USBSTS_FRM_LST_ROLL                   (0x00000008)
 118 #define USBSTS_SYS_ERR                        (0x00000010) /* not used */
 119 #define USBSTS_IAA                            (0x00000020)
 120 #define USBSTS_RESET                          (0x00000040)
 121 #define USBSTS_SOF                            (0x00000080)
 122 #define USBSTS_SUSPEND                        (0x00000100)
 123 #define USBSTS_HC_HALTED                      (0x00001000)
 124 #define USBSTS_RCL                            (0x00002000)
 125 #define USBSTS_PERIODIC_SCHEDULE              (0x00004000)
 126 #define USBSTS_ASYNC_SCHEDULE                 (0x00008000)
 127
 128 /* USB INTR Register Bit Masks */
 129 #define USBINTR_INT_EN                        (0x00000001)
 130 #define USBINTR_ERR_INT_EN                    (0x00000002)
 131 #define USBINTR_PTC_DETECT_EN                 (0x00000004)
 132 #define USBINTR_FRM_LST_ROLL_EN               (0x00000008)
 133 #define USBINTR_SYS_ERR_EN                    (0x00000010)
 134 #define USBINTR_ASYN_ADV_EN                   (0x00000020)
 135 #define USBINTR_RESET_EN                      (0x00000040)
 136 #define USBINTR_SOF_EN                        (0x00000080)
 137 #define USBINTR_DEVICE_SUSPEND                (0x00000100)
 138
 139 /* ULPI Register Bit Masks */
 140 #define ULPI_ULPIWU                           (0x80000000)
 141 #define ULPI_ULPIRUN                          (0x40000000)
 142 #define ULPI_ULPIRW                           (0x20000000)
 143 #define ULPI_ULPISS                           (0x08000000)
 144 #define ULPI_ULPIPORT                         (0x07000000)
 145 #define ULPI_ULPIADDR                         (0x00FF0000)
 146 #define ULPI_ULPIDATRD                        (0x0000FF00)
 147 #define ULPI_ULPIDATWR                        (0x000000FF)
 148
 149 /* Device Address bit masks */
 150 #define USBDEVICEADDRESS_MASK                 (0xFE000000)
 151 #define USBDEVICEADDRESS_BIT_POS              (25)
 152
 153 /* endpoint list address bit masks */
 154 #define USB_EP_LIST_ADDRESS_MASK               (0xfffff800)
 155
 156 /* PORTSCX  Register Bit Masks */
 157 #define PORTSCX_CURRENT_CONNECT_STATUS         (0x00000001)
 158 #define PORTSCX_CONNECT_STATUS_CHANGE          (0x00000002)
 159 #define PORTSCX_PORT_ENABLE                    (0x00000004)
 160 #define PORTSCX_PORT_EN_DIS_CHANGE             (0x00000008)
 161 #define PORTSCX_OVER_CURRENT_ACT               (0x00000010)
 162 #define PORTSCX_OVER_CURRENT_CHG               (0x00000020)
 163 #define PORTSCX_PORT_FORCE_RESUME              (0x00000040)
 164 #define PORTSCX_PORT_SUSPEND                   (0x00000080)
 165 #define PORTSCX_PORT_RESET                     (0x00000100)
 166 #define PORTSCX_LINE_STATUS_BITS               (0x00000C00)
 167 #define PORTSCX_PORT_POWER                     (0x00001000)
 168 #define PORTSCX_PORT_INDICTOR_CTRL             (0x0000C000)
 169 #define PORTSCX_PORT_TEST_CTRL                 (0x000F0000)
 170 #define PORTSCX_WAKE_ON_CONNECT_EN             (0x00100000)
 171 #define PORTSCX_WAKE_ON_CONNECT_DIS            (0x00200000)
 172 #define PORTSCX_WAKE_ON_OVER_CURRENT           (0x00400000)
 173 #define PORTSCX_PHY_LOW_POWER_SPD              (0x00800000)
 174 #define PORTSCX_PORT_FORCE_FULL_SPEED          (0x01000000)
 175 #define PORTSCX_PORT_SPEED_MASK                (0x0C000000)
 176 #define PORTSCX_PORT_WIDTH                     (0x10000000)
 177 #define PORTSCX_PHY_TYPE_SEL                   (0xC0000000)
 178
 179 /* bit 11-10 are line status */
 180 #define PORTSCX_LINE_STATUS_SE0                (0x00000000)
 181 #define PORTSCX_LINE_STATUS_JSTATE             (0x00000400)
 182 #define PORTSCX_LINE_STATUS_KSTATE             (0x00000800)
 183 #define PORTSCX_LINE_STATUS_UNDEF              (0x00000C00)
 184 #define PORTSCX_LINE_STATUS_BIT_POS            (10)
 185
 186 /* bit 15-14 are port indicator control */
 187 #define PORTSCX_PIC_OFF                        (0x00000000)
 188 #define PORTSCX_PIC_AMBER                      (0x00004000)
 189 #define PORTSCX_PIC_GREEN                      (0x00008000)
 190 #define PORTSCX_PIC_UNDEF                      (0x0000C000)
 191 #define PORTSCX_PIC_BIT_POS                    (14)
 192
 193 /* bit 19-16 are port test control */
 194 #define PORTSCX_PTC_DISABLE                    (0x00000000)
 195 #define PORTSCX_PTC_JSTATE                     (0x00010000)
 196 #define PORTSCX_PTC_KSTATE                     (0x00020000)
 197 #define PORTSCX_PTC_SE0NAK                     (0x00030000)
 198 #define PORTSCX_PTC_PACKET                     (0x00040000)
 199 #define PORTSCX_PTC_FORCE_EN                   (0x00050000)
 200 #define PORTSCX_PTC_BIT_POS                    (16)
 201
 202 /* bit 27-26 are port speed */
 203 #define PORTSCX_PORT_SPEED_FULL                (0x00000000)
 204 #define PORTSCX_PORT_SPEED_LOW                 (0x04000000)
 205 #define PORTSCX_PORT_SPEED_HIGH                (0x08000000)
 206 #define PORTSCX_PORT_SPEED_UNDEF               (0x0C000000)
 207 #define PORTSCX_SPEED_BIT_POS                  (26)
 208
 209 /* bit 28 is parallel transceiver width for UTMI interface */
 210 #define PORTSCX_PTW                            (0x10000000)
 211 #define PORTSCX_PTW_8BIT                       (0x00000000)
 212 #define PORTSCX_PTW_16BIT                      (0x10000000)
 213
 214 /* bit 31-30 are port transceiver select */
 215 #define PORTSCX_PTS_UTMI                       (0x00000000)
 216 #define PORTSCX_PTS_CLASSIC                    (0x40000000)
 217 #define PORTSCX_PTS_ULPI                       (0x80000000)
 218 #define PORTSCX_PTS_FSLS                       (0xC0000000)
 219 #define PORTSCX_PTS_BIT_POS                    (30)
 220
 221 /* USB MODE Register Bit Masks */
 222 #define USBMODE_CTRL_MODE_IDLE                (0x00000000)
 223 #define USBMODE_CTRL_MODE_DEVICE              (0x00000002)
 224 #define USBMODE_CTRL_MODE_HOST                (0x00000003)
 225 #define USBMODE_CTRL_MODE_RSV                 (0x00000001)
 226 #define USBMODE_SETUP_LOCK_OFF                (0x00000008)
 227 #define USBMODE_STREAM_DISABLE                (0x00000010)
 228
 229 /* Endpoint Flush Register */
 230 #define EPFLUSH_TX_OFFSET                      (0x00010000)
 231 #define EPFLUSH_RX_OFFSET                      (0x00000000)
 232
 233 /* Endpoint Setup Status bit masks */
 234 #define EPSETUP_STATUS_MASK                   (0x0000003F)
 235 #define EPSETUP_STATUS_EP0                    (0x00000001)
 236
 237 /* ENDPOINTCTRLx  Register Bit Masks */
 238 #define EPCTRL_TX_ENABLE                       (0x00800000)
 239 #define EPCTRL_TX_DATA_TOGGLE_RST              (0x00400000)    /* Not EP0 */
 240 #define EPCTRL_TX_DATA_TOGGLE_INH              (0x00200000)    /* Not EP0 */
 241 #define EPCTRL_TX_TYPE                         (0x000C0000)
 242 #define EPCTRL_TX_DATA_SOURCE                  (0x00020000)    /* Not EP0 */
 243 #define EPCTRL_TX_EP_STALL                     (0x00010000)
 244 #define EPCTRL_RX_ENABLE                       (0x00000080)
 245 #define EPCTRL_RX_DATA_TOGGLE_RST              (0x00000040)    /* Not EP0 */
 246 #define EPCTRL_RX_DATA_TOGGLE_INH              (0x00000020)    /* Not EP0 */
 247 #define EPCTRL_RX_TYPE                         (0x0000000C)
 248 #define EPCTRL_RX_DATA_SINK                    (0x00000002)    /* Not EP0 */
 249 #define EPCTRL_RX_EP_STALL                     (0x00000001)
 250
 251 /* bit 19-18 and 3-2 are endpoint type */
 252 #define EPCTRL_EP_TYPE_CONTROL                 (0)
 253 #define EPCTRL_EP_TYPE_ISO                     (1)
 254 #define EPCTRL_EP_TYPE_BULK                    (2)
 255 #define EPCTRL_EP_TYPE_INTERRUPT               (3)
 256 #define EPCTRL_TX_EP_TYPE_SHIFT                (18)
 257 #define EPCTRL_RX_EP_TYPE_SHIFT                (2)
 258
 259 /* pri_ctrl Register Bit Masks */
 260 #define PRI_CTRL_PRI_LVL1                      (0x0000000C)
 261 #define PRI_CTRL_PRI_LVL0                      (0x00000003)
 262
 263 /* si_ctrl Register Bit Masks */
 264 #define SI_CTRL_ERR_DISABLE                    (0x00000010)
 265 #define SI_CTRL_IDRC_DISABLE                   (0x00000008)
 266 #define SI_CTRL_RD_SAFE_EN                     (0x00000004)
 267 #define SI_CTRL_RD_PREFETCH_DISABLE            (0x00000002)
 268 #define SI_CTRL_RD_PREFEFETCH_VAL              (0x00000001)
 269
 270 /* control Register Bit Masks */
 271 #define USB_CTRL_IOENB                         (0x00000004)
 272 #define USB_CTRL_ULPI_INT0EN                   (0x00000001)
 273
 274 /* OTGSC Register Bit Masks */
 275 #define OTGSC_B_SESSION_VALID                  (0x00000800)
 276
 277 #define QH_MULT_POS                            (30)
 278 #define QH_ZLT_SEL                             (0x20000000)
 279 #define QH_MAX_PKT_LEN_POS                     (16)
 280 #define QH_IOS                                 (0x00008000)
 281 #define QH_NEXT_TERMINATE                      (0x00000001)
 282 #define QH_IOC                                 (0x00008000)
 283 #define QH_MULTO                               (0x00000C00)
 284 #define QH_STATUS_HALT                         (0x00000040)
 285 #define QH_STATUS_ACTIVE                       (0x00000080)
 286 #define EP_QUEUE_CURRENT_OFFSET_MASK         (0x00000FFF)
 287 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK      (0xFFFFFFE0)
 288 #define EP_QUEUE_FRINDEX_MASK                (0x000007FF)
 289 #define EP_MAX_LENGTH_TRANSFER               (0x4000)
 290
 291 #define DTD_NEXT_TERMINATE                   (0x00000001)
 292 #define DTD_IOC                              (0x00008000)
 293 #define DTD_STATUS_ACTIVE                    (0x00000080)
 294 #define DTD_STATUS_HALTED                    (0x00000040)
 295 #define DTD_STATUS_DATA_BUFF_ERR             (0x00000020)
 296 #define DTD_STATUS_TRANSACTION_ERR           (0x00000008)
 297 #define DTD_RESERVED_FIELDS                  (0x80007300)
 298 #define DTD_ADDR_MASK                        (0xFFFFFFE0)
 299 #define DTD_PACKET_SIZE                      (0x7FFF0000)
 300 #define DTD_LENGTH_BIT_POS                   (16)
 301 #define DTD_ERROR_MASK                       (DTD_STATUS_HALTED | \
 302                                                DTD_STATUS_DATA_BUFF_ERR | \
 303                                                DTD_STATUS_TRANSACTION_ERR)
 304
 305 #define DTD_RESERVED_LENGTH_MASK             0x0001ffff
 306 #define DTD_RESERVED_IN_USE                  0x80000000
 307 #define DTD_RESERVED_PIPE_MASK               0x0ff00000
 308 #define DTD_RESERVED_PIPE_OFFSET             20
 309 /*-------------------------------------------------------------------------*/
 310
 311 /* manual: 32.13.2 Endpoint Transfer Descriptor (dTD) */
 312 struct transfer_descriptor {
 313     unsigned int next_td_ptr;           /* Next TD pointer(31-5), T(0) set
 314                                            indicate invalid */
 315     unsigned int size_ioc_sts;          /* Total bytes (30-16), IOC (15),
 316                                            MultO(11-10), STS (7-0)  */
 317     unsigned int buff_ptr0;             /* Buffer pointer Page 0 */
 318     unsigned int buff_ptr1;             /* Buffer pointer Page 1 */
 319     unsigned int buff_ptr2;             /* Buffer pointer Page 2 */
 320     unsigned int buff_ptr3;             /* Buffer pointer Page 3 */
 321     unsigned int buff_ptr4;             /* Buffer pointer Page 4 */
 322     unsigned int reserved;
 323 } __attribute__ ((packed));
 324
 325 static struct transfer_descriptor td_array[NUM_ENDPOINTS*2]
 326     USBDEVBSS_ATTR __attribute__((aligned(32)));
 327
 328 /* manual: 32.13.1 Endpoint Queue Head (dQH) */
 329 struct queue_head {
 330     unsigned int max_pkt_length;    /* Mult(31-30) , Zlt(29) , Max Pkt len
 331                                        and IOS(15) */
 332     unsigned int curr_dtd_ptr;      /* Current dTD Pointer(31-5) */
 333     struct transfer_descriptor dtd; /* dTD overlay */
 334     unsigned int setup_buffer[2];   /* Setup data 8 bytes */
 335     unsigned int reserved;          /* for software use, pointer to the first TD */
 336     unsigned int status;            /* for software use, status of chain in progress */
 337     unsigned int length;            /* for software use, transfered bytes of chain in progress */
 338     unsigned int wait;              /* for softwate use, indicates if the transfer is blocking */
 339 } __attribute__((packed));
 340
 341 static struct queue_head qh_array[NUM_ENDPOINTS*2]
 342     USBDEVBSS_ATTR __attribute__((aligned (2048)));
 343
 344 static struct wakeup transfer_completion_signal[NUM_ENDPOINTS*2]
 345     SHAREDBSS_ATTR;
 346
 347 static const unsigned int pipe2mask[] = {
 348     0x01, 0x010000,
 349     0x02, 0x020000,
 350     0x04, 0x040000,
 351     0x08, 0x080000,
 352     0x10, 0x100000,
 353 };
 354
 355 /*-------------------------------------------------------------------------*/
 356 static void transfer_completed(void);
 357 static void control_received(void);
 358 static int prime_transfer(int endpoint, void* ptr,
 359                           int len, bool send, bool wait);
 360 static void prepare_td(struct transfer_descriptor* td,
 361                        struct transfer_descriptor* previous_td,
 362                        void *ptr, int len,int pipe);
 363 static void bus_reset(void);
 364 static void init_control_queue_heads(void);
 365 static void init_bulk_queue_heads(void);
 366 static void init_endpoints(void);
 367 /*-------------------------------------------------------------------------*/
 368
 369 bool usb_drv_powered(void)
 370 {
 371     return (REG_OTGSC & OTGSC_B_SESSION_VALID) ? true : false;
 372 }
 373
 374 /* One-time driver startup init */
 375 void usb_drv_startup(void)
 376 {
 377 #if CONFIG_CPU == IMX31L && defined(BOOTLOADER)
 378     /* This is the bootloader - activate the OTG controller or cold
 379      * connect later could/will fail */
 380     REG_USBCMD &= ~USBCMD_RUN;
 381
 382     sleep(HZ/20);
 383     REG_USBCMD |= USBCMD_CTRL_RESET;
 384     while (REG_USBCMD & USBCMD_CTRL_RESET);
 385
 386     /* Set to ULPI */
 387     REG_PORTSC1 = (REG_PORTSC1 & ~PORTSCX_PHY_TYPE_SEL) | PORTSCX_PTS_ULPI;
 388     sleep(HZ/10);
 389 #endif
 390
 391     /* Initialize all the signal objects once */
 392     int i;
 393     for(i=0;i<NUM_ENDPOINTS*2;i++) {
 394         wakeup_init(&transfer_completion_signal[i]);
 395     }
 396 }
 397
 398 /* manual: 32.14.1 Device Controller Initialization */
 399 void usb_drv_init(void)
 400 {
 401     REG_USBCMD &= ~USBCMD_RUN;
 402     sleep(HZ/20);
 403     REG_USBCMD |= USBCMD_CTRL_RESET;
 404     while (REG_USBCMD & USBCMD_CTRL_RESET);
 405
 406
 407     REG_USBMODE = USBMODE_CTRL_MODE_DEVICE;
 408
 409 #if CONFIG_CPU == IMX31L
 410     /* Set to ULPI */
 411     REG_PORTSC1 = (REG_PORTSC1 & ~PORTSCX_PHY_TYPE_SEL) | PORTSCX_PTS_ULPI;
 412 #endif
 413
 414 #ifndef USE_HIGH_SPEED
 415     /* Force device to full speed */
 416     /* See 32.9.5.9.2 */
 417     REG_PORTSC1 |= PORTSCX_PORT_FORCE_FULL_SPEED;
 418 #endif
 419
 420     init_control_queue_heads();
 421     memset(td_array, 0, sizeof td_array);
 422
 423     REG_ENDPOINTLISTADDR = (unsigned int)qh_array;
 424     REG_DEVICEADDR = 0;
 425
 426     /* enable USB interrupts */
 427     REG_USBINTR =
 428         USBINTR_INT_EN |
 429         USBINTR_ERR_INT_EN |
 430         USBINTR_PTC_DETECT_EN |
 431         USBINTR_RESET_EN |
 432         USBINTR_SYS_ERR_EN;
 433
 434 #if CONFIG_CPU == IMX31L
 435     avic_enable_int(USB_OTG, IRQ, 7, USB_OTG_HANDLER);
 436 #else
 437     /* enable USB IRQ in CPU */
 438     CPU_INT_EN = USB_MASK;
 439 #endif
 440
 441     /* go go go */
 442     REG_USBCMD |= USBCMD_RUN;
 443
 444
 445     logf("usb_drv_init() finished");
 446     logf("usb id %x", REG_ID);
 447     logf("usb dciversion %x", REG_DCIVERSION);
 448     logf("usb dccparams %x", REG_DCCPARAMS);
 449
 450     /* now a bus reset will occur. see bus_reset() */
 451 }
 452
 453 void usb_drv_exit(void)
 454 {
 455     /* disable interrupts */
 456     REG_USBINTR = 0;
 457
 458     /* stop usb controller */
 459     REG_USBCMD &= ~USBCMD_RUN;
 460
 461     /* TODO : is one of these needed to save power ?
 462     REG_PORTSC1 |= PORTSCX_PHY_LOW_POWER_SPD;
 463     REG_USBCMD |= USBCMD_CTRL_RESET;
 464     */
 465
 466 #if CONFIG_CPU == IMX31L
 467     avic_disable_int(USB_OTG);
 468 #else
 469     CPU_INT_CLR = USB_MASK;
 470 #endif
 471
 472     cancel_cpu_boost();
 473 }
 474
 475 #if CONFIG_CPU == IMX31L
 476 static void __attribute__((interrupt("IRQ"))) USB_OTG_HANDLER(void)
 477 #else
 478 void usb_drv_int(void)
 479 #endif
 480 {
 481     unsigned int status = REG_USBSTS;
 482
 483 #if 0
 484     if (status & USBSTS_INT) logf("int: usb ioc");
 485     if (status & USBSTS_ERR) logf("int: usb err");
 486     if (status & USBSTS_PORT_CHANGE) logf("int: portchange");
 487     if (status & USBSTS_RESET) logf("int: reset");
 488     if (status & USBSTS_SYS_ERR) logf("int: syserr");
 489 #endif
 490
 491     /* usb transaction interrupt */
 492     if (status & USBSTS_INT) {
 493         REG_USBSTS = USBSTS_INT;
 494
 495         /* a control packet? */
 496         if (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0) {
 497             control_received();
 498         }
 499
 500         if (REG_ENDPTCOMPLETE)
 501             transfer_completed();
 502     }
 503
 504     /* error interrupt */
 505     if (status & USBSTS_ERR) {
 506         REG_USBSTS = USBSTS_ERR;
 507         logf("usb error int");
 508     }
 509
 510     /* reset interrupt */
 511     if (status & USBSTS_RESET) {
 512         REG_USBSTS = USBSTS_RESET;
 513         bus_reset();
 514         usb_core_bus_reset(); /* tell mom */
 515     }
 516
 517     /* port change */
 518     if (status & USBSTS_PORT_CHANGE) {
 519         REG_USBSTS = USBSTS_PORT_CHANGE;
 520     }
 521 }
 522
 523 bool usb_drv_stalled(int endpoint,bool in)
 524 {
 525     if(in) {
 526         return ((REG_ENDPTCTRL(endpoint) & EPCTRL_TX_EP_STALL)!=0);
 527     }
 528     else {
 529         return ((REG_ENDPTCTRL(endpoint) & EPCTRL_RX_EP_STALL)!=0);
 530     }
 531
 532 }
 533 void usb_drv_stall(int endpoint, bool stall,bool in)
 534 {
 535     logf("%sstall %d", stall?"":"un", endpoint);
 536
 537     if(in) {
 538         if (stall) {
 539             REG_ENDPTCTRL(endpoint) |= EPCTRL_TX_EP_STALL;
 540         }
 541         else {
 542             REG_ENDPTCTRL(endpoint) &= ~EPCTRL_TX_EP_STALL;
 543         }
 544     }
 545     else {
 546         if (stall) {
 547             REG_ENDPTCTRL(endpoint) |= EPCTRL_RX_EP_STALL;
 548         }
 549         else {
 550             REG_ENDPTCTRL(endpoint) &= ~EPCTRL_RX_EP_STALL;
 551         }
 552     }
 553 }
 554
 555 int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
 556 {
 557     return prime_transfer(endpoint, ptr, length, true, false);
 558 }
 559
 560 int usb_drv_send(int endpoint, void* ptr, int length)
 561 {
 562     return prime_transfer(endpoint, ptr, length, true, true);
 563 }
 564
 565 int usb_drv_recv(int endpoint, void* ptr, int length)
 566 {
 567     //logf("usbrecv(%x, %d)", ptr, length);
 568     return prime_transfer(endpoint, ptr, length, false, false);
 569 }
 570
 571 void usb_drv_wait(int endpoint, bool send)
 572 {
 573     int pipe = endpoint * 2 + (send ? 1 : 0);
 574     struct queue_head* qh = &qh_array[pipe];
 575
 576     while (qh->dtd.size_ioc_sts & QH_STATUS_ACTIVE) {
 577         if (REG_USBSTS & USBSTS_RESET)
 578             break;
 579     }
 580 }
 581
 582 int usb_drv_port_speed(void)
 583 {
 584     return (REG_PORTSC1 & 0x08000000) ? 1 : 0;
 585 }
 586
 587 bool usb_drv_connected(void)
 588 {
 589     return ((REG_PORTSC1 & PORTSCX_CURRENT_CONNECT_STATUS) !=0);
 590 }
 591
 592 void usb_drv_set_address(int address)
 593 {
 594     REG_DEVICEADDR = address << USBDEVICEADDRESS_BIT_POS;
 595     init_bulk_queue_heads();
 596     init_endpoints();
 597 }
 598
 599 void usb_drv_reset_endpoint(int endpoint, bool send)
 600 {
 601     int pipe = endpoint * 2 + (send ? 1 : 0);
 602     unsigned int mask = pipe2mask[pipe];
 603     REG_ENDPTFLUSH = mask;
 604     while (REG_ENDPTFLUSH & mask);
 605 }
 606
 607 void usb_drv_set_test_mode(int mode)
 608 {
 609     switch(mode){
 610         case 0:
 611             REG_PORTSC1 &= ~PORTSCX_PORT_TEST_CTRL;
 612             break;
 613         case 1:
 614             REG_PORTSC1 |= PORTSCX_PTC_JSTATE;
 615             break;
 616         case 2:
 617             REG_PORTSC1 |= PORTSCX_PTC_KSTATE;
 618             break;
 619         case 3:
 620             REG_PORTSC1 |= PORTSCX_PTC_SE0NAK;
 621             break;
 622         case 4:
 623             REG_PORTSC1 |= PORTSCX_PTC_PACKET;
 624             break;
 625         case 5:
 626             REG_PORTSC1 |= PORTSCX_PTC_FORCE_EN;
 627             break;
 628     }
 629     REG_USBCMD &= ~USBCMD_RUN;
 630     sleep(HZ/20);
 631     REG_USBCMD |= USBCMD_CTRL_RESET;
 632     while (REG_USBCMD & USBCMD_CTRL_RESET);
 633     REG_USBCMD |= USBCMD_RUN;
 634 }
 635
 636 /*-------------------------------------------------------------------------*/
 637
 638 /* manual: 32.14.5.2 */
 639 static int prime_transfer(int endpoint, void* ptr, int len, bool send, bool wait)
 640 {
 641     int rc = 0;
 642     int pipe = endpoint * 2 + (send ? 1 : 0);
 643     unsigned int mask = pipe2mask[pipe];
 644     struct queue_head* qh = &qh_array[pipe];
 645     static long last_tick;
 646     struct transfer_descriptor* new_td;
 647
 648 /*
 649     if (send && endpoint > EP_CONTROL) {
 650         logf("usb: sent %d bytes", len);
 651     }
 652 */
 653     qh->status = 0;
 654     qh->length = 0;
 655     qh->wait   = wait;
 656
 657     new_td=&td_array[pipe];
 658     prepare_td(new_td, 0, ptr, len,pipe);
 659     //logf("starting ep %d %s",endpoint,send?"send":"receive");
 660
 661     qh->dtd.next_td_ptr = (unsigned int)new_td;
 662     qh->dtd.size_ioc_sts &= ~(QH_STATUS_HALT | QH_STATUS_ACTIVE);
 663
 664     REG_ENDPTPRIME |= mask;
 665
 666     if(endpoint == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
 667         /* 32.14.3.2.2 */
 668         logf("new setup arrived");
 669         rc = -4;
 670         goto pt_error;
 671     }
 672
 673     last_tick = current_tick;
 674     while ((REG_ENDPTPRIME & mask)) {
 675         if (REG_USBSTS & USBSTS_RESET) {
 676             rc = -1;
 677             goto pt_error;
 678         }
 679
 680         if (TIME_AFTER(current_tick, last_tick + HZ/4)) {
 681             logf("prime timeout");
 682             rc = -2;
 683             goto pt_error;
 684         }
 685     }
 686
 687     if (!(REG_ENDPTSTATUS & mask)) {
 688         logf("no prime! %d %d %x", endpoint, pipe, qh->dtd.size_ioc_sts & 0xff );
 689         rc = -3;
 690         goto pt_error;
 691     }
 692     if(endpoint == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
 693         /* 32.14.3.2.2 */
 694         logf("new setup arrived");
 695         rc = -4;
 696         goto pt_error;
 697     }
 698
 699     if (wait) {
 700         /* wait for transfer to finish */
 701         wakeup_wait(&transfer_completion_signal[pipe], TIMEOUT_BLOCK);
 702         if(qh->status!=0) {
 703             /* No need to cancel wait here since it was done and the signal
 704              * came. */
 705             return 5;
 706         }
 707         //logf("all tds done");
 708     }
 709
 710 pt_error:
 711     /* Error status must make sure an abandoned wakeup signal isn't left */
 712     if (rc < 0 && wait) {
 713         /* Cancel wait */
 714         qh->wait = 0;
 715         /* Make sure to remove any signal if interrupt fired before we zeroed
 716          * qh->wait. Could happen during a bus reset for example. */
 717         wakeup_wait(&transfer_completion_signal[pipe], TIMEOUT_NOBLOCK);
 718     }
 719
 720     return rc;
 721 }
 722
 723 void usb_drv_cancel_all_transfers(void)
 724 {
 725     int i;
 726     REG_ENDPTFLUSH = ~0;
 727     while (REG_ENDPTFLUSH);
 728
 729     memset(td_array, 0, sizeof td_array);
 730     for(i=0;i<NUM_ENDPOINTS*2;i++) {
 731         if(qh_array[i].wait) {
 732             qh_array[i].wait=0;
 733             qh_array[i].status=DTD_STATUS_HALTED;
 734             wakeup_signal(&transfer_completion_signal[i]);
 735         }
 736     }
 737 }
 738
 739 static void prepare_td(struct transfer_descriptor* td,
 740                        struct transfer_descriptor* previous_td,
 741                        void *ptr, int len,int pipe)
 742 {
 743     //logf("adding a td : %d",len);
 744     memset(td, 0, sizeof(struct transfer_descriptor));
 745     td->next_td_ptr = DTD_NEXT_TERMINATE;
 746     td->size_ioc_sts = (len<< DTD_LENGTH_BIT_POS) |
 747         DTD_STATUS_ACTIVE | DTD_IOC;
 748     td->buff_ptr0 = (unsigned int)ptr;
 749     td->buff_ptr1 = ((unsigned int)ptr & 0xfffff000) + 0x1000;
 750     td->buff_ptr2 = ((unsigned int)ptr & 0xfffff000) + 0x2000;
 751     td->buff_ptr3 = ((unsigned int)ptr & 0xfffff000) + 0x3000;
 752     td->buff_ptr4 = ((unsigned int)ptr & 0xfffff000) + 0x4000;
 753     td->reserved |= DTD_RESERVED_LENGTH_MASK & len;
 754     td->reserved |= DTD_RESERVED_IN_USE;
 755     td->reserved |= (pipe << DTD_RESERVED_PIPE_OFFSET);
 756
 757     if (previous_td != 0) {
 758         previous_td->next_td_ptr=(unsigned int)td;
 759     }
 760 }
 761
 762 static void control_received(void)
 763 {
 764     int i;
 765     /* copy setup data from packet */
 766     static unsigned int tmp[2];
 767     tmp[0] = qh_array[0].setup_buffer[0];
 768     tmp[1] = qh_array[0].setup_buffer[1];
 769
 770     /* acknowledge packet recieved */
 771     REG_ENDPTSETUPSTAT = EPSETUP_STATUS_EP0;
 772
 773     /* Stop pending control transfers */
 774     for(i=0;i<2;i++) {
 775         if(qh_array[i].wait) {
 776             qh_array[i].wait=0;
 777             qh_array[i].status=DTD_STATUS_HALTED;
 778             wakeup_signal(&transfer_completion_signal[i]);
 779         }
 780     }
 781
 782     usb_core_control_request((struct usb_ctrlrequest*)tmp);
 783 }
 784
 785 static void transfer_completed(void)
 786 {
 787     int ep;
 788     unsigned int mask = REG_ENDPTCOMPLETE;
 789     REG_ENDPTCOMPLETE = mask;
 790
 791     for (ep=0; ep<NUM_ENDPOINTS; ep++) {
 792         int dir;
 793         for (dir=0; dir<2; dir++) {
 794             int pipe = ep * 2 + dir;
 795             if (mask & pipe2mask[pipe]) {
 796                 struct queue_head* qh = &qh_array[pipe];
 797                 struct transfer_descriptor *td = &td_array[pipe];
 798
 799                 if(td->size_ioc_sts & DTD_STATUS_ACTIVE) {
 800                     /* TODO this shouldn't happen, but...*/
 801                     break;
 802                 }
 803                 if((td->size_ioc_sts & DTD_PACKET_SIZE) >> DTD_LENGTH_BIT_POS != 0 && dir==0) {
 804                     /* We got less data than we asked for. */
 805                 }
 806                 qh->length = (td->reserved & DTD_RESERVED_LENGTH_MASK) -
 807                     ((td->size_ioc_sts & DTD_PACKET_SIZE) >> DTD_LENGTH_BIT_POS);
 808                 if(td->size_ioc_sts & DTD_ERROR_MASK) {
 809                     logf("pipe %d err %x", pipe, td->size_ioc_sts & DTD_ERROR_MASK);
 810                     qh->status |= td->size_ioc_sts & DTD_ERROR_MASK;
 811                     /* TODO we need to handle this somehow. Flush the endpoint ? */
 812                 }
 813                 if(qh->wait) {
 814                     qh->wait=0;
 815                     wakeup_signal(&transfer_completion_signal[pipe]);
 816                 }
 817                 usb_core_transfer_complete(ep, dir, qh->status, qh->length);
 818             }
 819         }
 820     }
 821 }
 822
 823 /* manual: 32.14.2.1 Bus Reset */
 824 static void bus_reset(void)
 825 {
 826     int i;
 827     logf("usb bus_reset");
 828
 829     REG_DEVICEADDR = 0;
 830     REG_ENDPTSETUPSTAT = REG_ENDPTSETUPSTAT;
 831     REG_ENDPTCOMPLETE  = REG_ENDPTCOMPLETE;
 832
 833     for (i=0; i<100; i++) {
 834         if (!REG_ENDPTPRIME)
 835             break;
 836
 837         if (REG_USBSTS & USBSTS_RESET) {
 838             logf("usb: double reset");
 839             return;
 840         }
 841 #if CONFIG_CPU == IMX31L
 842         int x;
 843         for (x = 0; x < 30000; x++)
 844             asm volatile ("");
 845 #else
 846         udelay(100);
 847 #endif
 848     }
 849     if (REG_ENDPTPRIME) {
 850         logf("usb: short reset timeout");
 851     }
 852
 853     usb_drv_cancel_all_transfers();
 854
 855     if (!(REG_PORTSC1 & PORTSCX_PORT_RESET)) {
 856         logf("usb: slow reset!");
 857     }
 858 }
 859
 860 /* manual: 32.14.4.1 Queue Head Initialization */
 861 static void init_control_queue_heads(void)
 862 {
 863     memset(qh_array, 0, sizeof qh_array);
 864
 865     /*** control ***/
 866     qh_array[EP_CONTROL].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS | QH_IOS;
 867     qh_array[EP_CONTROL].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 868     qh_array[EP_CONTROL+1].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS;
 869     qh_array[EP_CONTROL+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 870 }
 871 /* manual: 32.14.4.1 Queue Head Initialization */
 872 static void init_bulk_queue_heads(void)
 873 {
 874     int tx_packetsize;
 875     int rx_packetsize;
 876     int i;
 877
 878     if (usb_drv_port_speed()) {
 879         rx_packetsize = 512;
 880         tx_packetsize = 512;
 881     }
 882     else {
 883         rx_packetsize = 64;
 884         tx_packetsize = 64;
 885     }
 886
 887     /*** bulk ***/
 888     for(i=1;i<NUM_ENDPOINTS;i++) {
 889         qh_array[i*2].max_pkt_length = rx_packetsize << QH_MAX_PKT_LEN_POS | QH_ZLT_SEL;
 890         qh_array[i*2].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 891         qh_array[i*2+1].max_pkt_length = tx_packetsize << QH_MAX_PKT_LEN_POS | QH_ZLT_SEL;
 892         qh_array[i*2+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 893     }
 894 }
 895
 896 static void init_endpoints(void)
 897 {
 898     int i;
 899     /* bulk */
 900     for(i=1;i<NUM_ENDPOINTS;i++) {
 901         REG_ENDPTCTRL(i) =
 902             EPCTRL_RX_DATA_TOGGLE_RST | EPCTRL_RX_ENABLE |
 903             EPCTRL_TX_DATA_TOGGLE_RST | EPCTRL_TX_ENABLE |
 904             (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT) |
 905             (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT);
 906     }
 907 }