firmware/target/arm/usb-s3c6400x.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2009 by Michael Sparmann
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "config.h"
  23 #include "usb.h"
  24
  25 #define OTGBASE 0x38800000
  26 #define PHYBASE 0x3C400000
  27 #include "usb-s3c6400x.h"
  28
  29 #include "cpu.h"
  30 #include "system.h"
  31 #include "kernel.h"
  32 #include "panic.h"
  33
  34 #ifdef HAVE_USBSTACK
  35 #include "usb_ch9.h"
  36 #include "usb_core.h"
  37 #include <inttypes.h>
  38 #include "power.h"
  39
  40 struct ep_type
  41 {
  42     bool active;
  43     bool busy;
  44     bool done;
  45     int rc;
  46     int size;
  47     struct wakeup complete;
  48 } ;
  49
  50 static struct ep_type endpoints[5];
  51 static struct usb_ctrlrequest ctrlreq USB_DEVBSS_ATTR;
  52
  53 int usb_drv_port_speed(void)
  54 {
  55     return (DSTS & 2) == 0 ? 1 : 0;
  56 }
  57
  58 void reset_endpoints(int reinit)
  59 {
  60     unsigned int i;
  61     for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
  62     {
  63         if (reinit) endpoints[i].active = false;
  64         endpoints[i].busy = false;
  65         endpoints[i].rc = -1;
  66         endpoints[i].done = true;
  67         wakeup_signal(&endpoints[i].complete);
  68     }
  69     DIEPCTL0 = 0x8800;  /* EP0 IN ACTIVE NEXT=1 */
  70     DOEPCTL0 = 0x8000;  /* EP0 OUT ACTIVE */
  71     DOEPTSIZ0 = 0x20080040;  /* EP0 OUT Transfer Size:
  72                                 64 Bytes, 1 Packet, 1 Setup Packet */
  73     DOEPDMA0 = (uint32_t)&ctrlreq;
  74     DOEPCTL0 |= 0x84000000;  /* EP0 OUT ENABLE CLEARNAK */
  75     if (reinit)
  76     {
  77         /* The size is getting set to zero, because we don't know
  78            whether we are Full Speed or High Speed at this stage */
  79         /* EP1 IN INACTIVE DATA0 SIZE=0 NEXT=3 */
  80         DIEPCTL1 = 0x10001800;
  81         /* EP2 OUT INACTIVE DATA0 SIZE=0 */
  82         DOEPCTL2 = 0x10000000;
  83         /* EP3 IN INACTIVE DATA0 SIZE=0 NEXT=0 */
  84         DIEPCTL3 = 0x10000000;
  85         /* EP4 OUT INACTIVE DATA0 SIZE=0 */
  86         DOEPCTL4 = 0x10000000;
  87     }
  88     else
  89     {
  90         /* INACTIVE DATA0 */
  91         DIEPCTL1 = (DIEPCTL1 & ~0x00008000) | 0x10000000;
  92         DOEPCTL2 = (DOEPCTL2 & ~0x00008000) | 0x10000000;
  93         DIEPCTL3 = (DIEPCTL3 & ~0x00008000) | 0x10000000;
  94         DOEPCTL4 = (DOEPCTL4 & ~0x00008000) | 0x10000000;
  95     }
  96     DAINTMSK = 0xFFFFFFFF;  /* Enable interrupts on all EPs */
  97 }
  98
  99 int usb_drv_request_endpoint(int type, int dir)
 100 {
 101     size_t ep;
 102     int ret = -1;
 103
 104     if (dir == USB_DIR_IN) ep = 1;
 105     else ep = 2;
 106
 107     while (ep < 5)
 108     {
 109         if (!endpoints[ep].active)
 110         {
 111             endpoints[ep].active = true;
 112             ret = ep | dir;
 113             uint32_t newbits = (type << 18) | 0x10000000;
 114             if (dir) DIEPCTL(ep) = (DIEPCTL(ep) & ~0x000C0000) | newbits;
 115             else DOEPCTL(ep) = (DOEPCTL(ep) & ~0x000C0000) | newbits;
 116             break;
 117         }
 118         ep += 2;
 119     }
 120
 121     return ret;
 122 }
 123
 124 void usb_drv_release_endpoint(int ep)
 125 {
 126     ep = ep & 0x7f;
 127
 128     if (ep < 1 || ep > USB_NUM_ENDPOINTS) return;
 129
 130     endpoints[ep].active = false;
 131 }
 132
 133 static void usb_reset(void)
 134 {
 135     volatile int i;
 136
 137     DCTL = 0x802;  /* Soft Disconnect */
 138
 139     OPHYPWR = 0;  /* PHY: Power up */
 140     ORSTCON = 1;  /* PHY: Assert Software Reset */
 141     for (i = 0; i < 50; i++);
 142     ORSTCON = 0;  /* PHY: Deassert Software Reset */
 143     OPHYCLK = 0;  /* PHY: 48MHz clock */
 144
 145     GRSTCTL = 1;  /* OTG: Assert Software Reset */
 146     while (GRSTCTL & 1);  /* Wait for OTG to ack reset */
 147     while (!(GRSTCTL & 0x80000000));  /* Wait for OTG AHB master idle */
 148
 149     GAHBCFG = 0x27;  /* OTG AHB config: Unmask ints, burst length 4, DMA on */
 150     GUSBCFG = 0x1408;  /* OTG: 16bit PHY and some reserved bits */
 151
 152     DCFG = 4;  /* Address 0 */
 153     DCTL = 0x800;  /* Soft Reconnect */
 154     DIEPMSK = 0x0D;  /* IN EP interrupt mask */
 155     DOEPMSK = 0x0D;  /* IN EP interrupt mask */
 156     GINTMSK = 0xC3000;  /* Interrupt mask: IN event, OUT event, bus reset */
 157
 158     reset_endpoints(1);
 159 }
 160
 161 /* IRQ handler */
 162 void INT_USB_FUNC(void)
 163 {
 164     int i;
 165     if (GINTSTS & 0x1000)  /* bus reset */
 166     {
 167         DCFG = 4;  /* Address 0 */
 168         reset_endpoints(1);
 169         usb_core_bus_reset();
 170     }
 171
 172     if (GINTSTS & 0x2000)  /* enumeration done, we now know the speed */
 173     {
 174         /* Set up the maximum packet sizes accordingly */
 175         uint32_t maxpacket = usb_drv_port_speed() ? 512 : 64;
 176         DIEPCTL1 = (DIEPCTL1 & ~0x000003FF) | maxpacket;
 177         DOEPCTL2 = (DOEPCTL2 & ~0x000003FF) | maxpacket;
 178         DIEPCTL3 = (DIEPCTL3 & ~0x000003FF) | maxpacket;
 179         DOEPCTL4 = (DOEPCTL4 & ~0x000003FF) | maxpacket;
 180     }
 181
 182     if (GINTSTS & 0x40000)  /* IN EP event */
 183         for (i = 0; i < 5; i ++)
 184             if (i != 2 && i != 4 && DIEPINT(i))
 185             {
 186                 if (DIEPINT(i) & 1)  /* Transfer completed */
 187                 {
 188                     invalidate_dcache();
 189                     int bytes = endpoints[i].size - (DIEPTSIZ(i) & 0x3FFFF);
 190                     if (endpoints[i].busy)
 191                     {
 192                         endpoints[i].busy = false;
 193                         endpoints[i].rc = 0;
 194                         endpoints[i].done = true;
 195                         usb_core_transfer_complete(i, USB_DIR_IN, 0, bytes);
 196                         wakeup_signal(&endpoints[i].complete);
 197                     }
 198                 }
 199                 if (DIEPINT(i) & 4)  /* AHB error */
 200                     panicf("USB: AHB error on IN EP%d", i);
 201                 if (DIEPINT(i) & 8)  /* Timeout */
 202                 {
 203                     if (endpoints[i].busy)
 204                     {
 205                         endpoints[i].busy = false;
 206                         endpoints[i].rc = 1;
 207                         endpoints[i].done = true;
 208                         wakeup_signal(&endpoints[i].complete);
 209                     }
 210                 }
 211                 DIEPINT(i) = DIEPINT(i);
 212             }
 213
 214     if (GINTSTS & 0x80000)  /* OUT EP event */
 215         for (i = 0; i < 5; i += 2)
 216             if (DOEPINT(i))
 217             {
 218                 if (DOEPINT(i) & 1)  /* Transfer completed */
 219                 {
 220                     invalidate_dcache();
 221                     int bytes = endpoints[i].size - (DOEPTSIZ(i) & 0x3FFFF);
 222                     if (endpoints[i].busy)
 223                     {
 224                         endpoints[i].busy = false;
 225                         endpoints[i].rc = 0;
 226                         endpoints[i].done = true;
 227                         usb_core_transfer_complete(i, USB_DIR_OUT, 0, bytes);
 228                         wakeup_signal(&endpoints[i].complete);
 229                     }
 230                 }
 231                 if (DOEPINT(i) & 4)  /* AHB error */
 232                     panicf("USB: AHB error on OUT EP%d", i);
 233                 if (DOEPINT(i) & 8)  /* SETUP phase done */
 234                 {
 235                     invalidate_dcache();
 236                     if (i == 0)
 237                     {
 238                         if (ctrlreq.bRequest == 5)
 239                         {
 240                             /* Already set the new address here,
 241                                before passing the packet to the core.
 242                                See below (usb_drv_set_address) for details. */
 243                             DCFG = (DCFG & ~0x7F0) | (ctrlreq.wValue << 4);
 244                         }
 245                         usb_core_control_request(&ctrlreq);
 246                     }
 247                     else panicf("USB: SETUP done on OUT EP%d!?", i);
 248                 }
 249                 /* Make sure EP0 OUT is set up to accept the next request */
 250                 if (!i)
 251                 {
 252                     DOEPTSIZ0 = 0x20080040;
 253                     DOEPDMA0 = (uint32_t)&ctrlreq;
 254                     DOEPCTL0 |= 0x84000000;
 255                 }
 256                 DOEPINT(i) = DOEPINT(i);
 257             }
 258
 259     GINTSTS = GINTSTS;
 260 }
 261
 262 void usb_drv_set_address(int address)
 263 {
 264     (void)address;
 265     /* Ignored intentionally, because the controller requires us to set the
 266        new address before sending the response for some reason. So we'll
 267        already set it when the control request arrives, before passing that
 268        into the USB core, which will then call this dummy function. */
 269 }
 270
 271 void ep_send(int ep, void *ptr, int length)
 272 {
 273     endpoints[ep].busy = true;
 274     endpoints[ep].size = length;
 275     DIEPCTL(ep) |= 0x8000;  /* EPx OUT ACTIVE */
 276     int blocksize = usb_drv_port_speed() ? 512 : 64;
 277     int packets = (length + blocksize - 1) / blocksize;
 278     if (!length)
 279     {
 280         DIEPTSIZ(ep) = 1 << 19;  /* one empty packet */
 281         DIEPDMA(ep) = 0x10000000;  /* dummy address */
 282     }
 283     else
 284     {
 285         DIEPTSIZ(ep) = length | (packets << 19);
 286         DIEPDMA(ep) = (uint32_t)ptr;
 287     }
 288     clean_dcache();
 289     DIEPCTL(ep) |= 0x84000000;  /* EPx OUT ENABLE CLEARNAK */
 290 }
 291
 292 void ep_recv(int ep, void *ptr, int length)
 293 {
 294     endpoints[ep].busy = true;
 295     endpoints[ep].size = length;
 296     DOEPCTL(ep) &= ~0x20000;  /* EPx UNSTALL */
 297     DOEPCTL(ep) |= 0x8000;  /* EPx OUT ACTIVE */
 298     int blocksize = usb_drv_port_speed() ? 512 : 64;
 299     int packets = (length + blocksize - 1) / blocksize;
 300     if (!length)
 301     {
 302         DOEPTSIZ(ep) = 1 << 19;  /* one empty packet */
 303         DOEPDMA(ep) = 0x10000000;  /* dummy address */
 304     }
 305     else
 306     {
 307         DOEPTSIZ(ep) = length | (packets << 19);
 308         DOEPDMA(ep) = (uint32_t)ptr;
 309     }
 310     clean_dcache();
 311     DOEPCTL(ep) |= 0x84000000;  /* EPx OUT ENABLE CLEARNAK */
 312 }
 313
 314 int usb_drv_send(int endpoint, void *ptr, int length)
 315 {
 316     endpoint &= 0x7f;
 317     endpoints[endpoint].done = false;
 318     ep_send(endpoint, ptr, length);
 319     while (!endpoints[endpoint].done && endpoints[endpoint].busy)
 320         wakeup_wait(&endpoints[endpoint].complete, TIMEOUT_BLOCK);
 321     return endpoints[endpoint].rc;
 322 }
 323
 324 int usb_drv_send_nonblocking(int endpoint, void *ptr, int length)
 325 {
 326     ep_send(endpoint & 0x7f, ptr, length);
 327     return 0;
 328 }
 329
 330 int usb_drv_recv(int endpoint, void* ptr, int length)
 331 {
 332     ep_recv(endpoint & 0x7f, ptr, length);
 333     return 0;
 334 }
 335
 336 void usb_drv_cancel_all_transfers(void)
 337 {
 338     int flags = disable_irq_save();
 339     reset_endpoints(0);
 340     restore_irq(flags);
 341 }
 342
 343 void usb_drv_set_test_mode(int mode)
 344 {
 345     (void)mode;
 346 }
 347
 348 bool usb_drv_stalled(int endpoint, bool in)
 349 {
 350     if (in) return DIEPCTL(endpoint) & 0x00200000 ? true : false;
 351     else return DOEPCTL(endpoint) & 0x00200000 ? true : false;
 352 }
 353
 354 void usb_drv_stall(int endpoint, bool stall, bool in)
 355 {
 356     if (in)
 357     {
 358         if (stall) DIEPCTL(endpoint) |= 0x00200000;
 359         else DIEPCTL(endpoint) &= ~0x00200000;
 360     }
 361     else
 362     {
 363         if (stall) DOEPCTL(endpoint) |= 0x00200000;
 364         else DOEPCTL(endpoint) &= ~0x00200000;
 365     }
 366 }
 367
 368 void usb_drv_init(void)
 369 {
 370     /* Enable USB clock */
 371     PWRCON &= ~0x4000;
 372     PWRCONEXT &= ~0x800;
 373     PCGCCTL = 0;
 374
 375     /* unmask irq */
 376     INTMSK |= INTMSK_USB_OTG;
 377
 378     /* reset the beast */
 379     usb_reset();
 380 }
 381
 382 void usb_drv_exit(void)
 383 {
 384     DCTL = 0x802;  /* Soft Disconnect */
 385
 386     ORSTCON = 1;  /* Put the PHY into reset (needed to get current down) */
 387     PCGCCTL = 1;  /* Shut down PHY clock */
 388     OPHYPWR = 0xF;  /* PHY: Power down */
 389
 390     PWRCON |= 0x4000;
 391     PWRCONEXT |= 0x800;
 392 }
 393
 394 void usb_init_device(void)
 395 {
 396     unsigned int i;
 397     for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
 398         wakeup_init(&endpoints[i].complete);
 399     usb_drv_exit();
 400 }
 401
 402 void usb_enable(bool on)
 403 {
 404     if (on) usb_core_init();
 405     else usb_core_exit();
 406 }
 407
 408 void usb_attach(void)
 409 {
 410     usb_enable(true);
 411 }
 412
 413 int usb_detect(void)
 414 {
 415     if (charger_inserted())
 416         return USB_INSERTED;
 417     return USB_EXTRACTED;
 418 }
 419
 420 #else
 421 void usb_init_device(void)
 422 {
 423     DCTL = 0x802;  /* Soft Disconnect */
 424
 425     ORSTCON = 1;  /* Put the PHY into reset (needed to get current down) */
 426     PCGCCTL = 1;  /* Shut down PHY clock */
 427     OPHYPWR = 0xF;  /* PHY: Power down */
 428
 429     PWRCON |= 0x4000;
 430     PWRCONEXT |= 0x800;
 431 }
 432
 433 void usb_enable(bool on)
 434 {
 435     (void)on;
 436 }
 437
 438 /* Always return false for now */
 439 int usb_detect(void)
 440 {
 441     return USB_EXTRACTED;
 442 }
 443 #endif