firmware/target/coldfire/pcm-coldfire.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 by Michael Sevakis
  11  * Copyright (C) 2005 by Linus Nielsen Feltzing
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22 #include <stdlib.h>
  23 #include "system.h"
  24 #include "kernel.h"
  25 #include "logf.h"
  26 #include "audio.h"
  27 #include "sound.h"
  28 #if defined(HAVE_SPDIF_REC) || defined(HAVE_SPDIF_OUT)
  29 #include "spdif.h"
  30 #endif
  31
  32 #define IIS_PLAY_DEFPARM ( (freq_ent[FPARM_CLOCKSEL] << 12) | \
  33                            (IIS_PLAY & (7 << 8)) | \
  34                            (4 << 2) )  /* 64 bit clocks / word clock */
  35 #define IIS_FIFO_RESET   (1 << 11)
  36 #define PDIR2_FIFO_RESET (1 << 9)
  37
  38 #if defined(IAUDIO_X5) || defined(IAUDIO_M5) || defined(IAUDIO_M3)
  39 #define IIS_PLAY         IIS1CONFIG
  40 #else
  41 #define IIS_PLAY         IIS2CONFIG
  42 #endif
  43
  44 #ifdef HAVE_SPDIF_OUT
  45 /* EBU TX auto sync, PDIR2 fifo auto sync, IIS1 fifo auto sync */
  46 #define AUDIOGLOB_DEFPARM   ((1 << 10) | (1 << 8) | (1 << 7))
  47 #else
  48 /* PDIR2 fifo auto sync, IIS1 fifo auto sync */
  49 #define AUDIOGLOB_DEFPARM   ((1 << 8) | (1 << 7))
  50 #endif
  51
  52 /** Sample rates **/
  53 #define PLLCR_SET_AUDIO_BITS_DEFPARM \
  54             ((freq_ent[FPARM_CLSEL] << 28) | (1 << 22))
  55
  56 #define FPARM_CLOCKSEL       0
  57 #define FPARM_CLSEL          1
  58
  59 /* SCLK = Fs * bit clocks per word
  60  * so SCLK should be Fs * 64
  61  *
  62  * CLOCKSEL sets SCLK freq based on Audio CLK
  63  * 0x0c SCLK = Audio CLK/2   88200 * 64 = 5644800 Hz
  64  * 0x06 SCLK = Audio CLK/4   44100 * 64 = 2822400 Hz
  65  * 0x04 SCLK = Audio CLK/8   22050 * 64 = 1411200 Hz
  66  * 0x02 SCLK = Audio CLK/16  11025 * 64 = 705600 Hz
  67  *
  68  * CLSEL sets MCLK1/2 DAC freq based on XTAL freq
  69  * 0x01 MCLK1/2 = XTAL freq
  70  * 0x02 MCLK1/2 = XTAL/2 freq
  71  *
  72  * Audio CLK can be XTAL freq or XTAL/2 freq  (bit22 in PLLCR)
  73  * we always set bit22 so Audio CLK is always XTAL freq
  74  */
  75
  76 #if CONFIG_CPU == MCF5249 && defined(HAVE_UDA1380)
  77 static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
  78 {
  79     [HW_FREQ_88] = { 0x0c, 0x01 },
  80     [HW_FREQ_44] = { 0x06, 0x01 },
  81     [HW_FREQ_22] = { 0x04, 0x02 },
  82     [HW_FREQ_11] = { 0x02, 0x02 },
  83 };
  84 #endif
  85
  86 #if CONFIG_CPU == MCF5249 && defined(HAVE_WM8750)
  87 /* We run codec in master mode.
  88  * Codec can reconstruct all frequencies
  89  * from single 11.2896 MHz master clock
  90  */
  91 static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
  92 {
  93     [HW_FREQ_88] = { 0x00, 0x01 },
  94     [HW_FREQ_44] = { 0x00, 0x01 },
  95     [HW_FREQ_22] = { 0x00, 0x01 },
  96     [HW_FREQ_11] = { 0x00, 0x01 },
  97 };
  98
  99 #endif
 100
 101 #if (CONFIG_CPU == MCF5250 || CONFIG_CPU == MCF5249) && defined(HAVE_TLV320)
 102 static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
 103 {
 104     [HW_FREQ_88] = { 0x0c, 0x01 },
 105     [HW_FREQ_44] = { 0x06, 0x01 },
 106     [HW_FREQ_22] = { 0x04, 0x01 },
 107     [HW_FREQ_11] = { 0x02, 0x02 },
 108 };
 109 #endif
 110
 111 static const unsigned char *freq_ent;
 112
 113 /* Lock status struct for playback and recording */
 114 struct dma_lock
 115 {
 116     int locked;
 117     unsigned long state;
 118 };
 119
 120 static void iis_play_reset(void)
 121 {
 122     or_l(IIS_FIFO_RESET, &IIS_PLAY);
 123     and_l(~IIS_FIFO_RESET, &IIS_PLAY);
 124     PDOR3 = 0;
 125 }
 126
 127 static bool is_playback_monitoring(void)
 128 {
 129     return (IIS_PLAY & (7 << 8)) == (3 << 8);
 130 }
 131
 132 static void iis_play_reset_if_playback(bool if_playback)
 133 {
 134     int level = set_irq_level(DMA_IRQ_LEVEL);
 135     if (is_playback_monitoring() == if_playback)
 136         iis_play_reset();
 137     restore_irq(level);
 138 }
 139
 140 /* apply audio settings */
 141 /* This clears the reset bit to enable monitoring immediately if monitoring
 142    recording sources or always if playback is in progress - we might be
 143    switching samplerates on the fly */
 144 void pcm_dma_apply_settings(void)
 145 {
 146     int level = set_irq_level(DMA_IRQ_LEVEL);
 147
 148     /* remember table entry */
 149     freq_ent = pcm_freq_parms[pcm_fsel];
 150
 151     /* Reprogramming bits 15-12 requires FIFO to be in a reset
 152        condition - Users Manual 17-8, Note 11 */
 153     or_l(IIS_FIFO_RESET, &IIS_PLAY);
 154     /* Important for TLV320 - this must happen in the correct order
 155        or starting recording will sound absolutely awful once in
 156        awhile - audiohw_set_frequency then coldfire_set_pllcr_audio_bits
 157      */
 158     IIS_PLAY = IIS_PLAY_DEFPARM | IIS_FIFO_RESET;
 159     restore_irq(level);
 160
 161     audiohw_set_frequency(pcm_fsel);
 162     coldfire_set_pllcr_audio_bits(PLLCR_SET_AUDIO_BITS_DEFPARM);
 163
 164     level = set_irq_level(DMA_IRQ_LEVEL);
 165
 166     IIS_PLAY = IIS_PLAY_DEFPARM;
 167
 168     if ((DCR0 & DMA_EEXT) != 0 && is_playback_monitoring())
 169         PDOR3 = 0; /* Kick FIFO out of reset by writing to it */
 170
 171     restore_irq(level);
 172 } /* pcm_dma_apply_settings */
 173
 174 void pcm_play_dma_init(void)
 175 {
 176     freq_ent = pcm_freq_parms[pcm_fsel];
 177
 178     AUDIOGLOB = AUDIOGLOB_DEFPARM;
 179     DIVR0     = 54; /* DMA0 is mapped into vector 54 in system.c */
 180     and_l(0xffffff00, &DMAROUTE);
 181     or_l(DMA0_REQ_AUDIO_1, &DMAROUTE);
 182     DMACONFIG = 1;  /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
 183     BCR0 = 0; /* No bytes waiting */
 184     ICR6 = (6 << 2); /* Enable interrupt at level 6, priority 0 */
 185
 186     /* Setup Coldfire I2S before initializing hardware or changing
 187        other settings. */
 188     or_l(IIS_FIFO_RESET, &IIS_PLAY);
 189     IIS_PLAY = IIS_PLAY_DEFPARM | IIS_FIFO_RESET;
 190     audio_set_output_source(AUDIO_SRC_PLAYBACK);
 191
 192     /* Initialize default register values. */
 193     audiohw_init();
 194
 195     audio_input_mux(AUDIO_SRC_PLAYBACK, SRCF_PLAYBACK);
 196
 197     audiohw_set_frequency(pcm_fsel);
 198     coldfire_set_pllcr_audio_bits(PLLCR_SET_AUDIO_BITS_DEFPARM);
 199
 200 #if defined(HAVE_SPDIF_REC) || defined(HAVE_SPDIF_OUT)
 201     spdif_init();
 202 #endif
 203 } /* pcm_play_dma_init */
 204
 205 void pcm_postinit(void)
 206 {
 207     audiohw_postinit();
 208     iis_play_reset();
 209 }
 210
 211 /** DMA **/
 212
 213 /****************************************************************************
 214  ** Playback DMA transfer
 215  **/
 216 /* For the locks, DMA interrupt must be disabled when manipulating the lock
 217    if the handler ever calls these - right now things are arranged so it
 218    doesn't */
 219 static struct dma_lock dma_play_lock =
 220 {
 221     .locked = 0,
 222     .state = (0 << 14)  /* bit 14 is DMA0 */
 223 };
 224
 225 void pcm_play_lock(void)
 226 {
 227     if (++dma_play_lock.locked == 1)
 228         or_l((1 << 14), &IMR);
 229 }
 230
 231 void pcm_play_unlock(void)
 232 {
 233     if (--dma_play_lock.locked == 0)
 234         and_l(~dma_play_lock.state, &IMR);
 235 }
 236
 237 /* Set up the DMA transfer that kicks in when the audio FIFO gets empty */
 238 void pcm_play_dma_start(const void *addr, size_t size)
 239 {
 240     /* Stop any DMA in progress */
 241     pcm_play_dma_stop();
 242
 243     /* Set up DMA transfer  */
 244     SAR0 = (unsigned long)addr;   /* Source address      */
 245     DAR0 = (unsigned long)&PDOR3; /* Destination address */
 246     BCR0 = (unsigned long)size;   /* Bytes to transfer   */
 247
 248     DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | DMA_SINC |
 249            DMA_SSIZE(DMA_SIZE_LINE) | DMA_START;
 250
 251     dma_play_lock.state = (1 << 14);
 252 } /* pcm_play_dma_start */
 253
 254 /* Stops the DMA transfer and interrupt */
 255 void pcm_play_dma_stop(void)
 256 {
 257     and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
 258     BCR0 = 0; /* No bytes remaining */
 259     DSR0 = 1; /* Clear interrupt, errors, stop transfer */
 260
 261     iis_play_reset_if_playback(true);
 262
 263     dma_play_lock.state = (0 << 14);
 264 } /* pcm_play_dma_stop */
 265
 266 void pcm_play_dma_pause(bool pause)
 267 {
 268     if (pause)
 269     {
 270         /* pause playback on current buffer */
 271         and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
 272         DSR0 = 1;                            /* stop channel */
 273         iis_play_reset_if_playback(true);
 274         dma_play_lock.state = (0 << 14);
 275     }
 276     else
 277     {
 278         /* restart playback on current buffer */
 279         iis_play_reset_if_playback(true);
 280         or_l(DMA_INT | DMA_EEXT | DMA_START, &DCR0); /* everything ON */
 281         dma_play_lock.state = (1 << 14);
 282     }
 283 } /* pcm_play_dma_pause */
 284
 285 size_t pcm_get_bytes_waiting(void)
 286 {
 287     return BCR0 & 0xffffff;
 288 } /* pcm_get_bytes_waiting */
 289
 290 /* DMA0 Interrupt is called when the DMA has finished transfering a chunk
 291    from the caller's buffer */
 292 void DMA0(void) __attribute__ ((interrupt_handler, section(".icode")));
 293 void DMA0(void)
 294 {
 295     unsigned long res = DSR0;
 296     void *start;
 297     size_t size;
 298
 299     and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
 300     DSR0 = 1; /* Clear interrupt and errors */
 301
 302     if (res & 0x70)
 303     {
 304         logf("DMA0 err: %02x", res);
 305 #if 0
 306         logf("  SAR0: %08x", SAR0);
 307         logf("  DAR0: %08x", DAR0);
 308         logf("  BCR0: %08x", BCR0);
 309         logf("  DCR0: %08x", DCR0);
 310 #endif
 311     }
 312
 313     /* Force stop on error */
 314     pcm_play_get_more_callback((res & 0x70) ? NULL : &start, &size);
 315
 316     if (size != 0)
 317     {
 318         SAR0 = (unsigned long)start;     /* Source address */
 319         BCR0 = size;                     /* Bytes to transfer */
 320         or_l(DMA_EEXT | DMA_INT, &DCR0); /* per request and int ON */
 321     }
 322     /* else inished playing */
 323 } /* DMA0 */
 324
 325 const void * pcm_play_dma_get_peak_buffer(int *count)
 326 {
 327     unsigned long addr, cnt;
 328
 329     /* Make sure interrupt doesn't change the second value after we read the
 330      * first value. */
 331     int level = set_irq_level(DMA_IRQ_LEVEL);
 332     addr = SAR0;
 333     cnt = BCR0;
 334     restore_irq(level);
 335
 336     *count = (cnt & 0xffffff) >> 2;
 337     return (void *)((addr + 2) & ~3);
 338 } /* pcm_play_dma_get_peak_buffer */
 339
 340 #ifdef HAVE_RECORDING
 341 /****************************************************************************
 342  ** Recording DMA transfer
 343  **/
 344 static struct dma_lock dma_rec_lock =
 345 {
 346     .locked = 0,
 347     .state = (0 << 15)  /* bit 15 is DMA1 */
 348 };
 349
 350 /* For the locks, DMA interrupt must be disabled when manipulating the lock
 351    if the handler ever calls these - right now things are arranged so it
 352    doesn't */
 353 void pcm_rec_lock(void)
 354 {
 355     if (++dma_rec_lock.locked == 1)
 356         or_l((1 << 15), &IMR);
 357 }
 358
 359 void pcm_rec_unlock(void)
 360 {
 361     if (--dma_rec_lock.locked == 0)
 362         and_l(~dma_rec_lock.state, &IMR);
 363 }
 364
 365 void pcm_rec_dma_start(void *addr, size_t size)
 366 {
 367     /* stop any DMA in progress */
 368     pcm_rec_dma_stop();
 369
 370     and_l(~PDIR2_FIFO_RESET, &DATAINCONTROL);
 371
 372     /* Start the DMA transfer.. */
 373 #ifdef HAVE_SPDIF_REC
 374     /* clear: ebu1cnew, valnogood, symbolerr, parityerr */
 375     INTERRUPTCLEAR = (1 << 25) | (1 << 24) | (1 << 23) | (1 << 22);
 376 #endif
 377
 378     SAR1 = (unsigned long)&PDIR2; /* Source address      */
 379     DAR1 = (unsigned long)addr;   /* Destination address */
 380     BCR1 = (unsigned long)size;   /* Bytes to transfer   */
 381
 382     DCR1 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | DMA_DINC |
 383            DMA_DSIZE(DMA_SIZE_LINE) | DMA_START;
 384
 385     dma_rec_lock.state = (1 << 15);
 386 } /* pcm_rec_dma_start */
 387
 388 void pcm_rec_dma_stop(void)
 389 {
 390     and_l(~(DMA_EEXT | DMA_INT), &DCR1); /* per request and int OFF */
 391     DSR1 = 1; /* Clear interrupt, errors, stop transfer */
 392     BCR1 = 0; /* No bytes received */
 393
 394     or_l(PDIR2_FIFO_RESET, &DATAINCONTROL);
 395
 396     iis_play_reset_if_playback(false);
 397
 398     dma_rec_lock.state = (0 << 15);
 399 } /* pcm_rec_dma_stop */
 400
 401 void pcm_rec_dma_init(void)
 402 {
 403     DIVR1     = 55; /* DMA1 is mapped into vector 55 in system.c */
 404     DMACONFIG = 1;  /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
 405     and_l(0xffff00ff, &DMAROUTE);
 406     or_l(DMA1_REQ_AUDIO_2, &DMAROUTE);
 407
 408     pcm_rec_dma_stop();
 409
 410     /* Enable interrupt at level 6, priority 1 */
 411     ICR7 = (6 << 2) | (1 << 0);
 412 } /* pcm_init_recording */
 413
 414 void pcm_rec_dma_close(void)
 415 {
 416     pcm_rec_dma_stop();
 417
 418     and_l(0xffff00ff, &DMAROUTE);
 419     ICR7 = 0x00;     /* Disable interrupt */
 420     dma_rec_lock.state = (0 << 15);
 421 } /* pcm_rec_dma_close */
 422
 423 /* DMA1 Interrupt is called when the DMA has finished transfering a chunk
 424    into the caller's buffer */
 425 void DMA1(void) __attribute__ ((interrupt_handler, section(".icode")));
 426 void DMA1(void)
 427 {
 428     unsigned long res = DSR1;
 429     int status = 0;
 430     void *start;
 431     size_t size;
 432
 433     and_l(~(DMA_EEXT | DMA_INT), &DCR1); /* per request and int OFF */
 434     DSR1 = 1;                            /* Clear interrupt and errors */
 435
 436     if (res & 0x70)
 437     {
 438         status = DMA_REC_ERROR_DMA;
 439         logf("DMA1 err: %02x", res);
 440 #if 0
 441         logf("  SAR1: %08x", SAR1);
 442         logf("  DAR1: %08x", DAR1);
 443         logf("  BCR1: %08x", BCR1);
 444         logf("  DCR1: %08x", DCR1);
 445 #endif
 446     }
 447 #ifdef HAVE_SPDIF_REC
 448     else if (DATAINCONTROL == 0xc038 &&
 449         (INTERRUPTSTAT & ((1 << 23) | (1 << 22))))
 450     {
 451         /* reason: symbolerr, parityerr.
 452          * Ignore valnogood since several sources don't set it properly. */
 453         /* clear: ebu1cnew, symbolerr, parityerr */
 454         INTERRUPTCLEAR = (1 << 25) | (1 << 23) | (1 << 22);
 455         status = DMA_REC_ERROR_SPDIF;
 456         logf("spdif err");
 457     }
 458 #endif
 459
 460     /* Inform PCM we have more data (or error) */
 461     pcm_rec_more_ready_callback(status, &start, &size);
 462
 463     if (size != 0)
 464     {
 465         DAR1 = (unsigned long)start;     /* Destination address */
 466         BCR1 = (unsigned long)size;      /* Bytes to transfer */
 467         or_l(DMA_EEXT | DMA_INT, &DCR1); /* per request and int ON */
 468     }
 469 } /* DMA1 */
 470
 471 const void * pcm_rec_dma_get_peak_buffer(void)
 472 {
 473     return (void *)(DAR1 & ~3);
 474 } /* pcm_rec_dma_get_peak_buffer */
 475 #endif