firmware/export/wm8978.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 by Michael Sevakis
  11  *
  12  * Header file for WM8978 codec
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23 #ifndef _WM8978_H
  24 #define _WM8978_H
  25
  26 #define VOLUME_MIN -900
  27 #define VOLUME_MAX 60
  28
  29 int tenthdb2master(int db);
  30 void audiohw_set_headphone_vol(int vol_l, int vol_r);
  31 void audiohw_set_recsrc(int source, bool recording);
  32
  33 void wmc_set(unsigned int reg, unsigned int bits);
  34 void wmc_clear(unsigned int reg, unsigned int bits);
  35
  36 #define WMC_I2C_ADDR 0x34
  37
  38 /* Registers */
  39 #define WMC_SOFTWARE_RESET              0x00
  40 #define WMC_POWER_MANAGEMENT1           0x01
  41 #define WMC_POWER_MANAGEMENT2           0x02
  42 #define WMC_POWER_MANAGEMENT3           0x03
  43 #define WMC_AUDIO_INTERFACE             0x04
  44 #define WMC_COMPANDING_CTRL             0x05
  45 #define WMC_CLOCK_GEN_CTRL              0x06
  46 #define WMC_ADDITIONAL_CTRL             0x07
  47 #define WMC_GPIO                        0x08
  48 #define WMC_JACK_DETECT_CONTROL1        0x09
  49 #define WMC_DAC_CONTROL                 0x0a
  50 #define WMC_LEFT_DAC_DIGITAL_VOL        0x0b
  51 #define WMC_RIGHT_DAC_DIGITAL_VOL       0x0c
  52 #define WMC_JACK_DETECT_CONTROL2        0x0d
  53 #define WMC_ADC_CONTROL                 0x0e
  54 #define WMC_LEFT_ADC_DIGITAL_VOL        0x0f
  55 #define WMC_RIGHT_ADC_DIGITAL_VOL       0x10
  56 #define WMC_EQ1_LOW_SHELF               0x12
  57 #define WMC_EQ2_PEAK1                   0x13
  58 #define WMC_EQ3_PEAK2                   0x14
  59 #define WMC_EQ4_PEAK3                   0x15
  60 #define WMC_EQ5_HIGH_SHELF              0x16
  61 #define WMC_DAC_LIMITER1                0x18
  62 #define WMC_DAC_LIMITER2                0x19
  63 #define WMC_NOTCH_FILTER1               0x1b
  64 #define WMC_NOTCH_FILTER2               0x1c
  65 #define WMC_NOTCH_FILTER3               0x1d
  66 #define WMC_NOTCH_FILTER4               0x1e
  67 #define WMC_ALC_CONTROL1                0x20
  68 #define WMC_ALC_CONTROL2                0x21
  69 #define WMC_ALC_CONTROL3                0x22
  70 #define WMC_NOISE_GATE                  0x23
  71 #define WMC_PLL_N                       0x24
  72 #define WMC_PLL_K1                      0x25
  73 #define WMC_PLL_K2                      0x26
  74 #define WMC_PLL_K3                      0x27
  75 #define WMC_3D_CONTROL                  0x29
  76 #define WMC_BEEP_CONTROL                0x2b
  77 #define WMC_INPUT_CTRL                  0x2c
  78 #define WMC_LEFT_INP_PGA_GAIN_CTRL      0x2d
  79 #define WMC_RIGHT_INP_PGA_GAIN_CTRL     0x2e
  80 #define WMC_LEFT_ADC_BOOST_CTRL         0x2f
  81 #define WMC_RIGHT_ADC_BOOST_CTRL        0x30
  82 #define WMC_OUTPUT_CTRL                 0x31
  83 #define WMC_LEFT_MIXER_CTRL             0x32
  84 #define WMC_RIGHT_MIXER_CTRL            0x33
  85 #define WMC_LOUT1_HP_VOLUME_CTRL        0x34
  86 #define WMC_ROUT1_HP_VOLUME_CTRL        0x35
  87 #define WMC_LOUT2_SPK_VOLUME_CTRL       0x36
  88 #define WMC_ROUT2_SPK_VOLUME_CTRL       0x37
  89 #define WMC_OUT3_MIXER_CTRL             0x38
  90 #define WMC_OUT4_MONO_MIXER_CTRL        0x39
  91 #define WMC_NUM_REGISTERS               0x3a
  92
  93 /* Register bitmasks */
  94
  95 /* Volume update bit for volume registers */
  96 #define WMC_VU                          (1 << 8)
  97
  98 /* Zero-crossing bit for volume registers */
  99 #define WMC_ZC                          (1 << 7)
 100
 101 /* Mute bit for volume registers */
 102 #define WMC_MUTE                        (1 << 6)
 103
 104 /* Volume masks and macros for digital volumes */
 105 #define WMC_DVOL                        0xff
 106
 107 /* Volums masks and macros for analogue volumes */
 108 #define WMC_AVOL                        0x3f
 109
 110 /* WMC_SOFTWARE_RESET (0x00) */
 111 #define WMC_RESET
 112     /* Write any value */
 113
 114 /* WMC_POWER_MANAGEMENT1 (0x01) */
 115 #define WMC_BUFDCOMPEN                  (1 << 8)
 116 #define WMC_OUT4MIXEN                   (1 << 7)
 117 #define WMC_OUT3MIXEN                   (1 << 6)
 118 #define WMC_PLLEN                       (1 << 5)
 119 #define WMC_MICBEN                      (1 << 4)
 120 #define WMC_BIASEN                      (1 << 3)
 121 #define WMC_BUFIOEN                     (1 << 2)
 122 #define WMC_VMIDSEL                     (3 << 0)
 123     #define WMC_VMIDSEL_OFF             (0 << 0)
 124     #define WMC_VMIDSEL_75K             (1 << 0)
 125     #define WMC_VMIDSEL_300K            (2 << 0)
 126     #define WMC_VMIDSEL_5K              (3 << 0)
 127
 128 /* WMC_POWER_MANAGEMENT2 (0x02) */
 129 #define WMC_ROUT1EN                     (1 << 8)
 130 #define WMC_LOUT1EN                     (1 << 7)
 131 #define WMC_SLEEP                       (1 << 6)
 132 #define WMC_BOOSTENR                    (1 << 5)
 133 #define WMC_BOOSTENL                    (1 << 4)
 134 #define WMC_INPPGAENR                   (1 << 3)
 135 #define WMC_INPPGAENL                   (1 << 2)
 136 #define WMC_ADCENR                      (1 << 1)
 137 #define WMC_ADCENL                      (1 << 0)
 138
 139 /* WMC_POWER_MANAGEMENT3 (0x03) */
 140 #define WMC_OUT4EN                      (1 << 8)
 141 #define WMC_OUT3EN                      (1 << 7)
 142 #define WMC_LOUT2EN                     (1 << 6)
 143 #define WMC_ROUT2EN                     (1 << 5)
 144 #define WMC_RMIXEN                      (1 << 3)
 145 #define WMC_LMIXEN                      (1 << 2)
 146 #define WMC_DACENR                      (1 << 1)
 147 #define WMC_DACENL                      (1 << 0)
 148
 149 /* WMC_AUDIO_INTERFACE (0x04) */
 150 #define WMC_BCP                         (1 << 8)
 151 #define WMC_LRP                         (1 << 7)
 152 #define WMC_WL                          (3 << 5)
 153     #define WMC_WL_16                   (0 << 5)
 154     #define WMC_WL_20                   (1 << 5)
 155     #define WMC_WL_24                   (2 << 5)
 156     #define WMC_WL_32                   (3 << 5)
 157 #define WMC_FMT                         (3 << 3)
 158     #define WMC_FMT_RJUST               (0 << 3)
 159     #define WMC_FMT_LJUST               (1 << 3)
 160     #define WMC_FMT_I2S                 (2 << 3)
 161     #define WMC_FMT_DSP_PCM             (3 << 3)
 162 #define WMC_DACLRSWAP                   (1 << 2)
 163 #define WMC_ADCLRSWAP                   (1 << 1)
 164 #define WMC_MONO                        (1 << 0)
 165
 166 /* WMC_COMPANDING_CTRL (0x05) */
 167 #define WMC_WL8                         (1 << 5)
 168 #define WMC_DAC_COMP                    (3 << 3)
 169     #define WMC_DAC_COMP_OFF            (0 << 3)
 170     #define WMC_DAC_COMP_U_LAW          (2 << 3)
 171     #define WMC_DAC_COMP_A_LAW          (3 << 3)
 172 #define WMC_ADC_COMP                    (3 << 1)
 173     #define WMC_ADC_COMP_OFF            (0 << 1)
 174     #define WMC_ADC_COMP_U_LAW          (2 << 1)
 175     #define WMC_ADC_COMP_A_LAW          (3 << 1)
 176 #define WMC_LOOPBACK                    (1 << 0)
 177
 178 /* WMC_CLOCK_GEN_CTRL (0x06) */
 179 #define WMC_CLKSEL                      (1 << 8)
 180 #define WMC_MCLKDIV                     (7 << 5)
 181     #define WMC_MCLKDIV_1               (0 << 5)
 182     #define WMC_MCLKDIV_1_5             (1 << 5)
 183     #define WMC_MCLKDIV_2               (2 << 5)
 184     #define WMC_MCLKDIV_3               (3 << 5)
 185     #define WMC_MCLKDIV_4               (4 << 5)
 186     #define WMC_MCLKDIV_6               (5 << 5)
 187     #define WMC_MCLKDIV_8               (6 << 5)
 188     #define WMC_MCLKDIV_12              (7 << 5)
 189 #define WMC_BCLKDIV                     (7 << 2)
 190     #define WMC_BCLKDIV_1               (0 << 2)
 191     #define WMC_BCLKDIV_2               (1 << 2)
 192     #define WMC_BCLKDIV_4               (2 << 2)
 193     #define WMC_BCLKDIV_8               (3 << 2)
 194     #define WMC_BCLKDIV_16              (4 << 2)
 195     #define WMC_BCLKDIV_32              (5 << 2)
 196 #define WMC_MS                          (1 << 0)
 197
 198 /* WMC_ADDITIONAL_CTRL (0x07) */
 199 /* This configure the digital filter coefficients - pick the closest
 200  * to what's really being used (greater than or equal). */
 201 #define WMC_SR                          (7 << 1)
 202 #define WMC_SR_48KHZ                    (0 << 1)
 203 #define WMC_SR_32KHZ                    (1 << 1)
 204 #define WMC_SR_24KHZ                    (2 << 1)
 205 #define WMC_SR_16KHZ                    (3 << 1)
 206 #define WMC_SR_12KHZ                    (4 << 1)
 207 #define WMC_SR_8KHZ                     (5 << 1)
 208 /* 110-111=reserved */
 209 #define WMC_SLOWCLKEN                   (1 << 0)
 210
 211 /* WMC_GPIO (0x08) */
 212 #define WMC_OPCLKDIV                    (3 << 4)
 213     #define WMC_OPCLKDIV_1              (0 << 4)
 214     #define WMC_OPCLKDIV_2              (1 << 4)
 215     #define WMC_OPCLKDIV_3              (2 << 4)
 216     #define WMC_OPCLKDIV_4              (3 << 4)
 217 #define WMC_GPIO1POL                    (1 << 3)
 218 #define WMC_GPIO1SEL                    (7 << 0)
 219     #define WMC_GPIO1SEL_TEMP_OK        (2 << 0)
 220     #define WMC_GPIO1SEL_AMUTE_ACTIVE   (3 << 0)
 221     #define WMC_GPIO1SEL_PLL_CLK_OP     (4 << 0)
 222     #define WMC_GPIO1SEL_PLL_LOCK       (5 << 0)
 223     #define WMC_GPIO1SEL_LOGIC_1        (6 << 0)
 224     #define WMC_GPIO1SEL_LOGIC_0        (7 << 0)
 225
 226 /* WMC_JACK_DETECT_CONTROL1 (0x09) */
 227 #define WMC_JD_VMID                     (3 << 7)
 228     #define WMC_JD_VMID_EN_0            (1 << 7)
 229     #define WMC_JD_VMID_EN_1            (2 << 7)
 230 #define WMC_JD_EN                       (1 << 6)
 231 #define WMC_JD_SEL                      (3 << 4)
 232     #define WMC_JD_SEL_GPIO1            (0 << 4)
 233     #define WMC_JD_SEL_GPIO2            (1 << 4)
 234     #define WMC_JD_SEL_GPIO3            (2 << 4)
 235
 236 /* WMC_DAC_CONTROL (0x0a) */
 237 #define WMC_SOFT_MUTE                   (1 << 6)
 238 #define WMC_DACOSR_128                  (1 << 3)
 239 #define WMC_AMUTE                       (1 << 2)
 240 #define WMC_DACPOLR                     (1 << 1)
 241 #define WMC_DACPOLL                     (1 << 0)
 242
 243 /* WMC_LEFT_DAC_DIGITAL_VOL (0x0b) */
 244 /* WMC_RIGHT_DAC_DIGITAL_VOL (0x0c) */
 245     /* 00000000=mute, 00000001=-127dB...(0.5dB steps)...11111111=0dB */
 246     /* Use WMC_DVOL* macros */
 247
 248 /* WMC_JACK_DETECT_CONTROL2 (0x0d) */
 249 #define WMC_JD_EN1                      (0xf << 4)
 250     #define WMC_OUT1_EN1                (1 << 4)
 251     #define WMC_OUT2_EN1                (2 << 4)
 252     #define WMC_OUT3_EN1                (4 << 4)
 253     #define WMC_OUT4_EN1                (8 << 4)
 254 #define WMC_JD_EN0                      (0xf << 0)
 255     #define WMC_OUT1_EN0                (1 << 0)
 256     #define WMC_OUT2_EN0                (2 << 0)
 257     #define WMC_OUT3_EN0                (4 << 0)
 258     #define WMC_OUT4_EN0                (8 << 0)
 259
 260 /* WMC_ADC_CONTROL (0x0e) */
 261 #define WMC_HPFEN                       (1 << 8)
 262 #define WMC_HPFAPP                      (1 << 7)
 263 #define WMC_HPFCUT                      (7 << 4)
 264 #define WMC_ADCOSR                      (1 << 3)
 265 #define WMC_ADCRPOL                     (1 << 1)
 266 #define WMC_ADCLPOL                     (1 << 0)
 267
 268 /* WMC_LEFT_ADC_DIGITAL_VOL (0x0f) */
 269 /* WMC_RIGHT_ADC_DITIGAL_VOL (0x10) */
 270     /* 0.5dB steps: Mute:0x00, -127dB:0x01...0dB:0xff */
 271     /*Use WMC_DVOL* macros */
 272
 273 /* Gain */
 274 #define WMC_EQG                         (0x1f << 0)
 275
 276 /* Cutoff/Center */
 277 #define WMC_EQC                         (0x3 << 5)
 278 #define WMC_EQC_POS                     (5)
 279
 280 /* Bandwidth */
 281 #define WMC_EQBW                        (1 << 8)
 282
 283 /* WMC_EQ1_LOW_SHELF (0x12) */
 284 #define WMC_EQ3DMODE                    (1 << 8)
 285     #define WMC_EQ1C_80HZ               (0 << 5) /* 80Hz */
 286     #define WMC_EQ1C_105HZ              (1 << 5) /* 105Hz */
 287     #define WMC_EQ1C_135HZ              (2 << 5) /* 135Hz */
 288     #define WMC_EQ1C_175HZ              (3 << 5) /* 175Hz */
 289     /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, 11001-11111=reserved */
 290
 291 /* WMC_EQ2_PEAK1 (0x13) */
 292     #define WMC_EQ2C_230HZ              (0 << 5) /* 230Hz */
 293     #define WMC_EQ2C_300HZ              (1 << 5) /* 300Hz */
 294     #define WMC_EQ2C_385HZ              (2 << 5) /* 385Hz */
 295     #define WMC_EQ2C_500HZ              (3 << 5) /* 500Hz */
 296     /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
 297        11001-11111=reserved */
 298
 299 /* WMC_EQ3_PEAK2 (0x14) */
 300     #define WMC_EQ3C_650HZ              (0 << 5) /* 650Hz */
 301     #define WMC_EQ3C_850HZ              (1 << 5) /* 850Hz */
 302     #define WMC_EQ3C_1_1KHZ             (2 << 5) /* 1.1kHz */
 303     #define WMC_EQ3C_1_4KHZ             (3 << 5) /* 1.4kHz */
 304     /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
 305        11001-11111=reserved */
 306
 307 /* WMC_EQ4_PEAK3 (0x15) */
 308     #define WMC_EQ4C_1_8KHZ             (0 << 5) /* 1.8kHz */
 309     #define WMC_EQ4C_2_4KHZ             (1 << 5) /* 2.4kHz */
 310     #define WMC_EQ4C_3_2KHZ             (2 << 5) /* 3.2kHz */
 311     #define WMC_EQ4C_4_1KHZ             (3 << 5) /* 4.1kHz */
 312     /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
 313        11001-11111=reserved */
 314
 315 /* WMC_EQ5_HIGH_SHELF (0x16) */
 316     #define WMC_EQ5C_5_3KHZ             (0 << 5) /* 5.3kHz */
 317     #define WMC_EQ5C_6_9KHZ             (1 << 5) /* 6.9kHz */
 318     #define WMC_EQ5C_9KHZ               (2 << 5) /* 9.0kHz */
 319     #define WMC_EQ5C_11_7KHZ            (3 << 5) /* 11.7kHz */
 320     /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
 321        11001-11111=reserved */
 322
 323 /* WMC_DAC_LIMITER1 (0x18) */
 324 #define WMC_LIMEN                       (1 << 8)
 325     /* 0000=750uS, 0001=1.5mS...(x2 each step)...1010-1111=768mS */
 326 #define WMC_LIMDCY                      (0xf << 4)
 327 #define WMC_LIMDCY_POS                  (4)
 328     /* 0000=94uS, 0001=188uS...(x2 each step)...1011-1111=192mS */
 329 #define WMC_LIMATK                      (0xf << 0)
 330
 331 /* WMC_DAC_LIMITER2 (0x19) */
 332     /* 000=-1dB, 001=-2dB...(-1dB steps)...101-111:-6dB */
 333 #define WMC_LIMLVL                      (7 << 4)
 334 #define WMC_LIMLVL_POS                  (4)
 335     /* 0000=0dB, 0001=+1dB...1100=+12dB, 1101-1111=reserved */
 336 #define WMC_LIMBOOST                    (0xf << 0)
 337
 338 /* Generic notch filter bits and macros */
 339 #define WMC_NFU                         (1 << 8)
 340 #define WMC_NFA                         (0x7f << 0)
 341
 342 /* WMC_NOTCH_FILTER1 (0x1b) */
 343 #define WMC_NFEN                        (1 << 7)
 344 /* WMC_NOTCH_FILTER2 (0x1c) */
 345 /* WMC_NOTCH_FILTER3 (0x1d) */
 346 /* WMC_NOTCH_FILTER4 (0x1e) */
 347
 348 /* WMC_ALC_CONTROL1 (0x20) */
 349 #define WMC_ALCSEL                      (3 << 7)
 350     #define WMC_ALCSEL_OFF              (0 << 7)
 351     #define WMC_ALCSEL_RIGHT_ONLY       (1 << 7)
 352     #define WMC_ALCSEL_LEFT_ONLY        (2 << 7)
 353     #define WMC_ALCSEL_BOTH_ON          (3 << 7)
 354     /* 000=-6.75dB, 001=-0.75dB...(6dB steps)...111=+35.25dB */
 355 #define WMC_ALCMAXGAIN                  (7 << 3)
 356 #define WMC_ALCMAXGAIN_POS              (3)
 357     /* 000:-12dB...(6dB steps)...111:+30dB */
 358 #define WMC_ALCMINGAIN                  (7 << 0)
 359
 360 /* WMC_ALC_CONTROL2 (0x21) */
 361     /* 0000=0ms, 0001=2.67ms, 0010=5.33ms...
 362        (2x with every step)...43.691s */
 363 #define WMC_ALCHLD                      (0xf << 4)
 364 #define WMC_ALCHLD_POS                  (4)
 365     /* 1111:-1.5dBFS, 1110:-1.5dBFS, 1101:-3dBFS, 1100:-4.5dBFS...
 366        (-1.5dB steps)...0001:-21dBFS, 0000:-22.5dBFS */
 367 #define WMC_ALCLVL                      (0xf << 0)
 368
 369 /* WMC_ALC_CONTROL3 (0x22) */
 370 #define WMC_ALCMODE                     (1 << 8)
 371 #define WMC_ALCDCY                      (0xf << 4)
 372 #define WMC_ALCATK                      (0xf << 0)
 373
 374 /* WMC_NOISE_GATE (0x23) */
 375 #define WMC_NGEN                        (1 << 3)
 376     /* 000=-39dB, 001=-45dB, 010=-51dB...(6dB steps)...111=-81dB */
 377 #define WMC_NGTH                        (7 << 0)
 378
 379 /* WMC_PLL_N (0x24) */
 380 #define WMC_PLL_PRESCALE                (1 << 4)
 381 #define WMC_PLLN                        (0xf << 0)
 382
 383 /* WMC_PLL_K1 (0x25) */
 384 #define WMC_PLLK_23_18                  (0x3f << 0)
 385
 386 /* WMC_PLL_K2 (0x26) */
 387 #define WMC_PLLK_17_9                   (0x1ff << 0)
 388
 389 /* WMC_PLL_K3 (0x27) */
 390 #define WMC_PLLK_8_0                    (0x1ff << 0)
 391
 392 /* WMC_3D_CONTROL (0x29) */
 393     /* 0000: 0%, 0001: 6.67%...1110: 93.3%, 1111: 100% */
 394 #define WMC_DEPTH3D                     (0xf << 0)
 395
 396 /* WMC_BEEP_CONTROL (0x2b) */
 397 #define WMC_MUTERPGA2INV                (1 << 5)
 398 #define WMC_INVROUT2                    (1 << 4)
 399     /* 000=-15dB, 001=-12dB...111=+6dB */
 400 #define WMC_BEEPVOL                     (7 << 1)
 401 #define WMC_BEEPVOL_POS                 (1)
 402 #define WMC_BEEPEN                      (1 << 0)
 403
 404 /* WMC_INPUT_CTRL (0x2c) */
 405 #define WMC_MBVSEL                      (1 << 8)
 406 #define WMC_R2_2INPPGA                  (1 << 6)
 407 #define WMC_RIN2INPPGA                  (1 << 5)
 408 #define WMC_RIP2INPPGA                  (1 << 4)
 409 #define WMC_L2_2INPPGA                  (1 << 2)
 410 #define WMC_LIN2INPPGA                  (1 << 1)
 411 #define WMC_LIP2INPPGA                  (1 << 0)
 412
 413 /* WMC_LEFT_INP_PGA_GAIN_CTRL (0x2d) */
 414     /* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */
 415     /* Uses WMC_AVOL* macros */
 416
 417 /* WMC_RIGHT_INP_PGA_GAIN_CTRL (0x2e) */
 418     /* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */
 419     /* Uses WMC_AVOL* macros */
 420
 421 /* WMC_LEFT_ADC_BOOST_CTRL (0x2f) */
 422 #define WMC_PGABOOSTL                    (1 << 8)
 423     /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
 424 #define WMC_L2_2BOOSTVOL                 (7 << 4)
 425 #define WMC_L2_2BOOSTVOL_POS             (4)
 426     /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
 427 #define WMC_AUXL2BOOSTVOL                (7 << 0)
 428
 429 /* WMC_RIGHT_ADC_BOOST_CTRL (0x30) */
 430 #define WMC_PGABOOSTR                    (1 << 8)
 431     /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
 432 #define WMC_R2_2BOOSTVOL                 (7 << 4)
 433 #define WMC_R2_2BOOSTVOL_POS             (4)
 434     /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
 435 #define WMC_AUXR2BOOSTVOL                (7 << 0)
 436
 437 /* WMC_OUTPUT_CTRL (0x31) */
 438 #define WMC_DACL2RMIX                    (1 << 6)
 439 #define WMC_DACR2LMIX                    (1 << 5)
 440 #define WMC_OUT4BOOST                    (1 << 4)
 441 #define WMC_OUT3BOOST                    (1 << 3)
 442 #define WMC_SPKBOOST                     (1 << 2)
 443 #define WMC_TSDEN                        (1 << 1)
 444 #define WMC_VROI                         (1 << 0)
 445
 446 /* WMC_LEFT_MIXER_CTRL (0x32) */
 447     /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
 448 #define WMC_AUXLMIXVOL                   (7 << 6)
 449 #define WMC_AUXLMIXVOL_POS               (6)
 450 #define WMC_AUXL2LMIX                    (1 << 5)
 451     /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
 452 #define WMC_BYPLMIXVOL                   (7 << 2)
 453 #define WMC_BYPLMIXVOL_POS               (2)
 454 #define WMC_BYPL2LMIX                    (1 << 1)
 455 #define WMC_DACL2LMIX                    (1 << 0)
 456
 457 /* WMC_RIGHT_MIXER_CTRL (0x33) */
 458     /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
 459 #define WMC_AUXRMIXVOL                   (7 << 6)
 460 #define WMC_AUXRMIXVOL_POS               (6)
 461 #define WMC_AUXR2RMIX                    (1 << 5)
 462     /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
 463 #define WMC_BYPRMIXVOL                   (7 << 2)
 464 #define WMC_BYPRMIXVOL_POS               (2)
 465 #define WMC_BYPR2RMIX                    (1 << 1)
 466 #define WMC_DACR2RMIX                    (1 << 0)
 467
 468 /* WMC_LOUT1_HP_VOLUME_CTRL (0x34) */
 469 /* WMC_ROUT1_HP_VOLUME_CTRL (0x35) */
 470 /* WMC_LOUT2_SPK_VOLUME_CTRL (0x36) */
 471 /* WMC_ROUT2_SPK_VOLUME_CTRL (0x37) */
 472     /* 000000=-57dB...111001=0dB...111111=+6dB */
 473     /* Uses WMC_AVOL* macros */
 474
 475 /* WMC_OUT3_MIXER_CTRL (0x38) */
 476 #define WMC_OUT42OUT3                    (1 << 3)
 477 #define WMC_BYPL2OUT3                    (1 << 2)
 478 #define WMC_LMIX2OUT3                    (1 << 1)
 479 #define WMC_LDAC2OUT3                    (1 << 0)
 480
 481 /* WMC_OUT4_MONO_MIXER_CTRL (0x39) */
 482 #define WMC_HALFSIG                      (1 << 5)
 483 #define WMC_LMIX2OUT4                    (1 << 4)
 484 #define WMC_LDAC2OUT4                    (1 << 3)
 485 #define WMC_BYPR2OUT4                    (1 << 2)
 486 #define WMC_RMIX2OUT4                    (1 << 1)
 487 #define WMC_RDAC2OUT4                    (1 << 0)
 488
 489 #endif /* _WM8978_H */