firmware/drivers/adc.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Linus Nielsen Feltzing
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 #include "config.h"
  20 #include "cpu.h"
  21 #include "kernel.h"
  22 #include "thread.h"
  23 #include "adc.h"
  24
  25 #if CONFIG_CPU == SH7034
  26 /**************************************************************************
  27  ** The A/D conversion is done every tick, in three steps:
  28  **
  29  ** 1) On the tick interrupt, the conversion of channels 0-3 is started, and
  30  **    the A/D interrupt is enabled.
  31  **
  32  ** 2) After the conversion is done (approx. 256*4 cycles later), an interrupt
  33  **    is generated at level 1, which is the same level as the tick interrupt
  34  **    itself. This interrupt will be pending until the tick interrupt is
  35  **    finished.
  36  **    When the A/D interrupt is finally served, it will read the results
  37  **    from the first conversion and start the conversion of channels 4-7.
  38  **
  39  ** 3) When the conversion of channels 4-7 is finished, the interrupt is
  40  **    triggered again, and the results are read. This time, no new
  41  **    conversion is started, it will be done in the next tick interrupt.
  42  **
  43  ** Thus, each channel will be updated HZ times per second.
  44  **
  45  *************************************************************************/
  46
  47 static int current_channel;
  48 static unsigned short adcdata[NUM_ADC_CHANNELS];
  49
  50 static void adc_tick(void)
  51 {
  52     /* Start a conversion of channel group 0. This will trigger an interrupt,
  53        and the interrupt handler will take care of group 1. */
  54
  55     current_channel = 0;
  56     ADCSR = ADCSR_ADST | ADCSR_ADIE | ADCSR_SCAN | 3;
  57 }
  58
  59 #pragma interrupt
  60 void ADITI(void)
  61 {
  62     if(ADCSR & ADCSR_ADF)
  63     {
  64         ADCSR = 0;
  65
  66         if(current_channel == 0)
  67         {
  68             adcdata[0] = ADDRA >> 6;
  69             adcdata[1] = ADDRB >> 6;
  70             adcdata[2] = ADDRC >> 6;
  71             adcdata[3] = ADDRD >> 6;
  72             current_channel = 4;
  73
  74             /* Convert the next group */
  75             ADCSR = ADCSR_ADST | ADCSR_ADIE | ADCSR_SCAN | 7;
  76         }
  77         else
  78         {
  79             adcdata[4] = ADDRA >> 6;
  80             adcdata[5] = ADDRB >> 6;
  81             adcdata[6] = ADDRC >> 6;
  82             adcdata[7] = ADDRD >> 6;
  83         }
  84     }
  85 }
  86
  87 unsigned short adc_read(int channel)
  88 {
  89     return adcdata[channel];
  90 }
  91
  92 void adc_init(void)
  93 {
  94     ADCR  = 0x7f; /* No external trigger; other bits should be 1 according
  95                      to the manual... */
  96
  97     ADCSR = 0;
  98
  99     current_channel = 0;
 100
 101     /* Enable the A/D IRQ on level 1 */
 102     IPRE = (IPRE & 0xf0ff) | 0x0100;
 103
 104     tick_add_task(adc_tick);
 105
 106     sleep(2);    /* Ensure valid readings when adc_init returns */
 107 }
 108 #elif CONFIG_CPU == MCF5249
 109
 110 static unsigned char adcdata[NUM_ADC_CHANNELS];
 111
 112 #define CS_LO  GPIO_OUT &= ~0x80
 113 #define CS_HI  GPIO_OUT |= 0x80
 114 #define CLK_LO GPIO_OUT &= ~0x00400000
 115 #define CLK_HI GPIO_OUT |= 0x00400000
 116 #define DO     (GPIO_READ & 0x80000000)
 117 #define DI_LO  GPIO_OUT &= ~0x00200000
 118 #define DI_HI  GPIO_OUT |= 0x00200000
 119
 120 /* delay loop */
 121 #define DELAY   do { int _x; for(_x=0;_x<10;_x++);} while (0)
 122
 123 unsigned char adc_scan(int channel)
 124 {
 125     unsigned char data = 0;
 126     int i;
 127
 128     CS_LO;
 129
 130     DI_HI;  /* Start bit */
 131     DELAY;
 132     CLK_HI;
 133     DELAY;
 134     CLK_LO;
 135
 136     DI_HI;  /* Single channel */
 137     DELAY;
 138     CLK_HI;
 139     DELAY;
 140     CLK_LO;
 141
 142     if(channel & 1) /* LSB of channel number */
 143         DI_HI;
 144     else
 145         DI_LO;
 146     DELAY;
 147     CLK_HI;
 148     DELAY;
 149     CLK_LO;
 150
 151     if(channel & 2) /* MSB of channel number */
 152         DI_HI;
 153     else
 154         DI_LO;
 155     DELAY;
 156     CLK_HI;
 157     DELAY;
 158     CLK_LO;
 159
 160     DELAY;
 161
 162     for(i = 0;i < 8;i++) /* 8 bits of data */
 163     {
 164         CLK_HI;
 165         DELAY;
 166         CLK_LO;
 167         DELAY;
 168         data <<= 1;
 169         data |= DO?1:0;
 170     }
 171
 172     CS_HI;
 173
 174     return data;
 175 }
 176
 177 unsigned short adc_read(int channel)
 178 {
 179     return adcdata[channel];
 180 }
 181
 182 static int adc_counter;
 183
 184 static void adc_tick(void)
 185 {
 186     if(++adc_counter == HZ)
 187     {
 188         adc_counter = 0;
 189         adcdata[ADC_BATTERY] = adc_scan(ADC_BATTERY);
 190     }
 191 }
 192
 193 void adc_init(void)
 194 {
 195     GPIO_FUNCTION |= 0x80600080; /* GPIO7:  CS
 196                                     GPIO21: Data In (to the ADC)
 197                                     GPIO22: CLK
 198                                     GPIO31: Data Out (from the ADC) */
 199     GPIO_ENABLE |= 0x00600080;
 200     GPIO_OUT |= 0x80;         /* CS high */
 201     GPIO_OUT &= ~0x00400000;  /* CLK low */
 202
 203     tick_add_task(adc_tick);
 204
 205     adcdata[3] = adc_scan(3);
 206 }
 207
 208 #elif CONFIG_CPU == TCC730
 209
 210
 211 /**************************************************************************
 212  **
 213  ** Each channel will be updated HZ/CHANNEL_ORDER_SIZE times per second.
 214  **
 215  *************************************************************************/
 216
 217 static int current_channel;
 218 static int current_channel_idx;
 219 static unsigned short adcdata[NUM_ADC_CHANNELS];
 220
 221 #define CHANNEL_ORDER_SIZE 2
 222 static int channel_order[CHANNEL_ORDER_SIZE] = {6,7};
 223
 224 static void adc_tick(void)
 225 {
 226     if (ADCON & (1 << 3)) {
 227         /* previous conversion finished? */
 228         adcdata[current_channel] = ADDATA >> 6;
 229         if (++current_channel_idx >= CHANNEL_ORDER_SIZE)
 230             current_channel_idx = 0;
 231         current_channel = channel_order[current_channel_idx];
 232         int adcon = (current_channel << 4) | 1;
 233         ADCON = adcon;
 234     }
 235 }
 236
 237 unsigned short adc_read(int channel)
 238 {
 239     return adcdata[channel];
 240 }
 241
 242 void adc_init(void)
 243 {
 244     current_channel_idx = 0;
 245     current_channel = channel_order[current_channel_idx];
 246
 247     ADCON = (current_channel << 4) | 1;
 248
 249     tick_add_task(adc_tick);
 250
 251     sleep(2);    /* Ensure valid readings when adc_init returns */
 252 }
 253
 254 #endif