?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Added some error returns
[kugel-rb.git] / firmware / target / arm / usb-drv-pp502x.c
blob1db3ebd42f636c644049cf9940dfa299fe024080
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Driver for ARC USBOTG Device Controller
11 *
12 * Copyright (C) 2007 by Björn Stenberg
13 *
14 * All files in this archive are subject to the GNU General Public License.
15 * See the file COPYING in the source tree root for full license agreement.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22 #include "system.h"
23 #include "string.h"
24 #include "usb_ch9.h"
25 #include "usb_core.h"
26 //#define LOGF_ENABLE
27 #include "logf.h"
28
29 /* USB device mode registers (Little Endian) */
30
31 #define REG_ID (*(volatile unsigned int *)(USB_BASE+0x000))
32 #define REG_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x004))
33 #define REG_CAPLENGTH (*(volatile unsigned char*)(USB_BASE+0x100))
34 #define REG_DCIVERSION (*(volatile unsigned int *)(USB_BASE+0x120))
35 #define REG_DCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x124))
36 #define REG_USBCMD (*(volatile unsigned int *)(USB_BASE+0x140))
37 #define REG_USBSTS (*(volatile unsigned int *)(USB_BASE+0x144))
38 #define REG_USBINTR (*(volatile unsigned int *)(USB_BASE+0x148))
39 #define REG_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x14c))
40 #define REG_DEVICEADDR (*(volatile unsigned int *)(USB_BASE+0x154))
41 #define REG_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158))
42 #define REG_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x160))
43 #define REG_CONFIGFLAG (*(volatile unsigned int *)(USB_BASE+0x180))
44 #define REG_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x184))
45 #define REG_OTGSC (*(volatile unsigned int *)(USB_BASE+0x1a4))
46 #define REG_USBMODE (*(volatile unsigned int *)(USB_BASE+0x1a8))
47 #define REG_ENDPTSETUPSTAT (*(volatile unsigned int *)(USB_BASE+0x1ac))
48 #define REG_ENDPTPRIME (*(volatile unsigned int *)(USB_BASE+0x1b0))
49 #define REG_ENDPTFLUSH (*(volatile unsigned int *)(USB_BASE+0x1b4))
50 #define REG_ENDPTSTATUS (*(volatile unsigned int *)(USB_BASE+0x1b8))
51 #define REG_ENDPTCOMPLETE (*(volatile unsigned int *)(USB_BASE+0x1bc))
52 #define REG_ENDPTCTRL0 (*(volatile unsigned int *)(USB_BASE+0x1c0))
53 #define REG_ENDPTCTRL1 (*(volatile unsigned int *)(USB_BASE+0x1c4))
54 #define REG_ENDPTCTRL2 (*(volatile unsigned int *)(USB_BASE+0x1c8))
55 #define REG_ENDPTCTRL(_x_) (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(_x_)))
56
57 /* Frame Index Register Bit Masks */
58 #define USB_FRINDEX_MASKS (0x3fff)
59
60 /* USB CMD Register Bit Masks */
61 #define USBCMD_RUN (0x00000001)
62 #define USBCMD_CTRL_RESET (0x00000002)
63 #define USBCMD_PERIODIC_SCHEDULE_EN (0x00000010)
64 #define USBCMD_ASYNC_SCHEDULE_EN (0x00000020)
65 #define USBCMD_INT_AA_DOORBELL (0x00000040)
66 #define USBCMD_ASP (0x00000300)
67 #define USBCMD_ASYNC_SCH_PARK_EN (0x00000800)
68 #define USBCMD_SUTW (0x00002000)
69 #define USBCMD_ATDTW (0x00004000)
70 #define USBCMD_ITC (0x00FF0000)
71
72 /* bit 15,3,2 are frame list size */
73 #define USBCMD_FRAME_SIZE_1024 (0x00000000)
74 #define USBCMD_FRAME_SIZE_512 (0x00000004)
75 #define USBCMD_FRAME_SIZE_256 (0x00000008)
76 #define USBCMD_FRAME_SIZE_128 (0x0000000C)
77 #define USBCMD_FRAME_SIZE_64 (0x00008000)
78 #define USBCMD_FRAME_SIZE_32 (0x00008004)
79 #define USBCMD_FRAME_SIZE_16 (0x00008008)
80 #define USBCMD_FRAME_SIZE_8 (0x0000800C)
81
82 /* bit 9-8 are async schedule park mode count */
83 #define USBCMD_ASP_00 (0x00000000)
84 #define USBCMD_ASP_01 (0x00000100)
85 #define USBCMD_ASP_10 (0x00000200)
86 #define USBCMD_ASP_11 (0x00000300)
87 #define USBCMD_ASP_BIT_POS (8)
88
89 /* bit 23-16 are interrupt threshold control */
90 #define USBCMD_ITC_NO_THRESHOLD (0x00000000)
91 #define USBCMD_ITC_1_MICRO_FRM (0x00010000)
92 #define USBCMD_ITC_2_MICRO_FRM (0x00020000)
93 #define USBCMD_ITC_4_MICRO_FRM (0x00040000)
94 #define USBCMD_ITC_8_MICRO_FRM (0x00080000)
95 #define USBCMD_ITC_16_MICRO_FRM (0x00100000)
96 #define USBCMD_ITC_32_MICRO_FRM (0x00200000)
97 #define USBCMD_ITC_64_MICRO_FRM (0x00400000)
98 #define USBCMD_ITC_BIT_POS (16)
99
100 /* USB STS Register Bit Masks */
101 #define USBSTS_INT (0x00000001)
102 #define USBSTS_ERR (0x00000002)
103 #define USBSTS_PORT_CHANGE (0x00000004)
104 #define USBSTS_FRM_LST_ROLL (0x00000008)
105 #define USBSTS_SYS_ERR (0x00000010) /* not used */
106 #define USBSTS_IAA (0x00000020)
107 #define USBSTS_RESET (0x00000040)
108 #define USBSTS_SOF (0x00000080)
109 #define USBSTS_SUSPEND (0x00000100)
110 #define USBSTS_HC_HALTED (0x00001000)
111 #define USBSTS_RCL (0x00002000)
112 #define USBSTS_PERIODIC_SCHEDULE (0x00004000)
113 #define USBSTS_ASYNC_SCHEDULE (0x00008000)
114
115 /* USB INTR Register Bit Masks */
116 #define USBINTR_INT_EN (0x00000001)
117 #define USBINTR_ERR_INT_EN (0x00000002)
118 #define USBINTR_PTC_DETECT_EN (0x00000004)
119 #define USBINTR_FRM_LST_ROLL_EN (0x00000008)
120 #define USBINTR_SYS_ERR_EN (0x00000010)
121 #define USBINTR_ASYN_ADV_EN (0x00000020)
122 #define USBINTR_RESET_EN (0x00000040)
123 #define USBINTR_SOF_EN (0x00000080)
124 #define USBINTR_DEVICE_SUSPEND (0x00000100)
125
126 /* Device Address bit masks */
127 #define USBDEVICEADDRESS_MASK (0xFE000000)
128 #define USBDEVICEADDRESS_BIT_POS (25)
129
130 /* endpoint list address bit masks */
131 #define USB_EP_LIST_ADDRESS_MASK (0xfffff800)
132
133 /* PORTSCX Register Bit Masks */
134 #define PORTSCX_CURRENT_CONNECT_STATUS (0x00000001)
135 #define PORTSCX_CONNECT_STATUS_CHANGE (0x00000002)
136 #define PORTSCX_PORT_ENABLE (0x00000004)
137 #define PORTSCX_PORT_EN_DIS_CHANGE (0x00000008)
138 #define PORTSCX_OVER_CURRENT_ACT (0x00000010)
139 #define PORTSCX_OVER_CURRENT_CHG (0x00000020)
140 #define PORTSCX_PORT_FORCE_RESUME (0x00000040)
141 #define PORTSCX_PORT_SUSPEND (0x00000080)
142 #define PORTSCX_PORT_RESET (0x00000100)
143 #define PORTSCX_LINE_STATUS_BITS (0x00000C00)
144 #define PORTSCX_PORT_POWER (0x00001000)
145 #define PORTSCX_PORT_INDICTOR_CTRL (0x0000C000)
146 #define PORTSCX_PORT_TEST_CTRL (0x000F0000)
147 #define PORTSCX_WAKE_ON_CONNECT_EN (0x00100000)
148 #define PORTSCX_WAKE_ON_CONNECT_DIS (0x00200000)
149 #define PORTSCX_WAKE_ON_OVER_CURRENT (0x00400000)
150 #define PORTSCX_PHY_LOW_POWER_SPD (0x00800000)
151 #define PORTSCX_PORT_FORCE_FULL_SPEED (0x01000000)
152 #define PORTSCX_PORT_SPEED_MASK (0x0C000000)
153 #define PORTSCX_PORT_WIDTH (0x10000000)
154 #define PORTSCX_PHY_TYPE_SEL (0xC0000000)
155
156 /* bit 11-10 are line status */
157 #define PORTSCX_LINE_STATUS_SE0 (0x00000000)
158 #define PORTSCX_LINE_STATUS_JSTATE (0x00000400)
159 #define PORTSCX_LINE_STATUS_KSTATE (0x00000800)
160 #define PORTSCX_LINE_STATUS_UNDEF (0x00000C00)
161 #define PORTSCX_LINE_STATUS_BIT_POS (10)
162
163 /* bit 15-14 are port indicator control */
164 #define PORTSCX_PIC_OFF (0x00000000)
165 #define PORTSCX_PIC_AMBER (0x00004000)
166 #define PORTSCX_PIC_GREEN (0x00008000)
167 #define PORTSCX_PIC_UNDEF (0x0000C000)
168 #define PORTSCX_PIC_BIT_POS (14)
169
170 /* bit 19-16 are port test control */
171 #define PORTSCX_PTC_DISABLE (0x00000000)
172 #define PORTSCX_PTC_JSTATE (0x00010000)
173 #define PORTSCX_PTC_KSTATE (0x00020000)
174 #define PORTSCX_PTC_SEQNAK (0x00030000)
175 #define PORTSCX_PTC_PACKET (0x00040000)
176 #define PORTSCX_PTC_FORCE_EN (0x00050000)
177 #define PORTSCX_PTC_BIT_POS (16)
178
179 /* bit 27-26 are port speed */
180 #define PORTSCX_PORT_SPEED_FULL (0x00000000)
181 #define PORTSCX_PORT_SPEED_LOW (0x04000000)
182 #define PORTSCX_PORT_SPEED_HIGH (0x08000000)
183 #define PORTSCX_PORT_SPEED_UNDEF (0x0C000000)
184 #define PORTSCX_SPEED_BIT_POS (26)
185
186 /* bit 28 is parallel transceiver width for UTMI interface */
187 #define PORTSCX_PTW (0x10000000)
188 #define PORTSCX_PTW_8BIT (0x00000000)
189 #define PORTSCX_PTW_16BIT (0x10000000)
190
191 /* bit 31-30 are port transceiver select */
192 #define PORTSCX_PTS_UTMI (0x00000000)
193 #define PORTSCX_PTS_ULPI (0x80000000)
194 #define PORTSCX_PTS_FSLS (0xC0000000)
195 #define PORTSCX_PTS_BIT_POS (30)
196
197 /* USB MODE Register Bit Masks */
198 #define USBMODE_CTRL_MODE_IDLE (0x00000000)
199 #define USBMODE_CTRL_MODE_DEVICE (0x00000002)
200 #define USBMODE_CTRL_MODE_HOST (0x00000003)
201 #define USBMODE_CTRL_MODE_RSV (0x00000001)
202 #define USBMODE_SETUP_LOCK_OFF (0x00000008)
203 #define USBMODE_STREAM_DISABLE (0x00000010)
204
205 /* Endpoint Flush Register */
206 #define EPFLUSH_TX_OFFSET (0x00010000)
207 #define EPFLUSH_RX_OFFSET (0x00000000)
208
209 /* Endpoint Setup Status bit masks */
210 #define EPSETUP_STATUS_MASK (0x0000003F)
211 #define EPSETUP_STATUS_EP0 (0x00000001)
212
213 /* ENDPOINTCTRLx Register Bit Masks */
214 #define EPCTRL_TX_ENABLE (0x00800000)
215 #define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000) /* Not EP0 */
216 #define EPCTRL_TX_DATA_TOGGLE_INH (0x00200000) /* Not EP0 */
217 #define EPCTRL_TX_TYPE (0x000C0000)
218 #define EPCTRL_TX_DATA_SOURCE (0x00020000) /* Not EP0 */
219 #define EPCTRL_TX_EP_STALL (0x00010000)
220 #define EPCTRL_RX_ENABLE (0x00000080)
221 #define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040) /* Not EP0 */
222 #define EPCTRL_RX_DATA_TOGGLE_INH (0x00000020) /* Not EP0 */
223 #define EPCTRL_RX_TYPE (0x0000000C)
224 #define EPCTRL_RX_DATA_SINK (0x00000002) /* Not EP0 */
225 #define EPCTRL_RX_EP_STALL (0x00000001)
226
227 /* bit 19-18 and 3-2 are endpoint type */
228 #define EPCTRL_EP_TYPE_CONTROL (0)
229 #define EPCTRL_EP_TYPE_ISO (1)
230 #define EPCTRL_EP_TYPE_BULK (2)
231 #define EPCTRL_EP_TYPE_INTERRUPT (3)
232 #define EPCTRL_TX_EP_TYPE_SHIFT (18)
233 #define EPCTRL_RX_EP_TYPE_SHIFT (2)
234
235 /* pri_ctrl Register Bit Masks */
236 #define PRI_CTRL_PRI_LVL1 (0x0000000C)
237 #define PRI_CTRL_PRI_LVL0 (0x00000003)
238
239 /* si_ctrl Register Bit Masks */
240 #define SI_CTRL_ERR_DISABLE (0x00000010)
241 #define SI_CTRL_IDRC_DISABLE (0x00000008)
242 #define SI_CTRL_RD_SAFE_EN (0x00000004)
243 #define SI_CTRL_RD_PREFETCH_DISABLE (0x00000002)
244 #define SI_CTRL_RD_PREFEFETCH_VAL (0x00000001)
245
246 /* control Register Bit Masks */
247 #define USB_CTRL_IOENB (0x00000004)
248 #define USB_CTRL_ULPI_INT0EN (0x00000001)
249
250 /* OTGSC Register Bit Masks */
251 #define OTGSC_B_SESSION_VALID (0x00000800)
252
253 #define QH_MULT_POS (30)
254 #define QH_ZLT_SEL (0x20000000)
255 #define QH_MAX_PKT_LEN_POS (16)
256 #define QH_IOS (0x00008000)
257 #define QH_NEXT_TERMINATE (0x00000001)
258 #define QH_IOC (0x00008000)
259 #define QH_MULTO (0x00000C00)
260 #define QH_STATUS_HALT (0x00000040)
261 #define QH_STATUS_ACTIVE (0x00000080)
262 #define EP_QUEUE_CURRENT_OFFSET_MASK (0x00000FFF)
263 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK (0xFFFFFFE0)
264 #define EP_QUEUE_FRINDEX_MASK (0x000007FF)
265 #define EP_MAX_LENGTH_TRANSFER (0x4000)
266
267 #define DTD_NEXT_TERMINATE (0x00000001)
268 #define DTD_IOC (0x00008000)
269 #define DTD_STATUS_ACTIVE (0x00000080)
270 #define DTD_STATUS_HALTED (0x00000040)
271 #define DTD_STATUS_DATA_BUFF_ERR (0x00000020)
272 #define DTD_STATUS_TRANSACTION_ERR (0x00000008)
273 #define DTD_RESERVED_FIELDS (0x80007300)
274 #define DTD_ADDR_MASK (0xFFFFFFE0)
275 #define DTD_PACKET_SIZE (0x7FFF0000)
276 #define DTD_LENGTH_BIT_POS (16)
277 #define DTD_ERROR_MASK (DTD_STATUS_HALTED | \
278 DTD_STATUS_DATA_BUFF_ERR | \
279 DTD_STATUS_TRANSACTION_ERR)
280
281 /*-------------------------------------------------------------------------*/
282
283 /* manual: 32.13.2 Endpoint Transfer Descriptor (dTD) */
284 struct transfer_descriptor {
285 unsigned int next_td_ptr; /* Next TD pointer(31-5), T(0) set
286 indicate invalid */
287 unsigned int size_ioc_sts; /* Total bytes (30-16), IOC (15),
288 MultO(11-10), STS (7-0) */
289 unsigned int buff_ptr0; /* Buffer pointer Page 0 */
290 unsigned int buff_ptr1; /* Buffer pointer Page 1 */
291 unsigned int buff_ptr2; /* Buffer pointer Page 2 */
292 unsigned int buff_ptr3; /* Buffer pointer Page 3 */
293 unsigned int buff_ptr4; /* Buffer pointer Page 4 */
294 unsigned int reserved;
295 } __attribute__ ((packed));
296
297 static struct transfer_descriptor _td_array[NUM_ENDPOINTS*2] __attribute((aligned (32)));
298 static struct transfer_descriptor* td_array;
299
300 /* manual: 32.13.1 Endpoint Queue Head (dQH) */
301 struct queue_head {
302 unsigned int max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len
303 and IOS(15) */
304 unsigned int curr_dtd_ptr; /* Current dTD Pointer(31-5) */
305 struct transfer_descriptor dtd; /* dTD overlay */
306 unsigned int setup_buffer[2]; /* Setup data 8 bytes */
307 unsigned int reserved[4];
308 } __attribute__((packed));
309
310 static struct queue_head _qh_array[NUM_ENDPOINTS*2] __attribute((aligned (2048)));
311 static struct queue_head* qh_array;
312
313
314 static const unsigned int pipe2mask[NUM_ENDPOINTS*2] = {
315 0x01, 0x010000,
316 0x02, 0x020000,
317 0x04, 0x040000,
318 };
319
320 /*-------------------------------------------------------------------------*/
321 static void transfer_completed(void);
322 static int prime_transfer(int endpoint, void* ptr, int len, bool send);
323 static void bus_reset(void);
324 static void init_queue_heads(void);
325 static void init_endpoints(void);
326 /*-------------------------------------------------------------------------*/
327
328 bool usb_drv_powered(void)
329 {
330 return (REG_OTGSC & OTGSC_B_SESSION_VALID) ? true : false;
331 }
332
333 /* manual: 32.14.1 Device Controller Initialization */
334 void usb_drv_init(void)
335 {
336 REG_USBCMD &= ~USBCMD_RUN;
337 udelay(50000);
338 REG_USBCMD |= USBCMD_CTRL_RESET;
339 while (REG_USBCMD & USBCMD_CTRL_RESET);
340
341 REG_USBMODE = USBMODE_CTRL_MODE_DEVICE;
342
343 td_array = (struct transfer_descriptor*)UNCACHED_ADDR(&_td_array);
344 qh_array = (struct queue_head*)UNCACHED_ADDR(&_qh_array);
345 init_queue_heads();
346 memset(td_array, 0, sizeof _td_array);
347
348 REG_ENDPOINTLISTADDR = (unsigned int)qh_array;
349 REG_DEVICEADDR = 0;
350
351 /* enable USB interrupts */
352 REG_USBINTR =
353 USBINTR_INT_EN |
354 USBINTR_ERR_INT_EN |
355 USBINTR_PTC_DETECT_EN |
356 USBINTR_RESET_EN |
357 USBINTR_SYS_ERR_EN;
358
359 /* enable USB IRQ in CPU */
360 CPU_INT_EN |= USB_MASK;
361
362 /* go go go */
363 REG_USBCMD |= USBCMD_RUN;
364
365 logf("usb_drv_init() finished");
366 logf("usb id %x", REG_ID);
367 logf("usb dciversion %x", REG_DCIVERSION);
368 logf("usb dccparams %x", REG_DCCPARAMS);
369
370 /* now a bus reset will occur. see bus_reset() */
371 }
372
373 void usb_drv_exit(void)
374 {
375 /* disable interrupts */
376 REG_USBINTR = 0;
377
378 /* stop usb controller */
379 REG_USBCMD &= ~USBCMD_RUN;
380 }
381
382 void usb_drv_int(void)
383 {
384 unsigned int status = REG_USBSTS;
385
386 #if 0
387 if (status & USBSTS_INT) logf("int: usb ioc");
388 if (status & USBSTS_ERR) logf("int: usb err");
389 if (status & USBSTS_PORT_CHANGE) logf("int: portchange");
390 if (status & USBSTS_RESET) logf("int: reset");
391 if (status & USBSTS_SYS_ERR) logf("int: syserr");
392 #endif
393
394 /* usb transaction interrupt */
395 if (status & USBSTS_INT) {
396 REG_USBSTS |= USBSTS_INT;
397
398 /* a control packet? */
399 if (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0) {
400 /* copy setup data from packet */
401 unsigned int tmp[2];
402 tmp[0] = qh_array[0].setup_buffer[0];
403 tmp[1] = qh_array[0].setup_buffer[1];
404
405 /* acknowledge packet recieved */
406 REG_ENDPTSETUPSTAT |= EPSETUP_STATUS_EP0;
407
408 usb_core_control_request((struct usb_ctrlrequest*)tmp);
409 }
410
411 if (REG_ENDPTCOMPLETE)
412 transfer_completed();
413 }
414
415 /* error interrupt */
416 if (status & USBSTS_ERR) {
417 REG_USBSTS |= USBSTS_ERR;
418 logf("usb error int");
419 }
420
421 /* reset interrupt */
422 if (status & USBSTS_RESET) {
423 REG_USBSTS |= USBSTS_RESET;
424 bus_reset();
425 usb_core_bus_reset(); /* tell mom */
426 }
427
428 /* port change */
429 if (status & USBSTS_PORT_CHANGE) {
430 REG_USBSTS |= USBSTS_PORT_CHANGE;
431 }
432 }
433
434 void usb_drv_stall(int endpoint, bool stall)
435 {
436 logf("%sstall %d", stall?"":"un", endpoint);
437
438 if (stall) {
439 REG_ENDPTCTRL(endpoint) |= EPCTRL_RX_EP_STALL;
440 REG_ENDPTCTRL(endpoint) |= EPCTRL_TX_EP_STALL;
441 }
442 else {
443 REG_ENDPTCTRL(endpoint) &= ~EPCTRL_RX_EP_STALL;
444 REG_ENDPTCTRL(endpoint) &= ~EPCTRL_TX_EP_STALL;
445 }
446 }
447
448 int usb_drv_send(int endpoint, void* ptr, int length)
449 {
450 return prime_transfer(endpoint, ptr, length, true);
451 }
452
453 int usb_drv_recv(int endpoint, void* ptr, int length)
454 {
455 //logf("usbrecv(%x, %d)", ptr, length);
456 return prime_transfer(endpoint, ptr, length, false);
457 }
458
459 void usb_drv_wait(int endpoint, bool send)
460 {
461 int pipe = endpoint * 2 + (send ? 1 : 0);
462 struct queue_head* qh = &qh_array[pipe];
463
464 while (qh->dtd.size_ioc_sts & QH_STATUS_ACTIVE) {
465 if (REG_USBSTS & USBSTS_RESET)
466 break;
467 }
468 }
469
470
471 void usb_drv_set_address(int address)
472 {
473 REG_DEVICEADDR = address << USBDEVICEADDRESS_BIT_POS;
474 init_endpoints();
475 }
476
477 void usb_drv_reset_endpoint(int endpoint, bool send)
478 {
479 int pipe = endpoint * 2 + (send ? 1 : 0);
480 unsigned int mask = pipe2mask[pipe];
481 REG_ENDPTFLUSH = mask;
482 while (REG_ENDPTFLUSH & mask);
483 }
484
485 /*-------------------------------------------------------------------------*/
486
487 /* manual: 32.14.5.2 */
488 static int prime_transfer(int endpoint, void* ptr, int len, bool send)
489 {
490 int timeout;
491 int pipe = endpoint * 2 + (send ? 1 : 0);
492 unsigned int mask = pipe2mask[pipe];
493 struct transfer_descriptor* td = &td_array[pipe];
494 struct queue_head* qh = &qh_array[pipe];
495
496 if (send && endpoint > EP_CONTROL) {
497 logf("usb: sent %d bytes", len);
498 }
499
500 memset(td, 0, sizeof(struct transfer_descriptor));
501 td->next_td_ptr = DTD_NEXT_TERMINATE;
502 td->size_ioc_sts = (len << DTD_LENGTH_BIT_POS) |
503 DTD_STATUS_ACTIVE | DTD_IOC;
504 td->buff_ptr0 = (unsigned int)ptr;
505 td->buff_ptr1 = (unsigned int)ptr + 0x1000;
506 td->buff_ptr2 = (unsigned int)ptr + 0x2000;
507 td->buff_ptr3 = (unsigned int)ptr + 0x3000;
508 td->buff_ptr4 = (unsigned int)ptr + 0x4000;
509 td->reserved = len;
510 qh->dtd.next_td_ptr = (unsigned int)td;
511 qh->dtd.size_ioc_sts &= ~(QH_STATUS_HALT | QH_STATUS_ACTIVE);
512
513 REG_ENDPTPRIME |= mask;
514
515 timeout = 10000;
516 while ((REG_ENDPTPRIME & mask) && --timeout) {
517 if (REG_USBSTS & USBSTS_RESET)
518 return -1;
519 }
520 if (!timeout) {
521 logf("prime timeout");
522 return -2;
523 }
524
525 if (!(REG_ENDPTSTATUS & mask)) {
526 logf("no prime! %d %d %x", endpoint, pipe, qh->dtd.size_ioc_sts & 0xff );
527 return -3;
528 }
529
530 if (send) {
531 /* wait for transfer to finish */
532 timeout = 100000;
533 while ((td->size_ioc_sts & DTD_STATUS_ACTIVE) && --timeout) {
534 if (REG_ENDPTCOMPLETE & mask)
535 REG_ENDPTCOMPLETE |= mask;
536
537 if (REG_USBSTS & USBSTS_RESET)
538 return -4;
539 }
540 if (!timeout) {
541 logf("td never finished");
542 return -5;
543 }
544 }
545
546 return 0;
547 }
548
549 static void transfer_completed(void)
550 {
551 int i;
552 unsigned int mask = REG_ENDPTCOMPLETE;
553 REG_ENDPTCOMPLETE |= mask;
554
555 //logf("usb comp %x", mask);
556
557 for (i=0; i<NUM_ENDPOINTS; i++) {
558 int x;
559 for (x=0; x<2; x++) {
560 int pipe = i * 2 + x;
561 if (mask & pipe2mask[pipe])
562 usb_core_transfer_complete(i, x ? true : false);
563
564 if ((mask & pipe2mask[pipe]) &&
565 (td_array[pipe].size_ioc_sts & DTD_ERROR_MASK)) {
566 logf("pipe %d err %x", pipe, td_array[pipe].size_ioc_sts & DTD_ERROR_MASK);
567 }
568 }
569 }
570 }
571
572 /* manual: 32.14.2.1 Bus Reset */
573 static void bus_reset(void)
574 {
575 int i;
576 logf("usb bus_reset");
577
578 REG_DEVICEADDR = 0;
579 REG_ENDPTSETUPSTAT = REG_ENDPTSETUPSTAT;
580 REG_ENDPTCOMPLETE = REG_ENDPTCOMPLETE;
581
582 for (i=0; i<100; i++) {
583 if (!REG_ENDPTPRIME)
584 break;
585
586 if (REG_USBSTS & USBSTS_RESET) {
587 logf("usb: double reset");
588 return;
589 }
590
591 udelay(100);
592 }
593 if (REG_ENDPTPRIME) {
594 logf("usb: short reset timeout");
595 }
596
597 REG_ENDPTFLUSH = ~0;
598 //while (REG_ENDPTFLUSH);
599
600 if (!(REG_PORTSC1 & PORTSCX_PORT_RESET)) {
601 logf("usb: slow reset!");
602 }
603 }
604
605 /* manual: 32.14.4.1 Queue Head Initialization */
606 static void init_queue_heads(void)
607 {
608 memset(qh_array, 0, sizeof _qh_array);
609
610 /*** control ***/
611 qh_array[EP_CONTROL].max_pkt_length = 512 << QH_MAX_PKT_LEN_POS | QH_IOS;
612 qh_array[EP_CONTROL].dtd.next_td_ptr = QH_NEXT_TERMINATE;
613 qh_array[EP_CONTROL+1].max_pkt_length = 512 << QH_MAX_PKT_LEN_POS;
614 qh_array[EP_CONTROL+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
615
616 /*** bulk ***/
617 qh_array[EP_RX*2].max_pkt_length = 512 << QH_MAX_PKT_LEN_POS;
618 qh_array[EP_RX*2].dtd.next_td_ptr = QH_NEXT_TERMINATE;
619 qh_array[EP_TX*2+1].max_pkt_length = 512 << QH_MAX_PKT_LEN_POS;
620 qh_array[EP_TX*2+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
621 }
622
623 static void init_endpoints(void)
624 {
625 /* bulk */
626 REG_ENDPTCTRL(EP_RX) =
627 EPCTRL_RX_DATA_TOGGLE_RST | EPCTRL_RX_ENABLE |
628 (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT) |
629 (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT);
630
631 REG_ENDPTCTRL(EP_TX) =
632 EPCTRL_TX_DATA_TOGGLE_RST | EPCTRL_TX_ENABLE |
633 (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT) |
634 (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT);
635 }
My public Rockbox git repo