firmware/drivers/synaptics-mep.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 by Mark Arigo
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include <stdlib.h>
  23 #include "config.h"
  24 #include "cpu.h"
  25 #include "system.h"
  26 #include "kernel.h"
  27 #include "system.h"
  28
  29 #define LOGF_ENABLE
  30 #include "logf.h"
  31
  32 /* Driver for the Synaptics Touchpad based on the "Synaptics Modular Embedded
  33    Protocol: 3-Wire Interface Specification" documentation */
  34
  35 #if defined(MROBE_100)
  36 #define ACK     (GPIOD_INPUT_VAL & 0x1)
  37 #define ACK_HI  GPIOD_OUTPUT_VAL |=  0x1
  38 #define ACK_LO  GPIOD_OUTPUT_VAL &= ~0x1
  39
  40 #define CLK     ((GPIOD_INPUT_VAL & 0x2) >> 1)
  41 #define CLK_HI  GPIOD_OUTPUT_VAL |=  0x2
  42 #define CLK_LO  GPIOD_OUTPUT_VAL &= ~0x2
  43
  44 #define DATA    ((GPIOD_INPUT_VAL & 0x4) >> 2)
  45 #define DATA_HI GPIOD_OUTPUT_EN |= 0x4; GPIOD_OUTPUT_VAL |=  0x4
  46 #define DATA_LO GPIOD_OUTPUT_EN |= 0x4; GPIOD_OUTPUT_VAL &= ~0x4
  47 #define DATA_CL GPIOD_OUTPUT_EN &= ~0x4
  48
  49 #elif defined(PHILIPS_HDD1630)
  50 #define ACK     (GPIOD_INPUT_VAL & 0x80)
  51 #define ACK_HI  GPIOD_OUTPUT_VAL |=  0x80
  52 #define ACK_LO  GPIOD_OUTPUT_VAL &= ~0x80
  53
  54 #define CLK     ((GPIOA_INPUT_VAL & 0x20) >> 5)
  55 #define CLK_HI  GPIOA_OUTPUT_VAL |=  0x20
  56 #define CLK_LO  GPIOA_OUTPUT_VAL &= ~0x20
  57
  58 #define DATA    ((GPIOA_INPUT_VAL & 0x10) >> 4)
  59 #define DATA_HI GPIOA_OUTPUT_EN |= 0x10; GPIOA_OUTPUT_VAL |=  0x10
  60 #define DATA_LO GPIOA_OUTPUT_EN |= 0x10; GPIOA_OUTPUT_VAL &= ~0x10
  61 #define DATA_CL GPIOA_OUTPUT_EN &= ~0x10
  62 #endif
  63
  64 #define LO 0
  65 #define HI 1
  66
  67 #define READ_RETRY      8
  68 #define READ_ERROR     -1
  69
  70 #define MEP_HELLO_HEADER 0x19
  71 #define MEP_HELLO_ID     0x1
  72
  73 #define MEP_READ  0x1
  74 #define MEP_WRITE 0x3
  75
  76 static int syn_wait_clk_change(unsigned int val)
  77 {
  78     int i;
  79
  80     for (i = 0; i < 10000; i++)
  81     {
  82         if (CLK == val)
  83             return 1;
  84     }
  85
  86     return 0;
  87 }
  88
  89 static inline int syn_get_data(void)
  90 {
  91     DATA_CL;
  92     return DATA;
  93 }
  94
  95 static void syn_wait_guest_flush(void)
  96 {
  97     /* Flush receiving (flushee) state:
  98        handshake until DATA goes high during P3 stage */
  99     if (CLK == LO)
 100     {
 101         ACK_HI;                  /* P1 -> P2 */
 102         syn_wait_clk_change(HI); /* P2 -> P3 */
 103     }
 104
 105     while (syn_get_data() == LO)
 106     {
 107         ACK_HI;                  /* P3 -> P0 */
 108         syn_wait_clk_change(LO); /* P0 -> P1 */
 109         ACK_LO;                  /* P1 -> P2 */
 110         syn_wait_clk_change(HI); /* P2 -> P3 */
 111     }
 112
 113     /* Continue handshaking until back to P0 */
 114     ACK_HI;                      /* P3 -> P0 */
 115 }
 116
 117 static void syn_flush(void)
 118 {
 119     int i;
 120
 121     logf("syn_flush...");
 122
 123     /* Flusher holds DATA low for at least 36 handshake cycles */
 124     DATA_LO;
 125
 126     for (i = 0; i < 36; i++)
 127     {
 128         syn_wait_clk_change(LO); /* P0 -> P1 */
 129         ACK_LO;                  /* P1 -> P2 */
 130         syn_wait_clk_change(HI); /* P2 -> P3 */
 131         ACK_HI;                  /* P3 -> P0 */
 132     }
 133
 134     /* Raise DATA in P1 stage */
 135     syn_wait_clk_change(LO); /* P0 -> P1 */
 136     DATA_HI;
 137
 138     /* After a flush, the flushing device enters a flush-receiving (flushee)
 139        state */
 140     syn_wait_guest_flush();
 141 }
 142
 143 static int syn_send_data(int *data, int len)
 144 {
 145     int i, bit;
 146     int parity = 0;
 147
 148     logf("syn_send_data...");
 149
 150     /* 1. Lower DATA line to issue a request-to-send to guest */
 151     DATA_LO;
 152
 153     /* 2. Wait for guest to lower CLK */
 154     syn_wait_clk_change(LO);
 155
 156     /* 3. Lower ACK (with DATA still low) */
 157     ACK_LO;
 158
 159     /* 4. Wait for guest to raise CLK */
 160     syn_wait_clk_change(HI);
 161
 162     /* 5. Send data */
 163     for (i = 0; i < len; i++)
 164     {
 165        logf("  sending byte: %d", data[i]);
 166
 167         bit = 0;
 168         while (bit < 8)
 169         {
 170             /* 5a. Drive data low if bit is 0, or high if bit is 1 */
 171             if (data[i] & (1 << bit))
 172             {
 173                 DATA_HI;
 174                 parity++;
 175             }
 176             else
 177             {
 178                 DATA_LO;
 179             }
 180             bit++;
 181
 182             /* 5b. Invert ACK to indicate that the data bit is ready */
 183             ACK_HI;
 184
 185             /* 5c. Wait for guest to invert CLK */
 186             syn_wait_clk_change(LO);
 187
 188             /* Repeat for next bit */
 189             if (data[i] & (1 << bit))
 190             {
 191                 DATA_HI;
 192                 parity++;
 193             }
 194             else
 195             {
 196                 DATA_LO;
 197             }
 198             bit++;
 199
 200             ACK_LO;
 201
 202             syn_wait_clk_change(HI);
 203         }
 204     }
 205
 206     /* 7. Transmission termination sequence: */
 207     /* 7a. Host may put parity bit on DATA. Hosts that do not generate
 208            parity should set DATA high. Parity is 1 if there's an odd
 209            number of '1' bits, or 0 if there's an even number of '1' bits. */
 210     parity = parity % 2;
 211     if (parity)
 212     {
 213         DATA_HI;
 214     }
 215     else
 216     {
 217         DATA_LO;
 218     }
 219     logf("  send parity = %d", parity);
 220
 221     /* 7b. Raise ACK to indicate that the optional parity bit is ready */
 222     ACK_HI;
 223
 224     /* 7c. Guest lowers CLK */
 225     syn_wait_clk_change(LO);
 226
 227     /* 7d. Pull DATA high (if parity bit was 0) */
 228     DATA_HI;
 229
 230     /* 7e. Lower ACK to indicate that the stop bit is ready */
 231     ACK_LO;
 232
 233     /* 7f. Guest raises CLK */
 234     syn_wait_clk_change(HI);
 235
 236     /* 7g. If DATA is low, guest is flushing this transfer. Host should
 237            enter the flushee state. */
 238     if (syn_get_data() == LO)
 239     {
 240         logf("  module flushing");
 241
 242         syn_wait_guest_flush();
 243         return -1;
 244     }
 245
 246     /* 7h. Host raises ACK and the link enters the idle state */
 247     ACK_HI;
 248
 249     return len;
 250 }
 251
 252 static int syn_read_data(int *data, int data_len)
 253 {
 254     int i, len, bit, parity, tmp;
 255     int *data_ptr;
 256
 257     logf("syn_read_data...");
 258
 259     /* 1. Guest drives CLK low */
 260     if (CLK != LO)
 261         return 0;
 262
 263     /* 1a. If the host is willing to receive a packet it lowers ACK */
 264     ACK_LO;
 265
 266     /* 2. Guest may issue a request-to-send by lowering DATA. If the
 267           guest decides not to transmit a packet, it may abort the
 268           transmission by not lowering DATA. */
 269
 270     /* 3. The guest raises CLK */
 271     syn_wait_clk_change(HI);
 272
 273     /* 4. If the guest is still driving DATA low, the transfer is commited
 274           to occur. Otherwise, the transfer is aborted. In either case,
 275           the host raises ACK. */
 276     if (syn_get_data() == HI)
 277     {
 278         logf("  read abort");
 279
 280         ACK_HI;
 281         return READ_ERROR;
 282     }
 283     else
 284     {
 285         ACK_HI;
 286     }
 287
 288     /* 5. Read the incoming data packet */
 289     i = 0;
 290     len = 0;
 291     parity = 0;
 292     while (i <= len)
 293     {
 294         bit = 0;
 295
 296         if (i < data_len)
 297             data_ptr = &data[i];
 298         else
 299             data_ptr = &tmp;
 300
 301         *data_ptr = 0;
 302         while (bit < 8)
 303         {
 304             /* 5b. Guset inverts CLK to indicate that data is ready */
 305             syn_wait_clk_change(LO);
 306
 307             /* 5d. Read the data bit from DATA */
 308             if (syn_get_data() == HI)
 309             {
 310                 *data_ptr |= (1 << bit);
 311                 parity++;
 312             }
 313             bit++;
 314
 315             /* 5e. Invert ACK to indicate that data has been read */
 316             ACK_LO;
 317
 318             /* Repeat for next bit */
 319             syn_wait_clk_change(HI);
 320
 321             if (syn_get_data() == HI)
 322             {
 323                 *data_ptr |= (1 << bit);
 324                 parity++;
 325             }
 326             bit++;
 327
 328             ACK_HI;
 329         }
 330
 331         /* First byte is the packet header */
 332         if (i == 0)
 333         {
 334             /* Format control (bit 3) should be 1 */
 335             if (*data_ptr & 0x8)
 336             {
 337                 /* Packet length is bits 0:2 */
 338                 len = *data_ptr & 0x7;
 339                 logf("  packet length = %d", len);
 340             }
 341             else
 342             {
 343                 logf("  invalid format ctrl bit");
 344                 return READ_ERROR;
 345             }
 346         }
 347
 348         i++;
 349     }
 350
 351     /* 7. Transmission termination cycle */
 352     /* 7a. The guest generates a parity bit on DATA */
 353     /* 7b. The host waits for guest to lower CLK */
 354     syn_wait_clk_change(LO);
 355
 356     /* 7c. The host verifies the parity bit is correct */
 357     parity = parity % 2;
 358     logf("  parity check: %d / %d", syn_get_data(), parity);
 359
 360     /* TODO: parity error handling */
 361
 362     /* 7d. The host lowers ACK */
 363     ACK_LO;
 364
 365     /* 7e. The host waits for the guest to raise CLK indicating
 366            that the stop bit is ready */
 367     syn_wait_clk_change(HI);
 368
 369     /* 7f. The host reads DATA and verifies that it is 1 */
 370     if (syn_get_data() == LO)
 371     {
 372         logf("  framing error");
 373
 374         ACK_HI;
 375         return READ_ERROR;
 376     }
 377
 378     ACK_HI;
 379
 380     return len;
 381 }
 382
 383 int syn_read_device(int *data, int len)
 384 {
 385     int i;
 386     int ret = READ_ERROR;
 387
 388     for (i = 0; i < READ_RETRY; i++)
 389     {
 390         if (syn_wait_clk_change(LO))
 391         {
 392             /* module is sending data */
 393             ret = syn_read_data(data, len);
 394             if (ret != READ_ERROR)
 395                 return ret;
 396
 397             syn_flush();
 398         }
 399         else
 400         {
 401             /* module is idle */
 402             return 0;
 403         }
 404     }
 405
 406     return ret;
 407 }
 408
 409 static int syn_reset(void)
 410 {
 411     int val, id;
 412     int data[2];
 413
 414     logf("syn_reset...");
 415
 416     /* reset module 0 */
 417     val = (0 << 4) | (1 << 3) | 0;
 418     syn_send_data(&val, 1);
 419
 420     val = syn_read_device(data, 2);
 421     if (val == 1)
 422     {
 423         val = data[0] & 0xff;      /* packet header */
 424         id = (data[1] >> 4) & 0xf; /* packet id */
 425         if ((val == MEP_HELLO_HEADER) && (id == MEP_HELLO_ID))
 426         {
 427             logf("  module 0 reset");
 428             return 1;
 429         }
 430     }
 431
 432     logf("  reset failed");
 433     return 0;
 434 }
 435
 436 int syn_init(void)
 437 {
 438     syn_flush();
 439     return syn_reset();
 440 }
 441
 442 #ifdef ROCKBOX_HAS_LOGF
 443 void syn_info(void)
 444 {
 445     int i, val;
 446     int data[8];
 447
 448     logf("syn_info...");
 449
 450     /* module base info */
 451     logf("module base info:");
 452     data[0] = MEP_READ;
 453     data[1] = 0x80;
 454     syn_send_data(data, 2);
 455     val = syn_read_device(data, 8);
 456     if (val > 0)
 457     {
 458         for (i = 0; i < 8; i++)
 459             logf("  data[%d] = 0x%02x", i, data[i]);
 460     }
 461
 462     /* module product info */
 463     logf("module product info:");
 464     data[0] = MEP_READ;
 465     data[1] = 0x81;
 466     syn_send_data(data, 2);
 467     val = syn_read_device(data, 8);
 468     if (val > 0)
 469     {
 470         for (i = 0; i < 8; i++)
 471             logf("  data[%d] = 0x%02x", i, data[i]);
 472     }
 473
 474     /* module serialization */
 475     logf("module serialization:");
 476     data[0] = MEP_READ;
 477     data[1] = 0x82;
 478     syn_send_data(data, 2);
 479     val = syn_read_device(data, 8);
 480     if (val > 0)
 481     {
 482         for (i = 0; i < 8; i++)
 483             logf("  data[%d] = 0x%02x", i, data[i]);
 484     }
 485
 486     /* 1-D sensor info */
 487     logf("1-d sensor info:");
 488     data[0] = MEP_READ;
 489     data[1] = 0x80 + 0x20;
 490     syn_send_data(data, 2);
 491     val = syn_read_device(data, 8);
 492     if (val > 0)
 493     {
 494         for (i = 0; i < 8; i++)
 495             logf("  data[%d] = 0x%02x", i, data[i]);
 496     }
 497 }
 498 #endif