as3525*: make udelay() be a simple busy loop
[kugel-rb.git] / firmware / target / arm / as3525 / usb-drv-as3525.c
blob0b69e8953b9966d0db1132088c6a35c60b9c4a4a
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright © 2010 Tobias Diedrich
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
22 #include "system.h"
23 #include "usb.h"
24 #include "usb_drv.h"
25 #include "as3525.h"
26 #include "clock-target.h"
27 #include "ascodec.h"
28 #include "as3514.h"
29 #include <stdbool.h>
30 #include "panic.h"
31 /*#define LOGF_ENABLE*/
32 #include "logf.h"
33 #include "usb_ch9.h"
34 #include "usb_core.h"
35 #include "string.h"
37 #if defined(USE_ROCKBOX_USB)
39 #include "usb-drv-as3525.h"
41 static struct usb_endpoint endpoints[USB_NUM_EPS][2];
44 * dma/setup descriptors and buffers should avoid sharing
45 * a cacheline with other data.
46 * dmadescs may share with each other, since we only access them uncached.
48 static struct usb_dev_dma_desc dmadescs[USB_NUM_EPS][2] __attribute__((aligned(32)));
49 /* reuse unused EP2 OUT descriptor here */
50 static struct usb_dev_setup_buf *setup_desc = (void*)&dmadescs[2][1];
52 #if AS3525_MCLK_SEL != AS3525_CLK_PLLB
53 static inline void usb_enable_pll(void)
55 CGU_COUNTB = CGU_LOCK_CNT;
56 CGU_PLLB = AS3525_PLLB_SETTING;
57 CGU_PLLBSUP = 0; /* enable PLLB */
58 while(!(CGU_INTCTRL & CGU_PLLB_LOCK)); /* wait until PLLB is locked */
61 static inline void usb_disable_pll(void)
63 CGU_PLLBSUP = CGU_PLL_POWERDOWN;
65 #else
66 static inline void usb_enable_pll(void)
70 static inline void usb_disable_pll(void)
73 #endif /* AS3525_MCLK_SEL != AS3525_CLK_PLLB */
75 void usb_attach(void)
77 usb_enable(true);
80 /* delay is in milliseconds */
81 static inline void usb_delay(int delay)
83 udelay(1000 * delay);
86 static void usb_phy_on(void)
88 /* PHY clock */
89 CGU_USB = 1<<5 /* enable */
90 | (CLK_DIV(AS3525_PLLB_FREQ, 48000000) / 2) << 2
91 | 2; /* source = PLLB */
93 /* UVDD on */
94 ascodec_write(AS3515_USB_UTIL, ascodec_read(AS3515_USB_UTIL) | (1<<4));
95 usb_delay(100);
97 /* reset */
98 CCU_SRC = CCU_SRC_USB_AHB_EN|CCU_SRC_USB_PHY_EN;
99 CCU_SRL = CCU_SRL_MAGIC_NUMBER;
100 usb_delay(1);
101 CCU_SRC = CCU_SRC_USB_AHB_EN;
102 usb_delay(1);
103 CCU_SRC = CCU_SRL = 0;
105 USB_GPIO_CSR = USB_GPIO_TX_ENABLE_N
106 | USB_GPIO_TX_BIT_STUFF_EN
107 | USB_GPIO_XO_ON
108 | USB_GPIO_CLK_SEL10; /* 0x06180000; */
111 static void usb_phy_suspend(void)
113 USB_GPIO_CSR |= USB_GPIO_ASESSVLD_EXT |
114 USB_GPIO_BSESSVLD_EXT |
115 USB_GPIO_VBUS_VLD_EXT;
116 usb_delay(3);
117 USB_GPIO_CSR |= USB_GPIO_VBUS_VLD_EXT_SEL;
118 usb_delay(10);
121 static void usb_phy_resume(void)
123 USB_GPIO_CSR &= ~(USB_GPIO_ASESSVLD_EXT |
124 USB_GPIO_BSESSVLD_EXT |
125 USB_GPIO_VBUS_VLD_EXT);
126 usb_delay(3);
127 USB_GPIO_CSR &= ~USB_GPIO_VBUS_VLD_EXT_SEL;
128 usb_delay(10);
131 static void setup_desc_init(struct usb_dev_setup_buf *desc)
133 struct usb_dev_setup_buf *uc_desc = AS3525_UNCACHED_ADDR(desc);
135 uc_desc->status = USB_DMA_DESC_BS_HST_RDY;
136 uc_desc->resv = 0xffffffff;
137 uc_desc->data1 = 0xffffffff;
138 uc_desc->data2 = 0xffffffff;
141 static void dma_desc_init(int ep, int dir)
143 struct usb_dev_dma_desc *desc = &dmadescs[ep][dir];
144 struct usb_dev_dma_desc *uc_desc = AS3525_UNCACHED_ADDR(desc);
146 endpoints[ep][dir].uc_desc = uc_desc;
148 uc_desc->status = USB_DMA_DESC_BS_DMA_DONE | \
149 USB_DMA_DESC_LAST | \
150 USB_DMA_DESC_ZERO_LEN;
151 uc_desc->resv = 0xffffffff;
152 uc_desc->data_ptr = 0;
153 uc_desc->next_desc = 0;
156 static void reset_endpoints(int init)
158 int i;
161 * OUT EP 2 is an alias for OUT EP 0 on this HW!
163 * Resonates with "3 bidirectional- plus 1 in-endpoints in device mode"
164 * from the datasheet, but why ep2 and not ep3?
166 * Reserve it here so we will skip over it in request_endpoint().
168 endpoints[2][1].state |= EP_STATE_ALLOCATED;
170 for(i = 0; i < USB_NUM_EPS; i++) {
172 * LS: 8 (control), no bulk available
173 * FS: 64 (control), 64 (bulk)
174 * HS: 64 (control), 512 (bulk)
175 * TODO: switch depending on speed.
177 int mps = i == 0 ? 64 : 512;
179 if (init) {
180 endpoints[i][0].state = 0;
181 wakeup_init(&endpoints[i][0].complete);
183 if (i != 2) { /* Skip the OUT EP0 alias */
184 endpoints[i][1].state = 0;
185 wakeup_init(&endpoints[i][1].complete);
186 USB_OEP_SUP_PTR(i) = 0;
190 dma_desc_init(i, 0);
191 USB_IEP_CTRL (i) = USB_EP_CTRL_FLUSH|USB_EP_CTRL_SNAK;
192 USB_IEP_MPS (i) = mps; /* in bytes */
193 /* We don't care about the 'IN token received' event */
194 USB_IEP_STS_MASK(i) = USB_EP_STAT_IN; /* OF: 0x840 */
195 USB_IEP_TXFSIZE (i) = mps/2; /* in dwords => mps*2 bytes */
196 USB_IEP_STS (i) = 0xffffffff; /* clear status */
197 USB_IEP_DESC_PTR(i) = 0;
199 if (i != 2) { /* Skip the OUT EP0 alias */
200 dma_desc_init(i, 1);
201 USB_OEP_CTRL (i) = USB_EP_CTRL_FLUSH|USB_EP_CTRL_SNAK;
202 USB_OEP_MPS (i) = (mps/2 << 23) | mps;
203 USB_OEP_STS_MASK(i) = 0x0000; /* OF: 0x1800 */
204 USB_OEP_RXFR (i) = 0; /* Always 0 in OF trace? */
205 USB_OEP_STS (i) = 0xffffffff; /* clear status */
206 USB_OEP_DESC_PTR(i) = 0;
210 setup_desc_init(setup_desc);
211 USB_OEP_SUP_PTR(0) = (int)setup_desc;
214 void usb_drv_init(void)
216 logf("usb_drv_init() !!!!\n");
218 usb_enable_pll();
220 /* length regulator: normal operation */
221 ascodec_write(AS3514_CVDD_DCDC3, ascodec_read(AS3514_CVDD_DCDC3) | 1<<2);
223 /* AHB part */
224 CGU_PERI |= CGU_USB_CLOCK_ENABLE;
226 /* reset AHB */
227 CCU_SRC = CCU_SRC_USB_AHB_EN;
228 CCU_SRL = CCU_SRL_MAGIC_NUMBER;
229 usb_delay(1);
230 CCU_SRC = CCU_SRL = 0;
232 USB_GPIO_CSR = USB_GPIO_TX_ENABLE_N
233 | USB_GPIO_TX_BIT_STUFF_EN
234 | USB_GPIO_XO_ON
235 | USB_GPIO_CLK_SEL10; /* 0x06180000; */
237 /* bug workaround according to linux patch */
238 USB_DEV_CFG = (USB_DEV_CFG & ~3) | 1; /* full speed */
240 /* enable soft disconnect */
241 USB_DEV_CTRL |= USB_DEV_CTRL_SOFT_DISCONN;
243 usb_phy_on();
244 usb_phy_suspend();
245 USB_DEV_CTRL |= USB_DEV_CTRL_SOFT_DISCONN;
247 /* We don't care about SVC or SOF events */
248 /* Right now we don't handle suspend, so mask those too */
249 USB_DEV_INTR_MASK = USB_DEV_INTR_SVC |
250 USB_DEV_INTR_SOF |
251 USB_DEV_INTR_USB_SUSPEND |
252 USB_DEV_INTR_EARLY_SUSPEND;
254 USB_DEV_CFG = USB_DEV_CFG_STAT_ACK |
255 USB_DEV_CFG_UNI_DIR |
256 USB_DEV_CFG_PI_16BIT |
257 USB_DEV_CFG_HS |
258 USB_DEV_CFG_SELF_POWERED |
259 USB_DEV_CFG_CSR_PRG |
260 USB_DEV_CFG_PHY_ERR_DETECT;
262 USB_DEV_CTRL = USB_DEV_CTRL_BLEN_1DWORD |
263 USB_DEV_CTRL_DESC_UPDATE |
264 USB_DEV_CTRL_THRES_ENABLE |
265 USB_DEV_CTRL_RDE |
266 0x04000000;
268 USB_DEV_EP_INTR_MASK &= ~((1<<0) | (1<<16)); /* ep 0 */
270 reset_endpoints(1);
272 /* clear pending interrupts */
273 USB_DEV_EP_INTR = 0xffffffff;
274 USB_DEV_INTR = 0xffffffff;
276 VIC_INT_ENABLE = INTERRUPT_USB;
278 usb_phy_resume();
279 USB_DEV_CTRL &= ~USB_DEV_CTRL_SOFT_DISCONN;
281 USB_GPIO_CSR = USB_GPIO_TX_ENABLE_N
282 | USB_GPIO_TX_BIT_STUFF_EN
283 | USB_GPIO_XO_ON
284 | USB_GPIO_HS_INTR
285 | USB_GPIO_CLK_SEL10; /* 0x06180000; */
289 void usb_drv_exit(void)
291 USB_DEV_CTRL |= (1<<10); /* soft disconnect */
293 * mask all interrupts _before_ writing to VIC_INT_EN_CLEAR,
294 * or else the core might latch the interrupt while
295 * the write ot VIC_INT_EN_CLEAR is in the pipeline and
296 * so cause a fake spurious interrupt.
298 USB_DEV_EP_INTR_MASK = 0xffffffff;
299 USB_DEV_INTR_MASK = 0xffffffff;
300 VIC_INT_EN_CLEAR = INTERRUPT_USB;
301 CGU_USB &= ~(1<<5);
302 CGU_PERI &= ~CGU_USB_CLOCK_ENABLE;
303 /* Disable UVDD generating LDO */
304 ascodec_write(AS3515_USB_UTIL, ascodec_read(AS3515_USB_UTIL) & ~(1<<4));
305 usb_disable_pll();
306 logf("usb_drv_exit() !!!!\n");
309 int usb_drv_port_speed(void)
311 return (USB_DEV_STS & USB_DEV_STS_MASK_SPD) ? 0 : 1;
314 int usb_drv_request_endpoint(int type, int dir)
316 int d = dir == USB_DIR_IN ? 0 : 1;
317 int i = 1; /* skip the control EP */
319 for(; i < USB_NUM_EPS; i++) {
320 if (endpoints[i][d].state & EP_STATE_ALLOCATED)
321 continue;
323 endpoints[i][d].state |= EP_STATE_ALLOCATED;
325 if (dir == USB_DIR_IN) {
326 USB_IEP_CTRL(i) = USB_EP_CTRL_FLUSH |
327 USB_EP_CTRL_SNAK |
328 USB_EP_CTRL_ACT |
329 (type << 4);
330 USB_DEV_EP_INTR_MASK &= ~(1<<i);
331 } else {
332 USB_OEP_CTRL(i) = USB_EP_CTRL_FLUSH |
333 USB_EP_CTRL_SNAK |
334 USB_EP_CTRL_ACT |
335 (type << 4);
336 USB_DEV_EP_INTR_MASK &= ~(1<<(16+i));
338 /* logf("usb_drv_request_endpoint(%d, %d): returning %02x\n", type, dir, i | dir); */
339 return i | dir;
342 logf("usb_drv_request_endpoint(%d, %d): no free endpoint found\n", type, dir);
343 return -1;
346 void usb_drv_release_endpoint(int ep)
348 int i = ep & 0x7f;
349 int d = ep & USB_DIR_IN ? 0 : 1;
351 if (i >= USB_NUM_EPS)
352 return;
354 * Check for control EP and ignore it.
355 * Unfortunately the usb core calls
356 * usb_drv_release_endpoint() for ep=0..(USB_NUM_ENDPOINTS-1),
357 * but doesn't request a new control EP after that...
359 if (i == 0 || /* Don't mask control EP */
360 (i == 2 && d == 1)) /* See reset_endpoints(), EP2_OUT == EP0_OUT */
361 return;
363 if (!(endpoints[i][d].state & EP_STATE_ALLOCATED))
364 return;
366 /* logf("usb_drv_release_endpoint(%d, %d)\n", i, d); */
367 endpoints[i][d].state = 0;
368 USB_DEV_EP_INTR_MASK |= (1<<(16*d+i));
369 USB_EP_CTRL(i, !d) = USB_EP_CTRL_FLUSH | USB_EP_CTRL_SNAK;
372 void usb_drv_cancel_all_transfers(void)
374 logf("usb_drv_cancel_all_transfers()\n");
375 return;
377 int flags = disable_irq_save();
378 reset_endpoints(0);
379 restore_irq(flags);
382 int usb_drv_recv(int ep, void *ptr, int len)
384 struct usb_dev_dma_desc *uc_desc = endpoints[ep][1].uc_desc;
386 ep &= 0x7f;
387 logf("usb_drv_recv(%d,%x,%d)\n", ep, (int)ptr, len);
389 if ((int)ptr & 31) {
390 logf("addr %08x not aligned!\n", (int)ptr);
393 endpoints[ep][1].state |= EP_STATE_BUSY;
394 endpoints[ep][1].len = len;
395 endpoints[ep][1].rc = -1;
397 /* remove data buffer from cache */
398 invalidate_dcache();
400 /* DMA setup */
401 uc_desc->status = USB_DMA_DESC_BS_HST_RDY |
402 USB_DMA_DESC_LAST |
403 len;
404 if (len == 0) {
405 uc_desc->status |= USB_DMA_DESC_ZERO_LEN;
406 uc_desc->data_ptr = 0;
407 } else {
408 uc_desc->data_ptr = ptr;
410 USB_OEP_DESC_PTR(ep) = (int)&dmadescs[ep][1];
411 USB_OEP_STS(ep) = USB_EP_STAT_OUT_RCVD; /* clear status */
412 USB_OEP_CTRL(ep) |= USB_EP_CTRL_CNAK;
414 return 0;
417 #if defined(LOGF_ENABLE)
418 static char hexbuf[1025];
419 static char hextab[16] = "0123456789abcdef";
421 char *make_hex(char *data, int len)
423 int i;
424 if (!((int)data & 0x40000000))
425 data = AS3525_UNCACHED_ADDR(data); /* don't pollute the cache */
427 if (len > 512)
428 len = 512;
430 for (i=0; i<len; i++) {
431 hexbuf[2*i ] = hextab[(unsigned char)data[i] >> 4 ];
432 hexbuf[2*i+1] = hextab[(unsigned char)data[i] & 0xf];
434 hexbuf[2*i] = 0;
436 return hexbuf;
438 #endif
440 void ep_send(int ep, void *ptr, int len)
442 struct usb_dev_dma_desc *uc_desc = endpoints[ep][0].uc_desc;
444 endpoints[ep][0].state |= EP_STATE_BUSY;
445 endpoints[ep][0].len = len;
446 endpoints[ep][0].rc = -1;
448 /* Make sure data is committed to memory */
449 clean_dcache();
451 logf("xx%s\n", make_hex(ptr, len));
453 uc_desc->status = USB_DMA_DESC_BS_HST_RDY |
454 USB_DMA_DESC_LAST |
455 len;
456 if (len == 0)
457 uc_desc->status |= USB_DMA_DESC_ZERO_LEN;
459 uc_desc->data_ptr = ptr;
461 USB_IEP_DESC_PTR(ep) = (int)&dmadescs[ep][0];
462 USB_IEP_STS(ep) = 0xffffffff; /* clear status */
463 /* start transfer */
464 USB_IEP_CTRL(ep) |= USB_EP_CTRL_CNAK | USB_EP_CTRL_PD;
465 /* HW automatically sets NAK bit later */
468 int usb_drv_send(int ep, void *ptr, int len)
470 logf("usb_drv_send(%d,%x,%d): ", ep, (int)ptr, len);
472 ep &= 0x7f;
473 ep_send(ep, ptr, len);
474 while (endpoints[ep][0].state & EP_STATE_BUSY)
475 wakeup_wait(&endpoints[ep][0].complete, TIMEOUT_BLOCK);
477 return endpoints[ep][0].rc;
480 int usb_drv_send_nonblocking(int ep, void *ptr, int len)
482 logf("usb_drv_send_nonblocking(%d,%x,%d): ", ep, (int)ptr, len);
483 ep &= 0x7f;
484 endpoints[ep][0].state |= EP_STATE_ASYNC;
485 ep_send(ep, ptr, len);
486 return 0;
489 static void handle_in_ep(int ep)
491 int ep_sts = USB_IEP_STS(ep) & ~USB_IEP_STS_MASK(ep);
493 if (ep > 3)
494 panicf("in_ep > 3?!");
496 USB_IEP_STS(ep) = ep_sts; /* ack */
498 if (ep_sts & USB_EP_STAT_BNA) { /* Buffer was not set up */
499 logf("ep%d IN, status %x (BNA)\n", ep, ep_sts);
500 panicf("ep%d IN 0x%x (BNA)", ep, ep_sts);
503 if (ep_sts & USB_EP_STAT_TDC) {
504 endpoints[ep][0].state &= ~EP_STATE_BUSY;
505 endpoints[ep][0].rc = 0;
506 logf("EP%d %x %stx done len %x stat %08x\n",
507 ep, ep_sts, endpoints[ep][0].state & EP_STATE_ASYNC ? "async " :"",
508 endpoints[ep][0].len,
509 endpoints[ep][0].uc_desc->status);
510 if (endpoints[ep][0].state & EP_STATE_ASYNC) {
511 endpoints[ep][0].state &= ~EP_STATE_ASYNC;
512 usb_core_transfer_complete(ep, USB_DIR_IN, 0, endpoints[ep][0].len);
513 } else {
514 wakeup_signal(&endpoints[ep][0].complete);
516 ep_sts &= ~USB_EP_STAT_TDC;
519 if (ep_sts) {
520 logf("ep%d IN, hwstat %lx, epstat %x\n", ep, USB_IEP_STS(ep), endpoints[ep][0].state);
521 panicf("ep%d IN 0x%x", ep, ep_sts);
524 /* HW automatically disables RDE, re-enable it */
525 /* But this an IN ep, I wonder... */
526 USB_DEV_CTRL |= USB_DEV_CTRL_RDE;
529 static void handle_out_ep(int ep)
531 struct usb_ctrlrequest *req = (void*)AS3525_UNCACHED_ADDR(&setup_desc->data1);
532 int ep_sts = USB_OEP_STS(ep) & ~USB_OEP_STS_MASK(ep);
533 struct usb_dev_dma_desc *uc_desc = endpoints[ep][1].uc_desc;
535 if (ep > 3)
536 panicf("out_ep > 3!?");
538 USB_OEP_STS(ep) = ep_sts; /* ACK */
540 if (ep_sts & USB_EP_STAT_BNA) { /* Buffer was not set up */
541 logf("ep%d OUT, status %x (BNA)\n", ep, ep_sts);
542 panicf("ep%d OUT 0x%x (BNA)", ep, ep_sts);
545 if (ep_sts & USB_EP_STAT_OUT_RCVD) {
546 int dma_sts = uc_desc->status;
547 int dma_len = dma_sts & 0xffff;
549 if (!(dma_sts & USB_DMA_DESC_ZERO_LEN)) {
550 logf("EP%d OUT token, st:%08x len:%d frm:%x data=%s epstate=%d\n",
551 ep, dma_sts & 0xf8000000, dma_len, (dma_sts >> 16) & 0x7ff,
552 make_hex(uc_desc->data_ptr, dma_len), endpoints[ep][1].state);
554 * If parts of the just dmaed range are in cache, dump them now.
556 dump_dcache_range(uc_desc->data_ptr, dma_len);
557 } else{
558 logf("EP%d OUT token, st:%08x frm:%x (no data)\n", ep,
559 dma_mst, dma_frm);
562 if (endpoints[ep][1].state & EP_STATE_BUSY) {
563 endpoints[ep][1].state &= ~EP_STATE_BUSY;
564 endpoints[ep][1].rc = 0;
565 usb_core_transfer_complete(ep, USB_DIR_OUT, 0, dma_len);
566 } else {
567 logf("EP%d OUT, but no one was listening?\n", ep);
570 USB_OEP_CTRL(ep) |= USB_EP_CTRL_SNAK; /* make sure NAK is set */
572 ep_sts &= ~USB_EP_STAT_OUT_RCVD;
575 if (ep_sts & USB_EP_STAT_SETUP_RCVD) {
576 static struct usb_ctrlrequest req_copy;
578 req_copy = *req;
579 logf("t%ld:got SETUP packet: type=%d req=%d val=%d ind=%d len=%d\n",
580 current_tick,
581 req->bRequestType,
582 req->bRequest,
583 req->wValue,
584 req->wIndex,
585 req->wLength);
587 usb_core_control_request(&req_copy);
588 setup_desc_init(setup_desc);
590 ep_sts &= ~USB_EP_STAT_SETUP_RCVD;
593 if (ep_sts) {
594 logf("ep%d OUT, status %x\n", ep, ep_sts);
595 panicf("ep%d OUT 0x%x", ep, ep_sts);
598 /* HW automatically disables RDE, re-enable it */
599 /* THEORY: Because we only set up one DMA buffer... */
600 USB_DEV_CTRL |= USB_DEV_CTRL_RDE;
603 /* interrupt service routine */
604 void INT_USB(void)
606 int ep = USB_DEV_EP_INTR & ~USB_DEV_EP_INTR_MASK;
607 int intr = USB_DEV_INTR & ~USB_DEV_INTR_MASK;
609 /* ACK interrupt sources */
610 USB_DEV_EP_INTR = ep;
611 USB_DEV_INTR = intr;
613 /* Handle endpoint interrupts */
614 while (ep) {
615 int onebit = 31-__builtin_clz(ep);
617 if (onebit < 16) handle_in_ep(onebit);
618 else handle_out_ep(onebit-16);
620 ep &= ~(1 << onebit);
623 /* Handle general device interrupts */
624 if (intr) {
625 if (intr & USB_DEV_INTR_SET_INTERFACE) {/* SET_INTERFACE received */
626 logf("set interface\n");
627 panicf("set interface");
628 intr &= ~USB_DEV_INTR_SET_INTERFACE;
630 if (intr & USB_DEV_INTR_SET_CONFIG) {/* SET_CONFIGURATION received */
632 * This is handled in HW, we have to fake a request here
633 * for usb_core.
635 static struct usb_ctrlrequest set_config = {
636 bRequestType: USB_TYPE_STANDARD | USB_RECIP_DEVICE,
637 bRequest: USB_REQ_SET_CONFIGURATION,
638 wValue: 0,
639 wIndex: 0,
640 wLength: 0,
643 logf("set config\n");
645 set_config.wValue = USB_DEV_STS & USB_DEV_STS_MASK_CFG;
646 usb_core_control_request(&set_config);
648 /* Tell the HW we handled the request */
649 USB_DEV_CTRL |= USB_DEV_CTRL_APCSR_DONE;
650 intr &= ~USB_DEV_INTR_SET_CONFIG;
652 if (intr & USB_DEV_INTR_EARLY_SUSPEND) {/* idle >3ms detected */
653 logf("usb idle\n");
654 intr &= ~USB_DEV_INTR_EARLY_SUSPEND;
656 if (intr & USB_DEV_INTR_USB_RESET) {/* usb reset from host? */
657 logf("usb reset\n");
658 reset_endpoints(1);
659 usb_core_bus_reset();
660 intr &= ~USB_DEV_INTR_USB_RESET;
662 if (intr & USB_DEV_INTR_USB_SUSPEND) {/* suspend req from host? */
663 logf("usb suspend\n");
664 intr &= ~USB_DEV_INTR_USB_SUSPEND;
666 if (intr & USB_DEV_INTR_SOF) {/* sof received */
667 logf("sof\n");
668 intr &= ~USB_DEV_INTR_SOF;
670 if (intr & USB_DEV_INTR_SVC) {/* device status changed */
671 logf("svc: %08x otg: %08x\n", (int)USB_DEV_STS, (int)USB_OTG_CSR);
672 intr &= ~USB_DEV_INTR_SVC;
674 if (intr & USB_DEV_INTR_ENUM_DONE) {/* speed enumeration complete */
675 int spd = USB_DEV_STS & USB_DEV_STS_MASK_SPD; /* Enumerated Speed */
677 logf("speed enum complete: ");
678 if (spd == USB_DEV_STS_SPD_HS) logf("hs\n");
679 if (spd == USB_DEV_STS_SPD_FS) logf("fs\n");
680 if (spd == USB_DEV_STS_SPD_LS) logf("ls\n");
682 USB_PHY_EP0_INFO = 0x00200000 |
683 USB_CSR_DIR_OUT |
684 USB_CSR_TYPE_CTL;
685 USB_PHY_EP1_INFO = 0x00200000 |
686 USB_CSR_DIR_IN |
687 USB_CSR_TYPE_CTL;
688 USB_PHY_EP2_INFO = 0x00200001 |
689 USB_CSR_DIR_IN |
690 USB_CSR_TYPE_BULK;
691 USB_PHY_EP3_INFO = 0x00200001 |
692 USB_CSR_DIR_IN |
693 USB_CSR_TYPE_BULK;
694 USB_DEV_CTRL |= USB_DEV_CTRL_APCSR_DONE;
695 USB_IEP_CTRL(0) |= USB_EP_CTRL_ACT;
696 USB_OEP_CTRL(0) |= USB_EP_CTRL_ACT;
697 intr &= ~USB_DEV_INTR_ENUM_DONE;
699 if (intr)
700 panicf("usb devirq 0x%x", intr);
703 if (!(USB_DEV_CTRL & USB_DEV_CTRL_RDE)){
704 logf("re-enabling receive DMA\n");
705 USB_DEV_CTRL |= USB_DEV_CTRL_RDE;
710 /* (not essential? , not implemented in usb-tcc.c) */
711 void usb_drv_set_test_mode(int mode)
713 (void)mode;
716 /* handled internally by controller */
717 void usb_drv_set_address(int address)
719 (void)address;
722 void usb_drv_stall(int ep, bool stall, bool in)
724 if (stall) USB_EP_CTRL(ep, in) |= USB_EP_CTRL_STALL;
725 else USB_EP_CTRL(ep, in) &= ~USB_EP_CTRL_STALL;
728 bool usb_drv_stalled(int ep, bool in)
730 return USB_EP_CTRL(ep, in) & USB_EP_CTRL_STALL;
733 #else
735 void usb_attach(void)
739 void usb_drv_init(void)
743 void usb_drv_exit(void)
747 int usb_drv_port_speed(void)
749 return 0;
752 int usb_drv_request_endpoint(int type, int dir)
754 (void)type;
755 (void)dir;
757 return -1;
760 void usb_drv_release_endpoint(int ep)
762 (void)ep;
765 void usb_drv_cancel_all_transfers(void)
769 void usb_drv_set_test_mode(int mode)
771 (void)mode;
774 void usb_drv_set_address(int address)
776 (void)address;
779 int usb_drv_recv(int ep, void *ptr, int len)
781 (void)ep;
782 (void)ptr;
783 (void)len;
785 return -1;
788 int usb_drv_send(int ep, void *ptr, int len)
790 (void)ep;
791 (void)ptr;
792 (void)len;
794 return -1;
797 int usb_drv_send_nonblocking(int ep, void *ptr, int len)
799 (void)ep;
800 (void)ptr;
801 (void)len;
803 return -1;
806 void usb_drv_stall(int ep, bool stall, bool in)
808 (void)ep;
809 (void)stall;
810 (void)in;
813 bool usb_drv_stalled(int ep, bool in)
815 (void)ep;
816 (void)in;
818 return 0;
821 #endif