firmware/export/mcf5249.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2004 by Linus Nielsen Feltzing
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __MCF5249_H__
  22 #define __MCF5249_H__
  23
  24 #define MBAR  0x40000000
  25 #define MBAR2 0x80000000
  26
  27 #define RSR   (*(volatile unsigned char *)(MBAR + 0x000))
  28 #define SYPCR (*(volatile unsigned char *)(MBAR + 0x001))
  29 #define SWIVR (*(volatile unsigned char *)(MBAR + 0x002))
  30 #define SWSR  (*(volatile unsigned char *)(MBAR + 0x003))
  31
  32 #define MPARK (*(volatile unsigned char *)(MBAR + 0x00c))
  33
  34 #define IPR   (*(volatile unsigned long *)(MBAR + 0x040))
  35 #define IMR   (*(volatile unsigned long *)(MBAR + 0x044))
  36 #define ICR0  (*(volatile unsigned char *)(MBAR + 0x04c))
  37 #define ICR1  (*(volatile unsigned char *)(MBAR + 0x04d))
  38 #define ICR2  (*(volatile unsigned char *)(MBAR + 0x04e))
  39 #define ICR3  (*(volatile unsigned char *)(MBAR + 0x04f))
  40 #define ICR4  (*(volatile unsigned char *)(MBAR + 0x050))
  41 #define ICR5  (*(volatile unsigned char *)(MBAR + 0x051))
  42 #define ICR6  (*(volatile unsigned char *)(MBAR + 0x052))
  43 #define ICR7  (*(volatile unsigned char *)(MBAR + 0x053))
  44 #define ICR8  (*(volatile unsigned char *)(MBAR + 0x054))
  45 #define ICR9  (*(volatile unsigned char *)(MBAR + 0x055))
  46 #define ICR10 (*(volatile unsigned char *)(MBAR + 0x056))
  47 #define ICR11 (*(volatile unsigned char *)(MBAR + 0x057))
  48
  49 #define CSAR0 (*(volatile unsigned long *)(MBAR + 0x080))
  50 #define CSMR0 (*(volatile unsigned long *)(MBAR + 0x084))
  51 #define CSCR0 (*(volatile unsigned long *)(MBAR + 0x088))
  52 #define CSAR1 (*(volatile unsigned long *)(MBAR + 0x08c))
  53 #define CSMR1 (*(volatile unsigned long *)(MBAR + 0x090))
  54 #define CSCR1 (*(volatile unsigned long *)(MBAR + 0x094))
  55 #define CSAR2 (*(volatile unsigned long *)(MBAR + 0x098))
  56 #define CSMR2 (*(volatile unsigned long *)(MBAR + 0x09c))
  57 #define CSCR2 (*(volatile unsigned long *)(MBAR + 0x0a0))
  58 #define CSAR3 (*(volatile unsigned long *)(MBAR + 0x0a4))
  59 #define CSMR3 (*(volatile unsigned long *)(MBAR + 0x0a8))
  60 #define CSCR3 (*(volatile unsigned long *)(MBAR + 0x0ac))
  61
  62 #define DCR   (*(volatile unsigned short *)(MBAR + 0x100))
  63 #define DACR0 (*(volatile unsigned long *)(MBAR + 0x108))
  64 #define DMR0  (*(volatile unsigned long *)(MBAR + 0x10c))
  65 #define DACR1 (*(volatile unsigned long *)(MBAR + 0x110))
  66 #define DMR1  (*(volatile unsigned long *)(MBAR + 0x114))
  67 #define TMR0  (*(volatile unsigned short *)(MBAR + 0x140))
  68 #define TRR0  (*(volatile unsigned short *)(MBAR + 0x144))
  69 #define TCR0  (*(volatile unsigned short *)(MBAR + 0x148))
  70 #define TCN0  (*(volatile unsigned short *)(MBAR + 0x14c))
  71 #define TER0  (*(volatile unsigned char *)(MBAR + 0x151))
  72 #define TMR1  (*(volatile unsigned short *)(MBAR + 0x180))
  73 #define TRR1  (*(volatile unsigned short *)(MBAR + 0x184))
  74 #define TCR1  (*(volatile unsigned short *)(MBAR + 0x188))
  75 #define TCN1  (*(volatile unsigned short *)(MBAR + 0x18c))
  76 #define TER1  (*(volatile unsigned char *)(MBAR + 0x191))
  77
  78 #define UMR0   (*(volatile unsigned char *)(MBAR + 0x1c0))
  79 #define USR0   (*(volatile unsigned char *)(MBAR + 0x1c4))
  80 #define UCSR0  (*(volatile unsigned char *)(MBAR + 0x1c4))
  81 #define UCR0   (*(volatile unsigned char *)(MBAR + 0x1c8))
  82 #define URB0   (*(volatile unsigned char *)(MBAR + 0x1cc))
  83 #define UTB0   (*(volatile unsigned char *)(MBAR + 0x1cc))
  84 #define UIPCR0 (*(volatile unsigned char *)(MBAR + 0x1d0))
  85 #define UACR0  (*(volatile unsigned char *)(MBAR + 0x1d0))
  86 #define UISR0  (*(volatile unsigned char *)(MBAR + 0x1d4))
  87 #define UIMR0  (*(volatile unsigned char *)(MBAR + 0x1d4))
  88 #define UBG10  (*(volatile unsigned char *)(MBAR + 0x1d8))
  89 #define UBG20  (*(volatile unsigned char *)(MBAR + 0x1dc))
  90 #define UIVR0  (*(volatile unsigned char *)(MBAR + 0x1f0))
  91 #define UIP0   (*(volatile unsigned char *)(MBAR + 0x1f4))
  92 #define UOP10  (*(volatile unsigned char *)(MBAR + 0x1f8))
  93 #define UOP00  (*(volatile unsigned char *)(MBAR + 0x1fc))
  94
  95 #define UMR1   (*(volatile unsigned char *)(MBAR + 0x200))
  96 #define USR1   (*(volatile unsigned char *)(MBAR + 0x204))
  97 #define UCSR1  (*(volatile unsigned char *)(MBAR + 0x204))
  98 #define UCR1   (*(volatile unsigned char *)(MBAR + 0x208))
  99 #define URB1   (*(volatile unsigned char *)(MBAR + 0x20c))
 100 #define UTB1   (*(volatile unsigned char *)(MBAR + 0x20c))
 101 #define UIPCR1 (*(volatile unsigned char *)(MBAR + 0x210))
 102 #define UACR1  (*(volatile unsigned char *)(MBAR + 0x210))
 103 #define UISR1  (*(volatile unsigned char *)(MBAR + 0x214))
 104 #define UIMR1  (*(volatile unsigned char *)(MBAR + 0x214))
 105 #define UBG11  (*(volatile unsigned char *)(MBAR + 0x218))
 106 #define UBG21  (*(volatile unsigned char *)(MBAR + 0x21c))
 107 #define UIVR1  (*(volatile unsigned char *)(MBAR + 0x230))
 108 #define UIP1   (*(volatile unsigned char *)(MBAR + 0x234))
 109 #define UOP11  (*(volatile unsigned char *)(MBAR + 0x238))
 110 #define UOP01  (*(volatile unsigned char *)(MBAR + 0x23c))
 111
 112 #define MADR   (*(volatile unsigned char *)(MBAR + 0x280))
 113 #define MFDR   (*(volatile unsigned char *)(MBAR + 0x284))
 114 #define MBCR   (*(volatile unsigned char *)(MBAR + 0x288))
 115 #define MBSR   (*(volatile unsigned char *)(MBAR + 0x28c))
 116 #define MBDR   (*(volatile unsigned char *)(MBAR + 0x290))
 117
 118 #define SAR0   (*(volatile unsigned long *)(MBAR + 0x300))
 119 #define DAR0   (*(volatile unsigned long *)(MBAR + 0x304))
 120 #define DCR0   (*(volatile unsigned long *)(MBAR + 0x308))
 121 #define BCR0   (*(volatile unsigned long *)(MBAR + 0x30c))
 122 #define DSR0   (*(volatile unsigned char *)(MBAR + 0x310))
 123 #define DIVR0  (*(volatile unsigned char *)(MBAR + 0x314))
 124
 125 #define SAR1   (*(volatile unsigned long *)(MBAR + 0x340))
 126 #define DAR1   (*(volatile unsigned long *)(MBAR + 0x344))
 127 #define DCR1   (*(volatile unsigned long *)(MBAR + 0x348))
 128 #define BCR1   (*(volatile unsigned long *)(MBAR + 0x34c))
 129 #define DSR1   (*(volatile unsigned char *)(MBAR + 0x350))
 130 #define DIVR1  (*(volatile unsigned char *)(MBAR + 0x354))
 131
 132 #define SAR2   (*(volatile unsigned long *)(MBAR + 0x380))
 133 #define DAR2   (*(volatile unsigned long *)(MBAR + 0x384))
 134 #define DCR2   (*(volatile unsigned long *)(MBAR + 0x388))
 135 #define BCR2   (*(volatile unsigned long *)(MBAR + 0x38c))
 136 #define DSR2   (*(volatile unsigned char *)(MBAR + 0x390))
 137 #define DIVR2  (*(volatile unsigned char *)(MBAR + 0x394))
 138
 139 #define SAR3   (*(volatile unsigned long *)(MBAR + 0x3c0))
 140 #define DAR3   (*(volatile unsigned long *)(MBAR + 0x3c4))
 141 #define DCR3   (*(volatile unsigned long *)(MBAR + 0x3c8))
 142 #define BCR3   (*(volatile unsigned long *)(MBAR + 0x3cc))
 143 #define DSR3   (*(volatile unsigned char *)(MBAR + 0x3d0))
 144 #define DIVR3  (*(volatile unsigned char *)(MBAR + 0x3d4))
 145
 146 #define QSPIMR    (*(volatile unsigned short *)(MBAR + 0x400))
 147 #define QSPIQDLYR (*(volatile unsigned short *)(MBAR + 0x404))
 148 #define QSPIQWR   (*(volatile unsigned short *)(MBAR + 0x408))
 149 #define QSPIQIR   (*(volatile unsigned short *)(MBAR + 0x40c))
 150 #define QSPIQAR   (*(volatile unsigned short *)(MBAR + 0x410))
 151 #define QSPIQDR   (*(volatile unsigned short *)(MBAR + 0x414))
 152
 153 #define GPIO_READ     (*(volatile unsigned long *)(MBAR2 + 0x000))
 154 #define GPIO_OUT      (*(volatile unsigned long *)(MBAR2 + 0x004))
 155 #define GPIO_ENABLE   (*(volatile unsigned long *)(MBAR2 + 0x008))
 156 #define GPIO_FUNCTION (*(volatile unsigned long *)(MBAR2 + 0x00c))
 157
 158 #define IIS1CONFIG (*(volatile unsigned long *)(MBAR2 + 0x010))
 159 #define IIS2CONFIG (*(volatile unsigned long *)(MBAR2 + 0x014))
 160 #define IIS3CONFIG (*(volatile unsigned long *)(MBAR2 + 0x018))
 161 #define IIS4CONFIG (*(volatile unsigned long *)(MBAR2 + 0x01c))
 162 #define EBU1CONFIG (*(volatile unsigned long *)(MBAR2 + 0x020))
 163 #define EBU1RCVCCHANNEL1 (*(volatile unsigned long *)(MBAR2 + 0x024))
 164 #define EBUTXCCHANNEL1   (*(volatile unsigned long *)(MBAR2 + 0x028))
 165 #define EBUTXCCHANNEL2   (*(volatile unsigned long *)(MBAR2 + 0x02c))
 166 #define DATAINCONTROL    (*(volatile unsigned long *)(MBAR2 + 0x030))
 167 #define PDIR1_L  (*(volatile unsigned long *)(MBAR2 + 0x034))
 168 #define PDIR3_L  (*(volatile unsigned long *)(MBAR2 + 0x044))
 169 #define PDIR1_R  (*(volatile unsigned long *)(MBAR2 + 0x054))
 170 #define PDIR3_R  (*(volatile unsigned long *)(MBAR2 + 0x064))
 171 #define PDOR1_L  (*(volatile unsigned long *)(MBAR2 + 0x034))
 172 #define PDOR1_R  (*(volatile unsigned long *)(MBAR2 + 0x044))
 173 #define PDOR2_L  (*(volatile unsigned long *)(MBAR2 + 0x054))
 174 #define PDOR2_R  (*(volatile unsigned long *)(MBAR2 + 0x064))
 175 #define PDIR2    (*(volatile unsigned long *)(MBAR2 + 0x074))
 176 #define PDOR3    (*(volatile unsigned long *)(MBAR2 + 0x074))
 177 #define UCHANNELTRANSMIT  (*(volatile unsigned long *)(MBAR2 + 0x084))
 178 #define U1CHANNELRECEIVE  (*(volatile unsigned long *)(MBAR2 + 0x088))
 179 #define Q1CHANNELRECEIVE  (*(volatile unsigned long *)(MBAR2 + 0x08c))
 180 #define CD_TEXT_CONTROL   (*(volatile unsigned char *)(MBAR2 + 0x092))
 181 #define INTERRUPTEN       (*(volatile unsigned long *)(MBAR2 + 0x094))
 182 #define INTERRUPTCLEAR    (*(volatile unsigned long *)(MBAR2 + 0x098))
 183 #define INTERRUPTSTAT     (*(volatile unsigned long *)(MBAR2 + 0x098))
 184 #define DMACONFIG         (*(volatile unsigned char *)(MBAR2 + 0x09f))
 185 #define PHASECONFIG       (*(volatile unsigned char *)(MBAR2 + 0x0a3))
 186 #define XTRIM             (*(volatile unsigned short *)(MBAR2 + 0x0a6))
 187 #define FREQMEAS          (*(volatile unsigned long *)(MBAR2 + 0x0a8))
 188 #define BLOCKCONTROL      (*(volatile unsigned short *)(MBAR2 + 0x0ca))
 189 #define AUDIOGLOB         (*(volatile unsigned short *)(MBAR2 + 0x0ce))
 190 #define EBU2CONFIG        (*(volatile unsigned long *)(MBAR2 + 0x0d0))
 191 #define EBU2RCVCCHANNEL1  (*(volatile unsigned short *)(MBAR2 + 0x0d4))
 192 #define U2CHANNELRECEIVE  (*(volatile unsigned long *)(MBAR2 + 0x0d8))
 193 #define Q2CHANNELRECEIVE  (*(volatile unsigned long *)(MBAR2 + 0x0dc))
 194
 195 #define DEVICE_ID (*(volatile unsigned long *)(MBAR2 + 0x0ac))
 196
 197 #define GPIO1_READ     (*(volatile unsigned long *)(MBAR2 + 0x0b0))
 198 #define GPIO1_OUT      (*(volatile unsigned long *)(MBAR2 + 0x0b4))
 199 #define GPIO1_ENABLE   (*(volatile unsigned long *)(MBAR2 + 0x0b8))
 200 #define GPIO1_FUNCTION (*(volatile unsigned long *)(MBAR2 + 0x0bc))
 201 #define GPIO_INT_STAT  (*(volatile unsigned long *)(MBAR2 + 0x0c0))
 202 #define GPIO_INT_CLEAR (*(volatile unsigned long *)(MBAR2 + 0x0c0))
 203 #define GPIO_INT_EN    (*(volatile unsigned long *)(MBAR2 + 0x0c4))
 204 #define INTERRUPTSTAT3  (*(volatile unsigned long *)(MBAR2 + 0x0e0))
 205 #define INTERRUPTCLEAR3 (*(volatile unsigned long *)(MBAR2 + 0x0e0))
 206 #define INTERRUPTEN3    (*(volatile unsigned long *)(MBAR2 + 0x0e4))
 207 #define INTPRI1  (*(volatile unsigned long *)(MBAR2 + 0x140))
 208 #define INTPRI2  (*(volatile unsigned long *)(MBAR2 + 0x144))
 209 #define INTPRI3  (*(volatile unsigned long *)(MBAR2 + 0x148))
 210 #define INTPRI4  (*(volatile unsigned long *)(MBAR2 + 0x14c))
 211 #define INTPRI5  (*(volatile unsigned long *)(MBAR2 + 0x150))
 212 #define INTPRI6  (*(volatile unsigned long *)(MBAR2 + 0x154))
 213 #define INTPRI7  (*(volatile unsigned long *)(MBAR2 + 0x158))
 214 #define INTPRI8  (*(volatile unsigned long *)(MBAR2 + 0x15c))
 215 #define SPURVEC  (*(volatile unsigned char *)(MBAR2 + 0x167))
 216 #define INTBASE  (*(volatile unsigned char *)(MBAR2 + 0x16b))
 217 #define PLLCR      (*(volatile unsigned long *)(MBAR2 + 0x180))
 218 #define DMAROUTE   (*(volatile unsigned long *)(MBAR2 + 0x188))
 219 #define IDECONFIG1 (*(volatile unsigned long *)(MBAR2 + 0x18c))
 220 #define IDECONFIG2 (*(volatile unsigned long *)(MBAR2 + 0x190))
 221 #define IPERRORADR (*(volatile unsigned long *)(MBAR2 + 0x194))
 222 #define EXTRAINT   (*(volatile unsigned long *)(MBAR2 + 0x198))
 223
 224 #define ADCONFIG   (*(volatile unsigned short *)(MBAR2 + 0x402))
 225 #define ADVALUE    (*(volatile unsigned short *)(MBAR2 + 0x406))
 226 #define MADR2      (*(volatile unsigned char *)(MBAR2 + 0x440))
 227 #define MFDR2      (*(volatile unsigned char *)(MBAR2 + 0x444))
 228 #define MBCR2      (*(volatile unsigned char *)(MBAR2 + 0x448))
 229 #define MBSR2      (*(volatile unsigned char *)(MBAR2 + 0x44c))
 230 #define MBDR2      (*(volatile unsigned char *)(MBAR2 + 0x450))
 231
 232 #define FLASHMEDIACONFIG   (*(volatile unsigned long *)(MBAR2 + 0x460))
 233 #define FLASHMEDIACMD1     (*(volatile unsigned long *)(MBAR2 + 0x464))
 234 #define FLASHMEDIACMD2     (*(volatile unsigned long *)(MBAR2 + 0x468))
 235 #define FLASHMEDIADATA1    (*(volatile unsigned long *)(MBAR2 + 0x46c))
 236 #define FLASHMEDIADATA2    (*(volatile unsigned long *)(MBAR2 + 0x470))
 237 #define FLASHMEDIASTATUS   (*(volatile unsigned long *)(MBAR2 + 0x474))
 238 #define FLASHMEDIAINTEN    (*(volatile unsigned long *)(MBAR2 + 0x478))
 239 #define FLASHMEDIAINTSTAT  (*(volatile unsigned long *)(MBAR2 + 0x47c))
 240 #define FLASHMEDIAINTCLEAR (*(volatile unsigned long *)(MBAR2 + 0x47c))
 241
 242 /* DMA Registers ... */
 243
 244 #define O_SAR   0x00        /* Source Address                       */
 245 #define O_DAR   0x04        /* Destination Address                  */
 246 #define O_DCR   0x08        /* DMA Control Register                 */
 247 #define O_BCR   0x0C        /* 16 or 24 bits depending on BCR24BIT  */
 248 #define O_DSR   0x10        /* DMA Status Register                  */
 249 #define O_IVR   0x14        /* Interrupt Vector Register            */
 250
 251 /* DMA Control Register bits */
 252 #define DMA_INT         (1 << 31)       /* Enable Interrupts            */
 253 #define DMA_EEXT        (1 << 30)       /* Enable peripherial request   */
 254 #define DMA_CS          (1 << 29)       /* Cycle Steal                  */
 255 #define DMA_AA          (1 << 28)       /* Auto-Align                   */
 256 #define DMA_BWC(x)      (((x)&7) << 25) /* Bandwidth control            */
 257 #define DMA_SINC        (1 << 22)       /* Source Increment             */
 258 #define DMA_SSIZE(x)    (((x)&3) << 20) /* Size of source data          */
 259 #define DMA_DINC        (1 << 19)       /* Destination Increment        */
 260 #define DMA_DSIZE(x)    (((x)&3) << 17) /* Size of destination data     */
 261 #define DMA_START       (1 << 16)       /* Start DMA transfer           */
 262
 263 #define DMA_SIZE_DWORD  0               /* 4 bytes  */
 264 #define DMA_SIZE_BYTE   1               /* 1 byte   */
 265 #define DMA_SIZE_WORD   2               /* 2 bytes  */
 266 #define DMA_SIZE_LINE   3               /* 16 bytes */
 267
 268 /* DMA Status Register bits */
 269 #define DMA_CE          (1 << 6)        /* Configuration Error          */
 270 #define DMA_BES         (1 << 5)        /* Bus error on source          */
 271 #define DMA_BED         (1 << 4)        /* Bus error on destination     */
 272 #define DMA_REQ         (1 << 2)        /* Request pending              */
 273 #define DMA_BSY         (1 << 1)        /* DMA channel busy             */
 274 #define DMA_DONE        (1 << 0)        /* Transfer has completed       */
 275
 276 /* DMAROUTE config */
 277 #define DMA0_REQ_AUDIO_1     0x80
 278 #define DMA0_REQ_AUDIO_2     0x81
 279 #define DMA1_REQ_AUDIO_1     0x8000
 280 #define DMA1_REQ_AUDIO_2     0x8100
 281
 282 /* Timer frequency */
 283 /* timer is based on busclk == cpuclk/2 */
 284 #define TIMER_FREQ (CPU_FREQ/2)
 285
 286 #endif