firmware/drivers/synaptics-mep.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 by Mark Arigo
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include <stdlib.h>
  23 #include "config.h"
  24 #include "cpu.h"
  25 #include "system.h"
  26 #include "kernel.h"
  27
  28 #define LOGF_ENABLE
  29 #include "logf.h"
  30
  31 /* Driver for the Synaptics Touchpad based on the "Synaptics Modular Embedded
  32    Protocol: 3-Wire Interface Specification" documentation */
  33
  34 #if defined(MROBE_100)
  35 #define INT_ENABLE  GPIOD_INT_LEV &= ~0x2; GPIOD_INT_EN  |= 0x2
  36 #define INT_DISABLE GPIOD_INT_EN  &= ~0x2; GPIOD_INT_CLR |= 0x2
  37
  38 #define ACK     (GPIOD_INPUT_VAL & 0x1)
  39 #define ACK_HI  GPIOD_OUTPUT_VAL |=  0x1
  40 #define ACK_LO  GPIOD_OUTPUT_VAL &= ~0x1
  41
  42 #define CLK     ((GPIOD_INPUT_VAL & 0x2) >> 1)
  43 #define CLK_HI  GPIOD_OUTPUT_VAL |=  0x2
  44 #define CLK_LO  GPIOD_OUTPUT_VAL &= ~0x2
  45
  46 #define DATA    ((GPIOD_INPUT_VAL & 0x4) >> 2)
  47 #define DATA_HI GPIOD_OUTPUT_EN |= 0x4; GPIOD_OUTPUT_VAL |=  0x4
  48 #define DATA_LO GPIOD_OUTPUT_EN |= 0x4; GPIOD_OUTPUT_VAL &= ~0x4
  49 #define DATA_CL GPIOD_OUTPUT_EN &= ~0x4
  50
  51 #elif defined(PHILIPS_HDD1630)
  52 #define INT_ENABLE  GPIOA_INT_LEV &= ~0x20; GPIOA_INT_EN  |= 0x20
  53 #define INT_DISABLE GPIOA_INT_EN  &= ~0x20; GPIOA_INT_CLR |= 0x20
  54
  55 #define ACK     (GPIOD_INPUT_VAL & 0x80)
  56 #define ACK_HI  GPIOD_OUTPUT_VAL |=  0x80
  57 #define ACK_LO  GPIOD_OUTPUT_VAL &= ~0x80
  58
  59 #define CLK     ((GPIOA_INPUT_VAL & 0x20) >> 5)
  60 #define CLK_HI  GPIOA_OUTPUT_VAL |=  0x20
  61 #define CLK_LO  GPIOA_OUTPUT_VAL &= ~0x20
  62
  63 #define DATA    ((GPIOA_INPUT_VAL & 0x10) >> 4)
  64 #define DATA_HI GPIOA_OUTPUT_EN |= 0x10; GPIOA_OUTPUT_VAL |=  0x10
  65 #define DATA_LO GPIOA_OUTPUT_EN |= 0x10; GPIOA_OUTPUT_VAL &= ~0x10
  66 #define DATA_CL GPIOA_OUTPUT_EN &= ~0x10
  67 #endif
  68
  69 #define LO 0
  70 #define HI 1
  71
  72 #define READ_RETRY      8
  73 #define READ_ERROR     -1
  74
  75 #define MEP_HELLO_HEADER 0x19
  76 #define MEP_HELLO_ID     0x1
  77
  78 #define MEP_READ  0x1
  79 #define MEP_WRITE 0x3
  80
  81 static unsigned short syn_status = 0;
  82
  83 static int syn_wait_clk_change(unsigned int val)
  84 {
  85     int i;
  86
  87     for (i = 0; i < 10000; i++)
  88     {
  89         if (CLK == val)
  90             return 1;
  91     }
  92
  93     return 0;
  94 }
  95
  96 static inline int syn_get_data(void)
  97 {
  98     DATA_CL;
  99     return DATA;
 100 }
 101
 102 static void syn_wait_guest_flush(void)
 103 {
 104     /* Flush receiving (flushee) state:
 105        handshake until DATA goes high during P3 stage */
 106     if (CLK == LO)
 107     {
 108         ACK_HI;                  /* P1 -> P2 */
 109         syn_wait_clk_change(HI); /* P2 -> P3 */
 110     }
 111
 112     while (syn_get_data() == LO)
 113     {
 114         ACK_HI;                  /* P3 -> P0 */
 115         syn_wait_clk_change(LO); /* P0 -> P1 */
 116         ACK_LO;                  /* P1 -> P2 */
 117         syn_wait_clk_change(HI); /* P2 -> P3 */
 118     }
 119
 120     /* Continue handshaking until back to P0 */
 121     ACK_HI;                      /* P3 -> P0 */
 122 }
 123
 124 static void syn_flush(void)
 125 {
 126     int i;
 127
 128     logf("syn_flush...");
 129
 130     /* Flusher holds DATA low for at least 36 handshake cycles */
 131     DATA_LO;
 132
 133     for (i = 0; i < 36; i++)
 134     {
 135         syn_wait_clk_change(LO); /* P0 -> P1 */
 136         ACK_LO;                  /* P1 -> P2 */
 137         syn_wait_clk_change(HI); /* P2 -> P3 */
 138         ACK_HI;                  /* P3 -> P0 */
 139     }
 140
 141     /* Raise DATA in P1 stage */
 142     syn_wait_clk_change(LO); /* P0 -> P1 */
 143     DATA_HI;
 144
 145     /* After a flush, the flushing device enters a flush-receiving (flushee)
 146        state */
 147     syn_wait_guest_flush();
 148 }
 149
 150 int syn_send(int *data, int len)
 151 {
 152     int i, bit;
 153     int parity = 0;
 154
 155     logf("syn_send...");
 156
 157     /* 1. Lower DATA line to issue a request-to-send to guest */
 158     DATA_LO;
 159
 160     /* 2. Wait for guest to lower CLK */
 161     syn_wait_clk_change(LO);
 162
 163     /* 3. Lower ACK (with DATA still low) */
 164     ACK_LO;
 165
 166     /* 4. Wait for guest to raise CLK */
 167     syn_wait_clk_change(HI);
 168
 169     /* 5. Send data */
 170     for (i = 0; i < len; i++)
 171     {
 172        logf("  sending byte: %d", data[i]);
 173
 174         bit = 0;
 175         while (bit < 8)
 176         {
 177             /* 5a. Drive data low if bit is 0, or high if bit is 1 */
 178             if (data[i] & (1 << bit))
 179             {
 180                 DATA_HI;
 181                 parity++;
 182             }
 183             else
 184             {
 185                 DATA_LO;
 186             }
 187             bit++;
 188
 189             /* 5b. Invert ACK to indicate that the data bit is ready */
 190             ACK_HI;
 191
 192             /* 5c. Wait for guest to invert CLK */
 193             syn_wait_clk_change(LO);
 194
 195             /* Repeat for next bit */
 196             if (data[i] & (1 << bit))
 197             {
 198                 DATA_HI;
 199                 parity++;
 200             }
 201             else
 202             {
 203                 DATA_LO;
 204             }
 205             bit++;
 206
 207             ACK_LO;
 208
 209             syn_wait_clk_change(HI);
 210         }
 211     }
 212
 213     /* 7. Transmission termination sequence: */
 214     /* 7a. Host may put parity bit on DATA. Hosts that do not generate
 215            parity should set DATA high. Parity is 1 if there's an odd
 216            number of '1' bits, or 0 if there's an even number of '1' bits. */
 217     parity = parity % 2;
 218     if (parity)
 219     {
 220         DATA_HI;
 221     }
 222     else
 223     {
 224         DATA_LO;
 225     }
 226     logf("  send parity = %d", parity);
 227
 228     /* 7b. Raise ACK to indicate that the optional parity bit is ready */
 229     ACK_HI;
 230
 231     /* 7c. Guest lowers CLK */
 232     syn_wait_clk_change(LO);
 233
 234     /* 7d. Pull DATA high (if parity bit was 0) */
 235     DATA_HI;
 236
 237     /* 7e. Lower ACK to indicate that the stop bit is ready */
 238     ACK_LO;
 239
 240     /* 7f. Guest raises CLK */
 241     syn_wait_clk_change(HI);
 242
 243     /* 7g. If DATA is low, guest is flushing this transfer. Host should
 244            enter the flushee state. */
 245     if (syn_get_data() == LO)
 246     {
 247         logf("  module flushing");
 248
 249         syn_wait_guest_flush();
 250         return -1;
 251     }
 252
 253     /* 7h. Host raises ACK and the link enters the idle state */
 254     ACK_HI;
 255
 256     return len;
 257 }
 258
 259 static int syn_read_data(int *data, int data_len)
 260 {
 261     int i, len, bit, parity, tmp;
 262     int *data_ptr;
 263
 264     logf("syn_read_data...");
 265
 266     /* 1. Guest drives CLK low */
 267     if (CLK != LO)
 268         return 0;
 269
 270     /* 1a. If the host is willing to receive a packet it lowers ACK */
 271     ACK_LO;
 272
 273     /* 2. Guest may issue a request-to-send by lowering DATA. If the
 274           guest decides not to transmit a packet, it may abort the
 275           transmission by not lowering DATA. */
 276
 277     /* 3. The guest raises CLK */
 278     syn_wait_clk_change(HI);
 279
 280     /* 4. If the guest is still driving DATA low, the transfer is commited
 281           to occur. Otherwise, the transfer is aborted. In either case,
 282           the host raises ACK. */
 283     if (syn_get_data() == HI)
 284     {
 285         logf("  read abort");
 286
 287         ACK_HI;
 288         return READ_ERROR;
 289     }
 290     else
 291     {
 292         ACK_HI;
 293     }
 294
 295     /* 5. Read the incoming data packet */
 296     i = 0;
 297     len = 0;
 298     parity = 0;
 299     while (i <= len)
 300     {
 301         bit = 0;
 302
 303         if (i < data_len)
 304             data_ptr = &data[i];
 305         else
 306             data_ptr = &tmp;
 307
 308         *data_ptr = 0;
 309         while (bit < 8)
 310         {
 311             /* 5b. Guset inverts CLK to indicate that data is ready */
 312             syn_wait_clk_change(LO);
 313
 314             /* 5d. Read the data bit from DATA */
 315             if (syn_get_data() == HI)
 316             {
 317                 *data_ptr |= (1 << bit);
 318                 parity++;
 319             }
 320             bit++;
 321
 322             /* 5e. Invert ACK to indicate that data has been read */
 323             ACK_LO;
 324
 325             /* Repeat for next bit */
 326             syn_wait_clk_change(HI);
 327
 328             if (syn_get_data() == HI)
 329             {
 330                 *data_ptr |= (1 << bit);
 331                 parity++;
 332             }
 333             bit++;
 334
 335             ACK_HI;
 336         }
 337
 338         /* First byte is the packet header */
 339         if (i == 0)
 340         {
 341             /* Format control (bit 3) should be 1 */
 342             if (*data_ptr & 0x8)
 343             {
 344                 /* Packet length is bits 0:2 */
 345                 len = *data_ptr & 0x7;
 346                 logf("  packet length = %d", len);
 347             }
 348             else
 349             {
 350                 logf("  invalid format ctrl bit");
 351                 return READ_ERROR;
 352             }
 353         }
 354
 355         i++;
 356     }
 357
 358     /* 7. Transmission termination cycle */
 359     /* 7a. The guest generates a parity bit on DATA */
 360     /* 7b. The host waits for guest to lower CLK */
 361     syn_wait_clk_change(LO);
 362
 363     /* 7c. The host verifies the parity bit is correct */
 364     parity = parity % 2;
 365     logf("  parity check: %d / %d", syn_get_data(), parity);
 366
 367     /* TODO: parity error handling */
 368
 369     /* 7d. The host lowers ACK */
 370     ACK_LO;
 371
 372     /* 7e. The host waits for the guest to raise CLK indicating
 373            that the stop bit is ready */
 374     syn_wait_clk_change(HI);
 375
 376     /* 7f. The host reads DATA and verifies that it is 1 */
 377     if (syn_get_data() == LO)
 378     {
 379         logf("  framing error");
 380
 381         ACK_HI;
 382         return READ_ERROR;
 383     }
 384
 385     ACK_HI;
 386
 387     return len;
 388 }
 389
 390 int syn_read(int *data, int len)
 391 {
 392     int i;
 393     int ret = READ_ERROR;
 394
 395     for (i = 0; i < READ_RETRY; i++)
 396     {
 397         if (syn_wait_clk_change(LO))
 398         {
 399             /* module is sending data */
 400             ret = syn_read_data(data, len);
 401             if (ret != READ_ERROR)
 402                 return ret;
 403
 404             syn_flush();
 405         }
 406         else
 407         {
 408             /* module is idle */
 409             return 0;
 410         }
 411     }
 412
 413     return ret;
 414 }
 415
 416 int syn_reset(void)
 417 {
 418     int val, id;
 419     int data[2];
 420
 421     logf("syn_reset...");
 422
 423     /* reset module 0 */
 424     val = (0 << 4) | (1 << 3) | 0;
 425     syn_send(&val, 1);
 426
 427     val = syn_read(data, 2);
 428     if (val == 1)
 429     {
 430         val = data[0] & 0xff;      /* packet header */
 431         id = (data[1] >> 4) & 0xf; /* packet id */
 432         if ((val == MEP_HELLO_HEADER) && (id == MEP_HELLO_ID))
 433         {
 434             logf("  module 0 reset");
 435             return 1;
 436         }
 437     }
 438
 439     logf("  reset failed");
 440     return 0;
 441 }
 442
 443 int syn_init(void)
 444 {
 445     syn_flush();
 446     syn_status = syn_reset();
 447
 448     if (syn_status)
 449     {
 450         INT_DISABLE;
 451         INT_ENABLE;
 452
 453         CPU_INT_EN    |= HI_MASK;
 454         CPU_HI_INT_EN |= GPIO0_MASK;
 455     }
 456
 457     return syn_status;
 458 }
 459
 460 int syn_get_status(void)
 461 {
 462     return syn_status;
 463 }
 464
 465 void syn_int_enable(bool enable)
 466 {
 467     if (enable)
 468     {
 469         INT_ENABLE;
 470     }
 471     else
 472     {
 473         INT_DISABLE;
 474     }
 475 }
 476
 477 #ifdef ROCKBOX_HAS_LOGF
 478 void syn_info(void)
 479 {
 480     int i, val;
 481     int data[8];
 482
 483     logf("syn_info...");
 484
 485     /* module base info */
 486     logf("module base info:");
 487     data[0] = MEP_READ;
 488     data[1] = 0x80;
 489     syn_send(data, 2);
 490     val = syn_read(data, 8);
 491     if (val > 0)
 492     {
 493         for (i = 0; i < 8; i++)
 494             logf("  data[%d] = 0x%02x", i, data[i]);
 495     }
 496
 497     /* module product info */
 498     logf("module product info:");
 499     data[0] = MEP_READ;
 500     data[1] = 0x81;
 501     syn_send(data, 2);
 502     val = syn_read(data, 8);
 503     if (val > 0)
 504     {
 505         for (i = 0; i < 8; i++)
 506             logf("  data[%d] = 0x%02x", i, data[i]);
 507     }
 508
 509     /* module serialization */
 510     logf("module serialization:");
 511     data[0] = MEP_READ;
 512     data[1] = 0x82;
 513     syn_send(data, 2);
 514     val = syn_read(data, 8);
 515     if (val > 0)
 516     {
 517         for (i = 0; i < 8; i++)
 518             logf("  data[%d] = 0x%02x", i, data[i]);
 519     }
 520
 521     /* 1-D sensor info */
 522     logf("1-d sensor info:");
 523     data[0] = MEP_READ;
 524     data[1] = 0x80 + 0x20;
 525     syn_send(data, 2);
 526     val = syn_read(data, 8);
 527     if (val > 0)
 528     {
 529         for (i = 0; i < 8; i++)
 530             logf("  data[%d] = 0x%02x", i, data[i]);
 531     }
 532 }
 533 #endif