firmware/export/uda1380.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Linus Nielsen Feltzing
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #ifndef _UDA1380_H
  23 #define _UDA1380_H
  24
  25 /* volume/balance/treble/bass interdependency */
  26 #define VOLUME_MIN -840
  27 #define VOLUME_MAX  0
  28
  29 #define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP | PRESCALER_CAP)
  30
  31 extern int tenthdb2master(int db);
  32 extern int tenthdb2mixer(int db);
  33
  34 extern void audiohw_set_master_vol(int vol_l, int vol_r);
  35 extern void audiohw_set_mixer_vol(int channel1, int channel2);
  36
  37 /**
  38  * Sets frequency settings for DAC and ADC relative to MCLK
  39  *
  40  * Selection for frequency ranges:
  41  *  Fs:        range:       with:
  42  *  11025: 0 = 6.25 to 12.5 SCLK, LRCK: Audio Clk / 16
  43  *  22050: 1 = 12.5 to 25   SCLK, LRCK: Audio Clk / 8
  44  *  44100: 2 = 25   to 50   SCLK, LRCK: Audio Clk / 4 (default)
  45  *  88200: 3 = 50   to 100  SCLK, LRCK: Audio Clk / 2
  46  */
  47 extern void audiohw_set_frequency(unsigned fsel);
  48
  49 #define UDA1380_ADDR        0x30
  50
  51 /* REG_0: Misc settings */
  52 #define REG_0               0x00
  53 #define EN_ADC              (1 << 11)    /* Enable ADC                     */
  54 #define EN_DEC              (1 << 10)    /* Enable Decimator               */
  55 #define EN_DAC              (1 << 9)     /* Enable DAC                     */
  56 #define EN_INT              (1 << 8)     /* Enable Interpolator            */
  57 #define ADC_CLK             (1 << 5)     /* ADC_CLK: WSPLL (1) SYSCLK (0)  */
  58 #define DAC_CLK             (1 << 4)     /* DAC_CLK: WSPLL (1) SYSCLK (0)  */
  59
  60 /* SYSCLK freqency select */
  61 #define SYSCLK_256FS        (0 << 2)
  62 #define SYSCLK_384FS        (1 << 2)
  63 #define SYSCLK_512FS        (2 << 2)
  64 #define SYSCLK_768FS        (3 << 2)
  65
  66 /* WSPLL Input frequency range (kHz) */
  67 #define WSPLL_625_125       (0 << 0)     /* 6.25 - 12.5      */
  68 #define WSPLL_125_25        (1 << 0)     /* 12.5 - 25        */
  69 #define WSPLL_25_50         (2 << 0)     /* 25   - 50        */
  70 #define WSPLL_50_100        (3 << 0)     /* 50   - 100       */
  71
  72
  73 /* REG_I2S: I2S settings */
  74 #define REG_I2S                 0x01
  75 #define I2S_IFMT_IIS        (0 << 8)
  76 #define I2S_IFMT_LSB16      (1 << 8)
  77 #define I2S_IFMT_LSB18      (2 << 8)
  78 #define I2S_IFMT_LSB20      (3 << 8)
  79 #define I2S_IFMT_MSB        (5 << 8)
  80 #define I2S_OFMT_IIS        (0 << 0)
  81 #define I2S_OFMT_LSB16      (1 << 0)
  82 #define I2S_OFMT_LSB18      (2 << 0)
  83 #define I2S_OFMT_LSB20      (3 << 0)
  84 #define I2S_OFMT_LSB24      (4 << 0)
  85 #define I2S_OFMT_MSB        (5 << 0)
  86 #define I2S_MODE_MASTER     (1 << 4)
  87
  88 /* REG_PWR: Power control */
  89 #define REG_PWR             0x02
  90 #define PON_PLL             (1 << 15)   /* Power-on WSPLL                     */
  91 #define PON_HP              (1 << 13)   /* Power-on Headphone driver          */
  92 #define PON_DAC             (1 << 10)   /* Power-on DAC                       */
  93 #define PON_BIAS            (1 << 8)    /* Power-on BIAS for ADC, AVC, FSDAC  */
  94 #define EN_AVC              (1 << 7)    /* Enable analog mixer                */
  95 #define PON_AVC             (1 << 6)    /* Power-on analog mixer              */
  96 #define PON_LNA             (1 << 4)    /* Power-on LNA & SDC                 */
  97 #define PON_PGAL            (1 << 3)    /* Power-on PGA left                  */
  98 #define PON_ADCL            (1 << 2)    /* Power-on ADC left                  */
  99 #define PON_PGAR            (1 << 1)    /* Power-on PGA right                 */
 100 #define PON_ADCR            (1 << 0)    /* Power-on ADC right                 */
 101
 102
 103 /* REG_AMIX: Analog mixer */
 104 #define REG_AMIX            0x03
 105 #define AMIX_LEFT(x)        (((x) & 0x3f) << 8)
 106 #define AMIX_RIGHT(x)       (((x) & 0x3f) << 0)
 107
 108 /* REG_HP: Headphone amp */
 109 #define REG_HP              0x04
 110
 111 /* REG_MV: Master Volume control */
 112 #define REG_MASTER_VOL      0x10
 113
 114 #define MASTER_VOL_RIGHT(x) (((x) & 0xff) << 8)
 115 #define MASTER_VOL_LEFT(x)  (((x) & 0xff) << 0)
 116
 117 /* REG_MIX: Mixer volume control */
 118 /* Channel 1 is from digital data from I2S */
 119 /* Channel 2 is from decimation filter */
 120
 121 #define REG_MIX_VOL         0x11
 122 #define MIX_VOL_CH_1(x)     (((x) & 0xff) << 0)
 123 #define MIX_VOL_CH_2(x)     (((x) & 0xff) << 8)
 124
 125 /* REG_EQ: Bass boost and tremble */
 126 #define REG_EQ              0x12
 127 #define EQ_MODE_FLAT        (0 << 14)
 128 #define EQ_MODE_MIN         (1 << 14)
 129 #define EQ_MODE_MAX         (3 << 14)
 130 #define BASSL(x)            (((x) & 0x1E) << 7)
 131 #define BASSR(x)            (((x) & 0x1E) >> 1)
 132 #define TREBLEL(x)          (((x) & 0x6) << 11)
 133 #define TREBLER(x)          (((x) & 0x6) << 3)
 134 #define BASS_MASK           0x0F0F
 135 #define TREBLE_MASK         0x3030
 136
 137 /* REG_MUTE: Master Mute, silence detector and oversampling */
 138 #define REG_MUTE            0x13
 139 #define MUTE_MASTER         (1 << 14)      /* Master Mute (soft)       */
 140 #define MUTE_CH2            (1 << 11)      /* Channel 2 mute           */
 141 #define MUTE_CH1            (1 << 3)       /* Channel 1 mute           */
 142 #define DE_EMPHASIS_NONE    (0 << 8)       /* no de-emphasis           */
 143 #define DE_EMPHASIS_32kHz   (1 << 8)       /* 32 kHz                   */
 144 #define DE_EMPHASIS_44kHz   (2 << 8)       /* 44.1 kHz                 */
 145 #define DE_EMPHASIS_48kHz   (3 << 8)       /* 48 kHz                   */
 146 #define DE_EMPHASIS_96kHz   (4 << 8)       /* 96 kHz                   */
 147
 148 /* REG_MIX_CTL: Mixer, silence detector and oversampling settings */
 149 #define REG_MIX_CTL         0x14
 150 #define DAC_INVERT          (1 << 15)      /* invert DAC polarity      */
 151 #define MIX_CTL_SEL_NS      (1 << 14)      /* 0 = 3rd, 1 = 5th order   */
 152 #define MIX_CTL_MIX_POS     (1 << 13)      /* MIX MODE bit MIX POS     */
 153 #define MIX_CTL_MIX         (1 << 12)      /* MIX MODE bit MIX         */
 154 #define MIX_MODE(x)         (((x) & 0x3) << 12) /* Mixer mode: See table 48 */
 155 #define SILENCE_MODE        (1 << 7)       /* force silence output     */
 156 #define SILENCE_DET_ON      (1 << 6)       /* enable silence detection */
 157 #define SILENCE_DET(x)      (((x) & 0x3) << 4) /* silence detection value  */
 158 #define SILENCE_DET_3200    (0 << 4)       /* 3200 samples             */
 159 #define SILENCE_DET_4800    (1 << 4)       /* 4800 samples             */
 160 #define SILENCE_DET_9600    (2 << 4)       /* 9600 samples             */
 161 #define SILENCE_DET_19200   (3 << 4)       /* 19200 samples            */
 162 #define OVERSAMPLE_MODE(x)  (((x) & 0x3) << 0) /* oversampling mode        */
 163
 164 /* REG_DEC_VOL: Decimator (ADC) volume control */
 165 #define REG_DEC_VOL         0x20
 166 #define DEC_VOLL(x)         (((x) & 0xff) << 8)
 167 #define DEC_VOLR(x)         (((x) & 0xff) << 0)
 168
 169 /* REG_PGA: PGA settings and mute */
 170 #define REG_PGA             0x21
 171 #define MUTE_ADC            (1 << 15)               /* Mute ADC */
 172 #define PGA_GAINR(x)        (((x) & 0xF) << 8)
 173 #define PGA_GAINL(x)        (((x) & 0xF) << 0)
 174 #define PGA_GAIN_MASK       0x0F0F
 175
 176 /* REG_ADC: */
 177 #define REG_ADC             0x22
 178 #define ADC_INVERT          (1 << 12)       /* invert ADC polarity      */
 179 #define VGA_GAIN(x)         (((x) & 0xF) << 8)
 180 #define VGA_GAIN_MASK       0x0F00
 181 #define SEL_LNA             (1 << 3)
 182 #define SEL_MIC             (1 << 2)
 183 #define SKIP_DCFIL          (1 << 1)
 184 #define EN_DCFIL            (1 << 0)
 185
 186 /* REG_AGC: Attack / Gain */
 187 #define REG_AGC             0x23
 188
 189 #endif /* _UDA_1380_H */