firmware/target/arm/wmcodec-pp.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Portalplayer specific code for Wolfson audio codecs
  11  *
  12  * Based on code from the ipodlinux project - http://ipodlinux.org/
  13  * Adapted for Rockbox in December 2005
  14  *
  15  * Original file: linux/arch/armnommu/mach-ipod/audio.c
  16  *
  17  * Copyright (c) 2003-2005 Bernard Leach (leachbj@bouncycastle.org)
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License
  21  * as published by the Free Software Foundation; either version 2
  22  * of the License, or (at your option) any later version.
  23  *
  24  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  25  * KIND, either express or implied.
  26  *
  27  ****************************************************************************/
  28
  29 #include "system.h"
  30 #include "audiohw.h"
  31 #include "i2c-pp.h"
  32 #include "i2s.h"
  33 #include "wmcodec.h"
  34
  35 #if defined(IRIVER_H10) || defined(IRIVER_H10_5GB) || \
  36     defined(MROBE_100) || defined(PHILIPS_HDD1630) || defined(PHILIPS_HDD6330) || \
  37     defined(PBELL_VIBE500)
  38 /* The H10's audio codec uses an I2C address of 0x1b */
  39 #define I2C_AUDIO_ADDRESS 0x1b
  40 #else
  41 /* The iPod's audio codecs use an I2C address of 0x1a */
  42 #define I2C_AUDIO_ADDRESS 0x1a
  43 #endif
  44
  45
  46 /*
  47  * Initialise the PP I2C and I2S.
  48  */
  49 void audiohw_init(void)
  50 {
  51 #ifdef CPU_PP502x
  52     /* normal outputs for CDI and I2S pin groups */
  53     DEV_INIT2 &= ~0x300;
  54
  55     /*mini2?*/
  56     DEV_INIT1 &=~0x3000000;
  57     /*mini2?*/
  58
  59     /* I2S device reset */
  60     DEV_RS |= DEV_I2S;
  61     DEV_RS &=~DEV_I2S;
  62
  63     /* I2S device enable */
  64     DEV_EN |= DEV_I2S;
  65
  66     /* enable external dev clock clocks */
  67     DEV_EN |= DEV_EXTCLOCKS;
  68
  69     /* external dev clock to 24MHz */
  70     outl(inl(0x70000018) & ~0xc, 0x70000018);
  71 #else
  72     /* device reset */
  73     outl(inl(0xcf005030) | 0x80, 0xcf005030);
  74     outl(inl(0xcf005030) & ~0x80, 0xcf005030);
  75
  76     /* device enable */
  77     outl(inl(0xcf005000) | 0x80, 0xcf005000);
  78
  79     /* GPIO D06 enable for output */
  80     outl(inl(0xcf00000c) | 0x40, 0xcf00000c);
  81     outl(inl(0xcf00001c) & ~0x40, 0xcf00001c);
  82 #ifdef IPOD_1G2G
  83     /* bits 11,10 == 10 */
  84     outl(inl(0xcf004040) & ~0x400, 0xcf004040);
  85     outl(inl(0xcf004040) | 0x800, 0xcf004040);
  86 #else /* IPOD_3G */
  87     /* bits 11,10 == 01 */
  88     outl(inl(0xcf004040) | 0x400, 0xcf004040);
  89     outl(inl(0xcf004040) & ~0x800, 0xcf004040);
  90
  91     outl(inl(0xcf004048) & ~0x1, 0xcf004048);
  92
  93     outl(inl(0xcf000004) & ~0xf, 0xcf000004);
  94     outl(inl(0xcf004044) & ~0xf, 0xcf004044);
  95
  96     /* C03 = 0 */
  97     outl(inl(0xcf000008) | 0x8, 0xcf000008);
  98     outl(inl(0xcf000018) | 0x8, 0xcf000018);
  99     outl(inl(0xcf000028) & ~0x8, 0xcf000028);
 100 #endif /* IPOD_1G2G/3G */
 101 #endif
 102
 103     /* reset the I2S controller into known state */
 104     i2s_reset();
 105
 106     audiohw_preinit();
 107 }
 108
 109 void wmcodec_write(int reg, int data)
 110 {
 111     pp_i2c_send(I2C_AUDIO_ADDRESS, (reg<<1) | ((data&0x100)>>8),data&0xff);
 112 }