firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "led.h"
  27 #include "hotswap.h"
  28 #include "system.h"
  29 #include "kernel.h"
  30 #include "cpu.h"
  31 #include <stdio.h>
  32 #include <stdlib.h>
  33 #include <string.h>
  34 #include "as3525v2.h"
  35 #include "pl081.h"  /* DMA controller */
  36 #include "dma-target.h" /* DMA request lines */
  37 #include "clock-target.h"
  38 #include "panic.h"
  39 #include "stdbool.h"
  40 #include "ata_idle_notify.h"
  41 #include "sd.h"
  42 #include "usb.h"
  43
  44 #ifdef HAVE_HOTSWAP
  45 #include "disk.h"
  46 #endif
  47
  48 #include "lcd.h"
  49 #include <stdarg.h>
  50 #include "sysfont.h"
  51
  52 #define     INTERNAL_AS3525  0   /* embedded SD card */
  53 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  54
  55 /* command flags */
  56 #define MCI_NO_RESP     (0<<0)
  57 #define MCI_RESP        (1<<0)
  58 #define MCI_LONG_RESP   (1<<1)
  59
  60 /* controller registers */
  61 #define SD_BASE 0xC6070000
  62
  63 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  64
  65 #define MCI_CTRL        SD_REG(0x00)
  66
  67 /* control bits */
  68 #define CTRL_RESET      (1<<0)
  69 #define FIFO_RESET      (1<<1)
  70 #define DMA_RESET       (1<<2)
  71 #define INT_ENABLE      (1<<4)
  72 #define DMA_ENABLE      (1<<5)
  73 #define READ_WAIT       (1<<6)
  74 #define SEND_IRQ_RESP   (1<<7)
  75 #define ABRT_READ_DATA  (1<<8)
  76 #define SEND_CCSD       (1<<9)
  77 #define SEND_AS_CCSD    (1<<10)
  78 #define EN_OD_PULLUP    (1<<24)
  79
  80
  81 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  82
  83 #define PWR_CRD_0       (1<<0)
  84 #define PWR_CRD_1       (1<<1)
  85 #define PWR_CRD_2       (1<<2)
  86 #define PWR_CRD_3       (1<<3)
  87
  88 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  89 /* CLK_DIV_0 :    bits 7:0
  90  * CLK_DIV_1 :    bits 15:8
  91  * CLK_DIV_2 :    bits 23:16
  92  * CLK_DIV_3 :    bits 31:24
  93  */
  94
  95 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
  96 /* CLK_SRC_CRD0:  bits 1:0
  97  * CLK_SRC_CRD1:  bits 3:2
  98  * CLK_SRC_CRD2:  bits 5:4
  99  * CLK_SRC_CRD3:  bits 7:6
 100  */
 101
 102 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
 103
 104 #define CCLK_ENA_CRD0   (1<<0)
 105 #define CCLK_ENA_CRD1   (1<<1)
 106 #define CCLK_ENA_CRD2   (1<<2)
 107 #define CCLK_ENA_CRD3   (1<<3)
 108 #define CCLK_LP_CRD0    (1<<16)         /* LP --> Low Power Mode? */
 109 #define CCLK_LP_CRD1    (1<<17)
 110 #define CCLK_LP_CRD2    (1<<18)
 111 #define CCLK_LP_CRD3    (1<<19)
 112
 113 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
 114 /* response timeout bits 0:7
 115  * data timeout bits     8:31
 116  */
 117
 118 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
 119                                         /* 1 bit per card, set = wide bus */
 120 #define WIDTH4_CRD0     (1<<0)
 121 #define WIDTH4_CRD1     (1<<1)
 122 #define WIDTH4_CRD2     (1<<2)
 123 #define WIDTH4_CRD3     (1<<3)
 124
 125 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size  bits 0:15*/
 126 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count  bits 0:31*/
 127 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
 128
 129
 130
 131 #define MCI_ARGUMENT    SD_REG(0x28)
 132 #define MCI_COMMAND     SD_REG(0x2C)
 133
 134 /* command bits (bits 5:0 are the command index) */
 135 #define CMD_RESP_EXP_BIT        (1<<6)
 136 #define CMD_RESP_LENGTH_BIT     (1<<7)
 137 #define CMD_CHECK_CRC_BIT       (1<<8)
 138 #define CMD_DATA_EXP_BIT        (1<<9)
 139 #define CMD_RW_BIT              (1<<10)
 140 #define CMD_TRANSMODE_BIT       (1<<11)
 141 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
 142 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
 143 #define CMD_ABRT_CMD_BIT        (1<<14)
 144 #define CMD_SEND_INIT_BIT       (1<<15)
 145 #define CMD_CARD_NO(x)          ((x)<<16)         /* 5 bits wide  */
 146 #define CMD_SEND_CLK_ONLY       (1<<21)
 147 #define CMD_READ_CEATA          (1<<22)
 148 #define CMD_CCS_EXPECTED        (1<<23)
 149 #define CMD_DONE_BIT            (1<<31)
 150
 151
 152 #define MCI_RESP0       SD_REG(0x30)
 153 #define MCI_RESP1       SD_REG(0x34)
 154 #define MCI_RESP2       SD_REG(0x38)
 155 #define MCI_RESP3       SD_REG(0x3C)
 156
 157 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 158 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 159                                          * status clear */
 160
 161 /* interrupt bits */                /* C D E   (Cmd) (Data) (End) */
 162 #define MCI_INT_CRDDET  (1<<0)      /*          card detect */
 163 #define MCI_INT_RE      (1<<1)      /* x         response error */
 164 #define MCI_INT_CD      (1<<2)      /*     x     command done */
 165 #define MCI_INT_DTO     (1<<3)      /*     x     data transfer over */
 166 #define MCI_INT_TXDR    (1<<4)      /*          tx fifo data request */
 167 #define MCI_INT_RXDR    (1<<5)      /*          rx fifo data request */
 168 #define MCI_INT_RCRC    (1<<6)      /* x         response crc error */
 169 #define MCI_INT_DCRC    (1<<7)      /*   x       data crc error */
 170 #define MCI_INT_RTO     (1<<8)      /* x         response timeout */
 171 #define MCI_INT_DRTO    (1<<9)      /*   x       data read timeout */
 172 #define MCI_INT_HTO     (1<<10)     /*   x       data starv timeout */
 173 #define MCI_INT_FRUN    (1<<11)     /*   x       fifo over/underrun */
 174 #define MCI_INT_HLE     (1<<12)     /* x x        hw locked while error */
 175 #define MCI_INT_SBE     (1<<13)     /*   x       start bit error */
 176 #define MCI_INT_ACD     (1<<14)     /*          auto command done */
 177 #define MCI_INT_EBE     (1<<15)     /*   x       end bit error */
 178 #define MCI_INT_SDIO    (0xf<<16)
 179
 180 /*
 181  *  STATUS register
 182  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 183  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 184  *  & 8         = MCI_INT_DTO
 185  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 186  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 187  */
 188
 189 #define MCI_CMD_ERROR    \
 190          (MCI_INT_RE   | \
 191           MCI_INT_RCRC | \
 192           MCI_INT_RTO  | \
 193           MCI_INT_HLE)
 194
 195 #define MCI_DATA_ERROR    \
 196         ( MCI_INT_DCRC  | \
 197           MCI_INT_DRTO  | \
 198           MCI_INT_HTO   | \
 199           MCI_INT_FRUN  | \
 200           MCI_INT_HLE   | \
 201           MCI_INT_SBE   | \
 202           MCI_INT_EBE)
 203
 204 #define MCI_STATUS      SD_REG(0x48)
 205
 206 #define FIFO_RX_WM              (1<<0)
 207 #define FIFO_TX_WM              (1<<1)
 208 #define FIFO_EMPTY              (1<<2)
 209 #define FIFO_FULL               (1<<3)
 210 #define CMD_FSM_STATE_B0        (1<<4)
 211 #define CMD_FSM_STATE_B1        (1<<5)
 212 #define CMD_FSM_STATE_B2        (1<<6)
 213 #define CMD_FSM_STATE_B3        (1<<7)
 214 #define DATA_3_STAT             (1<<8)
 215 #define DATA_BUSY               (1<<9)
 216 #define DATA_STAT_MC_BUSY       (1<<10)
 217 #define RESP_IDX_B0             (1<<11)
 218 #define RESP_IDX_B1             (1<<12)
 219 #define RESP_IDX_B2             (1<<13)
 220 #define RESP_IDX_B3             (1<<14)
 221 #define RESP_IDX_B4             (1<<15)
 222 #define RESP_IDX_B5             (1<<16)
 223 #define FIFO_CNT_B00            (1<<17)
 224 #define FIFO_CNT_B01            (1<<18)
 225 #define FIFO_CNT_B02            (1<<19)
 226 #define FIFO_CNT_B03            (1<<20)
 227 #define FIFO_CNT_B04            (1<<21)
 228 #define FIFO_CNT_B05            (1<<22)
 229 #define FIFO_CNT_B06            (1<<23)
 230 #define FIFO_CNT_B07            (1<<24)
 231 #define FIFO_CNT_B08            (1<<25)
 232 #define FIFO_CNT_B09            (1<<26)
 233 #define FIFO_CNT_B10            (1<<27)
 234 #define FIFO_CNT_B11            (1<<28)
 235 #define FIFO_CNT_B12            (1<<29)
 236 #define DMA_ACK                 (1<<30)
 237 #define START_CMD               (1<<31)
 238
 239 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 240 /* TX watermark :    bits 11:0
 241  * RX watermark :    bits 27:16
 242  * DMA MTRANS SIZE : bits 30:28
 243  * bits 31, 15:12 : unused
 244  */
 245 #define MCI_FIFOTH_MASK 0x8000f000
 246
 247 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 248
 249 #define CDETECT_CRD_0   (1<<0)
 250 #define CDETECT_CRD_1   (1<<1)
 251 #define CDETECT_CRD_2   (1<<2)
 252 #define CDETECT_CRD_3   (1<<3)
 253
 254 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 255 #define MCI_GPIO        SD_REG(0x58)
 256 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count (card)*/
 257 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes (FIFO)*/
 258 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce  bits 23:0*/
 259 #define MCI_USRID       SD_REG(0x68)    /* user id */
 260 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 261
 262 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 263 /* bit  0       : card type
 264  * bits 5:1     : maximum card index
 265  * bit  6       : BUS TYPE
 266  * bits 9:7     : DATA WIDTH
 267  * bits 15:10   : ADDR WIDTH
 268  * bits 17:16   : DMA IF
 269  * bits 20:18   : DMA WIDTH
 270  * bit  21      : FIFO RAM INSIDE
 271  * bit  22      : IMPL HOLD REG
 272  * bit  23      : SET CLK FALSE
 273  * bits 25:24   : MAX CLK DIV IDX
 274  * bit  26      : AREA OPTIM
 275  */
 276
 277 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 278 /* bit  0       : SWR
 279  * bit  1       : FB
 280  * bits 6:2     : DSL
 281  * bit  7       : DE
 282  * bit  10:8    : PBL
 283  */
 284
 285 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 286 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 287 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 288 /* bit  0       : TI
 289  * bit  1       : RI
 290  * bit  2       : FBE
 291  * bit  3       : unused
 292  * bit  4       : DU
 293  * bit  5       : CES
 294  * bits 7:6     : unused
 295  * bits 8       : NIS
 296  * bit  9       : AIS
 297  * bits 12:10   : EB
 298  * bits 16:13   : FSM
 299  */
 300
 301 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 302 /* bit  0       : TI
 303  * bit  1       : RI
 304  * bit  2       : FBE
 305  * bit  3       : unused
 306  * bit  4       : DU
 307  * bit  5       : CES
 308  * bits 7:6     : unused
 309  * bits 8       : NI
 310  * bit  9       : AI
 311  */
 312 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 313 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 314
 315 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 316
 317 #define UNALIGNED_NUM_SECTORS 10
 318 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 319 static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 320
 321 static void init_controller(void);
 322 static int sd_wait_for_state(const int drive, unsigned int state);
 323
 324 static tCardInfo card_info[NUM_DRIVES];
 325
 326 /* for compatibility */
 327 static long last_disk_activity = -1;
 328
 329 #define MIN_YIELD_PERIOD 5  /* ticks */
 330 static long next_yield = 0;
 331
 332 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 333 static const char         sd_thread_name[] = "ata/sd";
 334 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 335 static struct event_queue sd_queue;
 336 #ifndef BOOTLOADER
 337 bool sd_enabled = false;
 338 #endif
 339
 340 static struct wakeup transfer_completion_signal;
 341 static volatile bool retry;
 342
 343 #if defined(HAVE_MULTIDRIVE)
 344 int active_card = 0;
 345 #endif
 346
 347 static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
 348
 349 void INT_NAND(void)
 350 {
 351     MCI_CTRL &= ~INT_ENABLE;
 352     const int status = MCI_MASK_STATUS;
 353
 354     MCI_RAW_STATUS = status;    /* clear status */
 355
 356     if(status & MCI_DATA_ERROR)
 357         retry = true;
 358
 359     if( status & (MCI_INT_DTO|MCI_DATA_ERROR))
 360         wakeup_signal(&transfer_completion_signal);
 361
 362     MCI_CTRL |= INT_ENABLE;
 363 }
 364
 365 static inline bool card_detect_target(void)
 366 {
 367 #if defined(HAVE_MULTIDRIVE)
 368 #if defined(SANSA_FUZEV2)
 369     return GPIOA_PIN(2);
 370 #elif defined(SANSA_CLIPPLUS)
 371     return !(GPIOA_PIN(2));
 372 #else
 373 #error "microSD pin not defined for your target"
 374 #endif
 375 #else
 376     return false;
 377 #endif
 378 }
 379
 380 static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
 381         unsigned long *response)
 382 {
 383 #if defined(HAVE_MULTIDRIVE)
 384     /*  Check to see if we need to switch cards  */
 385     if(sd_present(SD_SLOT_AS3525))
 386          if(active_card != drive)
 387         {
 388             GPIOB_PIN(5) = (1-drive) << 5;
 389             active_card = drive;
 390         }
 391 #endif
 392
 393 #define TRANSFER_CMD  (cmd == SD_READ_MULTIPLE_BLOCK ||   \
 394                        cmd == SD_WRITE_MULTIPLE_BLOCK)
 395
 396     MCI_ARGUMENT = arg;
 397
 398     /* Construct MCI_COMMAND  */
 399     MCI_COMMAND =
 400       /*b5:0*/    cmd
 401       /*b6  */  | ((flags & MCI_RESP)                ? CMD_RESP_EXP_BIT:      0)
 402       /*b7  */  | ((flags & MCI_LONG_RESP)           ? CMD_RESP_LENGTH_BIT:   0)
 403       /*b8      | CMD_CHECK_CRC_BIT       unused  */
 404       /*b9  */  | (TRANSFER_CMD                      ? CMD_DATA_EXP_BIT:      0)
 405       /*b10 */  | ((cmd == SD_WRITE_MULTIPLE_BLOCK)  ? CMD_RW_BIT:            0)
 406       /*b11     | CMD_TRANSMODE_BIT       unused  */
 407       /*b12     | CMD_SENT_AUTO_STOP_BIT  unused  */
 408       /*b13 */  | (TRANSFER_CMD                      ? CMD_WAIT_PRV_DAT_BIT:  0)
 409       /*b14     | CMD_ABRT_CMD_BIT        unused  */
 410       /*b15     | CMD_SEND_INIT_BIT       unused  */
 411    /*b20:16 */  |                                      CMD_CARD_NO(drive)
 412       /*b21     | CMD_SEND_CLK_ONLY       unused  */
 413       /*b22     | CMD_READ_CEATA          unused  */
 414       /*b23     | CMD_CCS_EXPECTED        unused  */
 415       /*b31 */  |                                      CMD_DONE_BIT;
 416
 417     int max = 0x40000;
 418     while(MCI_COMMAND & CMD_DONE_BIT)
 419     {
 420         if(--max == 0)  /* timeout */
 421             return false;
 422     }
 423
 424     /* TODO  Check crc values to determine if the response was valid  */
 425     if(flags & MCI_RESP)
 426     {
 427         int i = 0xff; while(i--) ;
 428         /* if we read the response too fast we might read the response
 429          * of the previous command instead */
 430
 431         if(flags & MCI_LONG_RESP)
 432         {
 433             response[0] = MCI_RESP3;
 434             response[1] = MCI_RESP2;
 435             response[2] = MCI_RESP1;
 436             response[3] = MCI_RESP0;
 437         }
 438         else
 439             response[0] = MCI_RESP0;
 440     }
 441     return true;
 442 }
 443
 444 static int sd_init_card(const int drive)
 445 {
 446     unsigned long response;
 447     long init_timeout;
 448     bool sd_v2 = false;
 449
 450     /*  assume 24 MHz clock / 60 = 400 kHz  */
 451     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
 452
 453     /* 100 - 400kHz clock required for Identification Mode  */
 454     /*  Start of Card Identification Mode ************************************/
 455
 456     /* CMD0 Go Idle  */
 457     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 458         return -1;
 459     mci_delay();
 460
 461     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 462       Non v2 cards will not respond to this command*/
 463     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 464         if((response & 0xFFF) == 0x1AA)
 465             sd_v2 = true;
 466
 467     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 468     init_timeout = current_tick + HZ;
 469
 470     do {
 471         /* this timeout is the only valid error for this loop*/
 472         if(TIME_AFTER(current_tick, init_timeout))
 473             return -2;
 474
 475         /* app_cmd */
 476         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP, &response);
 477
 478          /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 479         if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 480                         MCI_RESP, &card_info[drive].ocr))
 481             return -3;
 482     } while(!(card_info[drive].ocr & (1<<31)) );
 483
 484     /* CMD2 send CID */
 485     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
 486         return -4;
 487
 488     /* CMD3 send RCA */
 489     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 490         return -5;
 491
 492 #ifdef HAVE_MULTIDRIVE
 493     /* Make sure we have 2 unique rca numbers */
 494     if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
 495         if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 496             return -6;
 497 #endif
 498     /*  End of Card Identification Mode   ************************************/
 499
 500     /* Attempt to switch cards to HS timings, non HS cards just ignore this */
 501     /*  CMD7 w/rca: Select card to put it in TRAN state */
 502     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 503         return -7;
 504
 505     if(sd_wait_for_state(drive, SD_TRAN))
 506         return -8;
 507
 508     /* CMD6 */
 509     if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 510         return -9;
 511     mci_delay();
 512
 513     /*  We need to go back to STBY state now so we can read csd */
 514     /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 515     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_RESP, &response))
 516         return -10;
 517
 518     /* CMD9 send CSD */
 519     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 520                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 521         return -11;
 522
 523     sd_parse_csd(&card_info[drive]);
 524
 525     /*  Card back to full speed  */
 526     MCI_CLKDIV &= ~(0xFF);    /* CLK_DIV_0 : bits 7:0 = 0x00 */
 527
 528 #ifndef HAVE_MULTIDRIVE
 529     /*  CMD7 w/rca: Select card to put it in TRAN state */
 530     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 531         return -12;
 532 #endif
 533
 534     card_info[drive].initialized = 1;
 535
 536     return 0;
 537 }
 538
 539 static void sd_thread(void) __attribute__((noreturn));
 540 static void sd_thread(void)
 541 {
 542     struct queue_event ev;
 543     bool idle_notified = false;
 544
 545     while (1)
 546     {
 547         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 548
 549         switch ( ev.id )
 550         {
 551 #ifdef HAVE_HOTSWAP
 552         case SYS_HOTSWAP_INSERTED:
 553         case SYS_HOTSWAP_EXTRACTED:
 554         {
 555             int microsd_init = 1;
 556             fat_lock();          /* lock-out FAT activity first -
 557                                     prevent deadlocking via disk_mount that
 558                                     would cause a reverse-order attempt with
 559                                     another thread */
 560             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 561                                     into driver that bypass the fat cache */
 562
 563             /* We now have exclusive control of fat cache and ata */
 564
 565             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 566                                     descriptors aren't leaked and any busy
 567                                     ones are invalid if mounting */
 568             /* Force card init for new card, re-init for re-inserted one or
 569              * clear if the last attempt to init failed with an error. */
 570             card_info[SD_SLOT_AS3525].initialized = 0;
 571
 572             if (ev.id == SYS_HOTSWAP_INSERTED)
 573             {
 574                 sd_enable(true);
 575                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 576                 if (microsd_init < 0) /* initialisation failed */
 577                     panicf("microSD init failed : %d", microsd_init);
 578
 579                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 580             }
 581
 582             /*
 583              * Mount succeeded, or this was an EXTRACTED event,
 584              * in both cases notify the system about the changed filesystems
 585              */
 586             if (microsd_init)
 587                 queue_broadcast(SYS_FS_CHANGED, 0);
 588             /* Access is now safe */
 589             mutex_unlock(&sd_mtx);
 590             fat_unlock();
 591             sd_enable(false);
 592         }
 593             break;
 594 #endif
 595         case SYS_TIMEOUT:
 596             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 597             {
 598                 idle_notified = false;
 599             }
 600             else
 601             {
 602                 /* never let a timer wrap confuse us */
 603                 next_yield = current_tick;
 604
 605                 if (!idle_notified)
 606                 {
 607                     call_storage_idle_notifys(false);
 608                     idle_notified = true;
 609                 }
 610             }
 611             break;
 612
 613         case SYS_USB_CONNECTED:
 614             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 615             /* Wait until the USB cable is extracted again */
 616             usb_wait_for_disconnect(&sd_queue);
 617
 618             break;
 619         case SYS_USB_DISCONNECTED:
 620             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 621             break;
 622         }
 623     }
 624 }
 625
 626 static void init_controller(void)
 627 {
 628     int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
 629     int card_mask = (1 << hcon_numcards) - 1;
 630
 631     MCI_PWREN &= ~card_mask;            /*  power off all cards  */
 632
 633     MCI_CLKSRC = 0x00;                  /* All CLK_SRC_CRD set to 0*/
 634     MCI_CLKDIV = 0x00;                  /* CLK_DIV_0 : bits 7:0  */
 635
 636     MCI_PWREN |= card_mask;             /*  power up cards  */
 637     mci_delay();
 638
 639     MCI_CTRL |= CTRL_RESET;
 640     while(MCI_CTRL & CTRL_RESET)
 641         ;
 642
 643     MCI_RAW_STATUS = 0xffffffff;        /* Clear all MCI Interrupts  */
 644
 645     MCI_TMOUT = 0xffffffff;             /*  data b31:8, response b7:0 */
 646
 647     MCI_CTYPE = 0x0;                    /*  all cards 1 bit bus for now */
 648
 649     MCI_CLKENA = card_mask;             /*  Enables card clocks  */
 650
 651     MCI_ARGUMENT = 0;
 652     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 653     while(MCI_COMMAND & CMD_DONE_BIT)
 654         ;
 655
 656     MCI_DEBNCE = 0xfffff;               /* default value */
 657
 658     /* Rx watermark = 63(sd reads)  Tx watermark = 128 (sd writes) */
 659     MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
 660
 661     GPIOB_DIR |= (1<<5);                 /* Set pin B5 to output  */
 662
 663     /* Mask all MCI Interrupts initially  */
 664     MCI_MASK = 0;
 665
 666     MCI_CTRL |= INT_ENABLE;
 667 }
 668
 669 int sd_init(void)
 670 {
 671     int ret;
 672
 673     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 674
 675     CGU_IDE =   (1<<7)          /* AHB interface enable */
 676             |   (AS3525_IDE_DIV << 2)
 677             |   1;              /* clock source = PLLA */
 678
 679     CGU_MEMSTICK =  (1<<7)      /* interface enable */
 680                  |  (AS3525_MS_DIV << 2)
 681                  |  1;          /* clock source = PLLA */
 682
 683     CGU_SDSLOT = (1<<7)         /* interface enable */
 684                | (AS3525_SDSLOT_DIV << 2)
 685                | 1;             /* clock source = PLLA */
 686
 687     wakeup_init(&transfer_completion_signal);
 688
 689 #ifdef HAVE_MULTIDRIVE
 690     /* setup isr for microsd monitoring */
 691     VIC_INT_ENABLE = (INTERRUPT_GPIOA);
 692     /* clear previous irq */
 693     GPIOA_IC = (1<<2);
 694     /* enable edge detecting */
 695     GPIOA_IS &= ~(1<<2);
 696     /* detect both raising and falling edges */
 697     GPIOA_IBE |= (1<<2);
 698     /* Configure XPD for SD-MCI interface */
 699     CCU_IO |= (1<<2);
 700 #endif
 701
 702     VIC_INT_ENABLE = INTERRUPT_NAND;
 703
 704     init_controller();
 705     ret = sd_init_card(INTERNAL_AS3525);
 706     if(ret < 0)
 707         return ret;
 708
 709     /* init mutex */
 710     mutex_init(&sd_mtx);
 711
 712     queue_init(&sd_queue, true);
 713     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 714             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 715
 716 #ifndef BOOTLOADER
 717     sd_enabled = true;
 718     sd_enable(false);
 719 #endif
 720     return 0;
 721 }
 722
 723 static int sd_wait_for_state(const int drive, unsigned int state)
 724 {
 725     unsigned long response;
 726     unsigned int timeout = 100; /* ticks */
 727     long t = current_tick;
 728
 729     while (1)
 730     {
 731         long tick;
 732
 733         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca,
 734                     MCI_RESP, &response))
 735             return -1;
 736
 737         if (((response >> 9) & 0xf) == state)
 738             return 0;
 739
 740         if(TIME_AFTER(current_tick, t + timeout))
 741             return -10 * ((response >> 9) & 0xf);
 742
 743         if (TIME_AFTER((tick = current_tick), next_yield))
 744         {
 745             yield();
 746             timeout += current_tick - tick;
 747             next_yield = tick + MIN_YIELD_PERIOD;
 748         }
 749     }
 750 }
 751
 752 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 753                                 int count, void* buf, bool write)
 754 {
 755     int ret = 0;
 756 #ifndef HAVE_MULTIDRIVE
 757     const int drive = 0;
 758 #endif
 759
 760     /* skip SanDisk OF */
 761     if (drive == INTERNAL_AS3525)
 762         start += 0xf000;
 763
 764     mutex_lock(&sd_mtx);
 765 #ifndef BOOTLOADER
 766     sd_enable(true);
 767     led(true);
 768 #endif
 769
 770     if (card_info[drive].initialized <= 0)
 771     {
 772         ret = sd_init_card(drive);
 773         if (!(card_info[drive].initialized))
 774         {
 775             panicf("card not initialised (%d)", ret);
 776             goto sd_transfer_error;
 777         }
 778     }
 779
 780 #ifdef HAVE_MULTIDRIVE
 781     /*  CMD7 w/rca: Select card to put it in TRAN state */
 782     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 783         return -6;
 784 #endif
 785
 786     last_disk_activity = current_tick;
 787     dma_retain();
 788
 789     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 790
 791     do
 792     {
 793         void *dma_buf = aligned_buffer;
 794         unsigned int transfer = count;
 795         if(transfer > UNALIGNED_NUM_SECTORS)
 796             transfer = UNALIGNED_NUM_SECTORS;
 797
 798         if(write)
 799             memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 800
 801         /* Interrupt handler might set this to true during transfer */
 802         retry = false;
 803
 804         MCI_BLKSIZ = SD_BLOCK_SIZE;
 805         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
 806
 807         ret = sd_wait_for_state(drive, SD_TRAN);
 808         if (ret < 0)
 809         {
 810             static const char *st[9] = {
 811                 "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV",
 812                                                                 "PRG", "DIS"};
 813             if(ret <= -10)
 814                 panicf("wait for TRAN state failed (%s) %d",
 815                                                     st[(-ret / 10) % 9], drive);
 816             else
 817                 panicf("wait for state failed");
 818             goto sd_transfer_error;
 819         }
 820
 821         MCI_MASK |= (MCI_DATA_ERROR | MCI_INT_DTO);
 822         MCI_CTRL |= DMA_ENABLE;
 823
 824         int arg = start;
 825         if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
 826             arg *= SD_BLOCK_SIZE;
 827
 828         if(!send_cmd(drive, cmd, arg, MCI_NO_RESP, NULL))
 829             panicf("%s multiple blocks failed", write ? "write" : "read");
 830
 831         if(write)
 832             dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
 833                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 834         else
 835             dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
 836                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 837
 838         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 839
 840         MCI_MASK &= ~(MCI_DATA_ERROR | MCI_INT_DTO);
 841
 842         last_disk_activity = current_tick;
 843
 844         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
 845         {
 846             ret = -666;
 847             panicf("STOP TRANSMISSION failed");
 848             goto sd_transfer_error;
 849         }
 850
 851         if(!retry)
 852         {
 853             if(!write)
 854                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 855             buf += transfer * SD_BLOCK_SIZE;
 856             start += transfer;
 857             count -= transfer;
 858         }
 859         else   /*  reset controller if we had an error  */
 860         {
 861             MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 862             while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 863                 ;
 864         }
 865
 866     } while(retry || count);
 867
 868     dma_release();
 869
 870 #ifdef HAVE_MULTIDRIVE
 871     /* CMD lines are separate, not common, so we need to actively deselect */
 872     /*  CMD7 w/rca =0 : deselects card & puts it in STBY state */
 873     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 874         return -6;
 875 #endif
 876
 877 #ifndef BOOTLOADER
 878     sd_enable(false);
 879     led(false);
 880 #endif
 881     mutex_unlock(&sd_mtx);
 882     return 0;
 883
 884 sd_transfer_error:
 885     panicf("transfer error : %d",ret);
 886     card_info[drive].initialized = 0;
 887     return ret;
 888 }
 889
 890 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 891                     void* buf)
 892 {
 893     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 894 }
 895
 896 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 897                      const void* buf)
 898 {
 899 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
 900 #ifdef HAVE_MULTIDRIVE
 901     (void) drive;
 902 #endif
 903     (void) start;
 904     (void) count;
 905     (void) buf;
 906     return -1;
 907 #else
 908     //return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 909     return -1; /* not working, seems to cause FIFO overruns */
 910 #endif
 911 }
 912
 913 #ifndef BOOTLOADER
 914 long sd_last_disk_activity(void)
 915 {
 916     return last_disk_activity;
 917 }
 918
 919 void sd_enable(bool on)
 920 {
 921     /* TODO */
 922     (void) on;
 923 }
 924
 925 tCardInfo *card_get_info_target(int card_no)
 926 {
 927     return &card_info[card_no];
 928 }
 929 #endif /* BOOTLOADER */
 930
 931 #ifdef HAVE_HOTSWAP
 932 bool sd_removable(IF_MD_NONVOID(int drive))
 933 {
 934     return (drive==1);
 935 }
 936
 937 bool sd_present(IF_MD_NONVOID(int drive))
 938 {
 939     return (drive == 0) ? true : card_detect_target();
 940 }
 941
 942 static int sd1_oneshot_callback(struct timeout *tmo)
 943 {
 944     (void)tmo;
 945
 946     /* This is called only if the state was stable for 300ms - check state
 947  *      * and post appropriate event. */
 948     if (card_detect_target())
 949     {
 950         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 951     }
 952     else
 953         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 954
 955     return 0;
 956 }
 957
 958 void INT_GPIOA(void)
 959 {
 960     static struct timeout sd1_oneshot;
 961     /* acknowledge interrupt */
 962     GPIOA_IC = (1<<2);
 963     timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 964 }
 965
 966 void card_enable_monitoring_target(bool on)
 967 {
 968     if (on) /* enable interrupt */
 969         GPIOA_IE |= (1<<2);
 970     else    /* disable interrupt */
 971         GPIOA_IE &= ~(1<<2);
 972 }
 973 #endif /* HAVE_HOTSWAP */
 974
 975 #ifdef CONFIG_STORAGE_MULTI
 976 int sd_num_drives(int first_drive)
 977 {
 978     /* We don't care which logical drive number(s) we have been assigned */
 979     (void)first_drive;
 980
 981     return NUM_DRIVES;
 982 }
 983 #endif /* CONFIG_STORAGE_MULTI */