firmware/export/pl180.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2008 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 /* ARM PrimeCell PL180 SD/MMC controller */
  23
  24 /* MCIStatus bits */
  25
  26 /* bits 10:0 can be cleared by a write in MCIClear */
  27 #define MCI_CMD_CRC_FAIL    (1<<0)
  28 #define MCI_DATA_CRC_FAIL   (1<<1)
  29 #define MCI_CMD_TIMEOUT     (1<<2)
  30 #define MCI_DATA_TIMEOUT    (1<<3)
  31 #define MCI_TX_UNDERRUN     (1<<4)
  32 #define MCI_RX_OVERRUN      (1<<5)
  33 #define MCI_CMD_RESP_END    (1<<6)
  34 #define MCI_CMD_SENT        (1<<7)
  35 #define MCI_DATA_END        (1<<8)
  36 #define MCI_START_BIT_ERR   (1<<9)
  37 #define MCI_DATA_BLOCK_END  (1<<10)
  38 /* bits 21:11 are only cleared by the hardware logic */
  39 #define MCI_CMD_ACTIVE          (1<<11)
  40 #define MCI_TX_ACTIVE           (1<<12)
  41 #define MCI_RX_ACTIVE           (1<<13)
  42 #define MCI_TX_FIFO_HALF_EMPTY  (1<<14)
  43 #define MCI_RX_FIFO_HALF_FULL   (1<<15)
  44 #define MCI_TX_FIFO_FULL        (1<<16)
  45 #define MCI_RX_FIFO_FULL        (1<<17)
  46 #define MCI_TX_FIFO_EMPTY       (1<<18)
  47 #define MCI_RX_FIFO_EMPTY       (1<<19)
  48 #define MCI_TX_DATA_AVAIL       (1<<20)
  49 #define MCI_RX_DATA_AVAIL       (1<<21)
  50
  51
  52 /* MCIPower bits */
  53 #define MCI_POWER_OFF           0x0
  54 /* 0x1 is reserved */
  55 #define MCI_POWER_UP            0x2
  56 #define MCI_POWER_ON            0x3
  57
  58 /* bits 5:2 are the voltage */
  59 #define MCI_VDD_2_0              (0<<2)      /* 2.0 - 2.6 comm only  */
  60 #define MCI_VDD_2_1              (1<<2)
  61 #define MCI_VDD_2_2              (2<<2)
  62 #define MCI_VDD_2_3              (3<<2)
  63 #define MCI_VDD_2_4              (4<<2)
  64 #define MCI_VDD_2_5              (5<<2)
  65 #define MCI_VDD_2_6              (6<<2)
  66
  67 #define MCI_VDD_2_7              (7<<2)     /*  2.7 - 3.6  Data Transfer  */
  68 #define MCI_VDD_2_8              (8<<2)
  69 #define MCI_VDD_2_9              (9<<2)
  70 #define MCI_VDD_3_0              (10<<2)
  71 #define MCI_VDD_3_1              (11<<2)
  72 #define MCI_VDD_3_2              (12<<2)
  73 #define MCI_VDD_3_3              (13<<2)
  74 #define MCI_VDD_3_4              (14<<2)
  75 #define MCI_VDD_3_5              (15<<2)
  76
  77 #define MCI_POWER_OPEN_DRAIN    (1<<6)
  78 #define MCI_POWER_ROD           (1<<7)
  79
  80
  81 /* MCIClock bits */
  82 /* bits 7:0 are the clock divider */
  83 #define MCI_CLOCK_ENABLE        (1<<8)
  84 #define MCI_CLOCK_POWERSAVE     (1<<9)
  85 #define MCI_CLOCK_BYPASS        (1<<10)
  86 #define MCI_CLOCK_WIDEBUS       (1<<11)
  87
  88
  89 /* MCICommand bits */
  90 /* bits 5:0 are the command index */
  91 #define MCI_COMMAND_RESPONSE        (1<<6)
  92 #define MCI_COMMAND_LONG_RESPONSE   (1<<7)
  93 #define MCI_COMMAND_INTERRUPT       (1<<8)
  94 #define MCI_COMMAND_PENDING         (1<<9)
  95 #define MCI_COMMAND_ENABLE          (1<<10)