firmware/target/arm/tms320dm320/mrobe-500/ata-mr500.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by Karl Kurbjun
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "config.h"
  23 #include "cpu.h"
  24 #include "kernel.h"
  25 #include "thread.h"
  26 #include "system.h"
  27 #include "power.h"
  28 #include "panic.h"
  29 #include "pcf50606.h"
  30 #include "ata.h"
  31 #include "ata-target.h"
  32 #include "backlight-target.h"
  33
  34 /* ARESET on C7C68300 and RESET on ATA interface (Active Low) */
  35 #define ATA_RESET_ENABLE  (IO_GIO_BITCLR0 = 1 << 10)
  36 #define ATA_RESET_DISABLE (IO_GIO_BITSET0 = 1 << 10)
  37
  38 /* ATA_EN on C7C68300 */
  39 #define USB_ATA_ENABLE    (IO_GIO_BITSET0 = 1 << 2)
  40 #define USB_ATA_DISABLE   (IO_GIO_BITCLR0 = 1 << 2)
  41
  42 void ata_reset(void)
  43 {
  44     ATA_RESET_ENABLE;
  45     sleep(1); /* > 25us */
  46     ATA_RESET_DISABLE;
  47     sleep(1); /* > 2ms */
  48 }
  49
  50 /* This function is called before enabling the USB bus */
  51 void ata_enable(bool on)
  52 {
  53     if(on)
  54         USB_ATA_DISABLE;
  55     else
  56         USB_ATA_ENABLE;
  57 }
  58
  59 bool ata_is_coldstart(void)
  60 {
  61     return true;
  62 }
  63
  64 void ata_device_init(void)
  65 {
  66     /* ATA reset */
  67     ATA_RESET_DISABLE; /* Set the pin to disable an active low reset */
  68     IO_GIO_DIR0&=~(1<<10);
  69 }
  70
  71 #if 0
  72 void copy_read_sectors(unsigned char* buf, int wordcount)
  73 {
  74     __buttonlight_trigger();
  75
  76     /* Unaligned transfer - slow copy */
  77     if ( (unsigned long)buf & 1)
  78     {   /* not 16-bit aligned, copy byte by byte */
  79         unsigned short tmp = 0;
  80         unsigned char* bufend = buf + wordcount*2;
  81         do
  82         {
  83             tmp = ATA_DATA;
  84             *buf++ = tmp & 0xff; /* I assume big endian */
  85             *buf++ = tmp >> 8;   /*  and don't use the SWAB16 macro */
  86         } while (buf < bufend); /* tail loop is faster */
  87         return;
  88     }
  89     /* This should never happen, but worth watching for */
  90     if(wordcount > (1 << 18))
  91         panicf("atd-meg-fx.c: copy_read_sectors: too many sectors per read!");
  92
  93 //#define GIGABEAT_DEBUG_ATA
  94 #ifdef GIGABEAT_DEBUG_ATA
  95         static int line = 0;
  96         static char str[256];
  97         snprintf(str, sizeof(str), "ODD DMA to %08x, %d", buf, wordcount);
  98         lcd_puts(10, line, str);
  99         line = (line+1) % 32;
 100         lcd_update();
 101 #endif
 102     /* Reset the channel */
 103     DMASKTRIG0 |= 4;
 104     /* Wait for DMA controller to be ready */
 105     while(DMASKTRIG0 & 0x2)
 106         ;
 107     while(DSTAT0 & (1 << 20))
 108         ;
 109     /* Source is ATA_DATA, on AHB Bus, Fixed */
 110     DISRC0 = (int) 0x18000000;
 111     DISRCC0 = 0x1;
 112     /* Dest mapped to physical address, on AHB bus, increment */
 113     DIDST0 = (int) buf;
 114         if(DIDST0 < 0x30000000)
 115                 DIDST0 += 0x30000000;
 116     DIDSTC0 = 0;
 117
 118     /* DACK/DREQ Sync to AHB, Whole service, No reload, 16-bit transfers */
 119     DCON0 = ((1 << 30) | (1<<27) | (1<<22) | (1<<20)) | wordcount;
 120
 121     /* Activate the channel */
 122     DMASKTRIG0 = 0x2;
 123
 124     invalidate_dcache_range((void *)buf, wordcount*2);
 125
 126     /* Start DMA */
 127     DMASKTRIG0 |= 0x1;
 128
 129     /* Wait for transfer to complete */
 130     while((DSTAT0 & 0x000fffff))
 131         priority_yield();
 132     /* Dump cache for the buffer  */
 133 }
 134 #endif