firmware/export/tlv320.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2005 by Christian Gmeiner
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #ifndef _TLV320_H_
  23 #define _TLV320_H_
  24
  25 #define VOLUME_MIN -730
  26 #define VOLUME_MAX  60
  27
  28 extern int tenthdb2master(int db);
  29
  30 /*** definitions ***/
  31
  32 /**
  33  * Sets internal sample rate for DAC and ADC relative to MCLK
  34  * Selection for frequency:
  35  * Fs:        tlv:   with:
  36  * 11025: 0 = MCLK/2 MCLK/2  SCLK, LRCK: Audio Clk / 16
  37  * 22050: 0 = MCLK/2 MCLK    SCLK, LRCK: Audio Clk / 8
  38  * 44100: 1 = MCLK   MCLK    SCLK, LRCK: Audio Clk / 4 (default)
  39  * 88200: 2 = MCLK*2 MCLK    SCLK, LRCK: Audio Clk / 2
  40  */
  41 extern void audiohw_set_frequency(int fsel);
  42 extern void audiohw_set_headphone_vol(int vol_l, int vol_r);
  43
  44 #define HEADPHONE_MUTE 0x30 /* 0110000 = -73db */
  45
  46 /* ToDo: samplerates */
  47
  48 /* registers */
  49 /* REG_LLIV: Left line input channel volume control */
  50 #define REG_LLIV        0x0
  51 #define LLIV_LRS        (1 << 8)    /* simultaneous volume/mute update  */
  52 #define LLIV_LIM        (1 << 7)    /* Left line input mute             */
  53 #define LLIV_LIV(x)     ((x) & 0x1f)/* Left line input volume control   */
  54
  55 /* REG_RLIV: Right line input channel volume control */
  56 #define REG_RLIV        0x1
  57 #define RLIV_RLS        (1 << 8)    /* simultaneous volume/mute update  */
  58 #define RLIV_RIM        (1 << 7)    /* Right line input mute            */
  59 #define RLIV_RIV(x)     ((x) & 0x1f)/* Right line input volume control  */
  60
  61 /* REG_LHV: Left Channel Headphone Volume Control */
  62 #define REG_LHV         0x2
  63 #define LHV_LRS         (1 << 8)    /* simultaneous volume/mute update */
  64 #define LHV_LZC         (1 << 7)    /* Left-channel zero-cross detect  */
  65 #define LHV_LHV(x)      ((x) & 0x7f)/* Left headphone volume control    */
  66
  67 /* REG_RHV: Right Channel Headphone Volume Control */
  68 #define REG_RHV         0x3
  69 #define RHV_LRS         (1 << 8)    /* simultaneous volume/mute update  */
  70 #define RHV_RZC         (1 << 7)    /* Right-channel zero-cross detect  */
  71 #define RHV_RHV(x)      ((x) & 0x7f)/* Right headphone volume control   */
  72
  73 /* REG_AAP: Analog Audio Path Control */
  74 #define REG_AAP         0x4
  75 #define AAP_DAC         (1 << 4)    /* DAC select           */
  76 #define AAP_BYPASS      (1 << 3)    /* bypass               */
  77 #define AAP_INSEL       (1 << 2)    /* Input select for ADC */
  78 #define AAP_MICM        (1 << 1)    /* Microphone mute      */
  79 #define AAP_MICB        (1 << 0)    /* Microphone boost     */
  80
  81 /* REG_DAP: Digital Audio Path Control */
  82 #define REG_DAP         0x5
  83 #define DAP_DACM        (1 << 3)    /* DAC soft mute                    */
  84 #define DAP_DEEMP_32    (1 << 1)    /* De-emphasis control: 32 kHz      */
  85 #define DAP_DEEMP_44    (2 << 1)    /* De-emphasis control: 44.1 kHz    */
  86 #define DAP_DEEMP_48    (3 << 1)    /* De-emphasis control: 48 kHz      */
  87 #define DAP_ADCHP       (1 << 0)    /* ADC high-pass filter             */
  88
  89 /* REG_PC: Power Down Control */
  90 #define REG_PC          0x6
  91 #define PC_OFF          (1 << 7)    /* Device power     */
  92 #define PC_CLK          (1 << 6)    /* Clock            */
  93 #define PC_OSC          (1 << 5)    /* Oscillator       */
  94 #define PC_OUT          (1 << 4)    /* Outputs          */
  95 #define PC_DAC          (1 << 3)    /* DAC              */
  96 #define PC_ADC          (1 << 2)    /* ADC              */
  97 #define PC_MIC          (1 << 1)    /* Microphone input */
  98 #define PC_LINE         (1 << 0)    /* Line input       */
  99
 100 /* REG_DAIF: Digital Audio Interface Format */
 101 #define REG_DAIF        0x7
 102 #define DAIF_MS         (1 << 6)    /* Master/slave mode                        */
 103 #define DAIF_LRSWAP     (1 << 5)    /* DAC left/right swap                      */
 104 #define DAIF_LRP        (1 << 4)    /* DAC left/right phase                     */
 105 #define DAIF_IWL_16     (0 << 2)    /* Input bit length: 16 bit                 */
 106 #define DAIF_IWL_20     (1 << 2)    /* Input bit length: 20 bit                 */
 107 #define DAIF_IWL_24     (2 << 2)    /* Input bit length: 24 bit                 */
 108 #define DAIF_IWL_32     (3 << 2)    /* Input bit length: 32 bit                 */
 109 #define DAIF_FOR_DSP    (3 << 0)    /* Data format: DSP                         */
 110 #define DAIF_FOR_I2S    (2 << 0)    /* Data format: I2S                         */
 111 #define DAIF_FOR_MSBL   (1 << 0)    /* Data format: MSB first, left aligned     */
 112 #define DAIF_FOR_MSBR   (0 << 0)    /* Data format: MSB first, right aligned    */
 113
 114 /* REG_SRC: Sample Rate Control */
 115 #define REG_SRC         0x8
 116 #define SRC_CLKIN       (1 << 6)    /* Clock input divider                          */
 117 #define SRC_CLKOUT      (1 << 7)    /* Clock output divider                         */
 118 /*#define SRC_SR        ()*/
 119 #define SRC_BOSR        (1 << 1)    /* Base oversampling rate, depends on SRC_USB   */
 120 #define SRC_USB         (1 << 0)    /* Clock mode select                            */
 121
 122 /* REG_DIA: Digital Interface Activation */
 123 #define REG_DIA         0x9
 124 #define DIA_ACT         (1 << 0)    /* Activate interface */
 125
 126 /* REG_RR: Reset Register */
 127 #define REG_RR          0xf
 128 #define RR_RESET        0           /* Reset */
 129
 130 #endif /*_TLV320_H_*/