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- inline asm optimizations by Stanislav
[gplbios.git] / rombios32.c
blob1f07f2a5888039ea45d3e6cdc2b411cab0e2cb71
1 /////////////////////////////////////////////////////////////////////////
2 // $Id$
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // 32 bit Bochs BIOS init code
6 // Copyright (C) 2006 Fabrice Bellard
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <stdarg.h>
22 #include <stddef.h>
23
24 #include "rombios.h"
25
26 typedef signed char int8_t;
27 typedef short int16_t;
28 typedef int int32_t;
29 typedef long long int64_t;
30 typedef unsigned char uint8_t;
31 typedef unsigned short uint16_t;
32 typedef unsigned int uint32_t;
33 typedef unsigned long long uint64_t;
34
35 /* if true, put the MP float table and ACPI RSDT in EBDA and the MP
36 table in RAM. Unfortunately, Linux has bugs with that, so we prefer
37 to modify the BIOS in shadow RAM */
38 //#define BX_USE_EBDA_TABLES
39
40 /* define it if the (emulated) hardware supports SMM mode */
41 #define BX_USE_SMM
42
43 #define cpuid(index, eax, ebx, ecx, edx) \
44 asm volatile ("cpuid" \
45 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
46 : "0" (index))
47
48 #define wbinvd() asm volatile("wbinvd")
49
50 #define CPUID_APIC (1 << 9)
51
52 #define APIC_BASE ((uint8_t *)0xfee00000)
53 #define APIC_ICR_LOW 0x300
54 #define APIC_SVR 0x0F0
55 #define APIC_ID 0x020
56 #define APIC_LVT3 0x370
57
58 #define APIC_ENABLED 0x0100
59
60 #define AP_BOOT_ADDR 0x10000
61
62 #define MPTABLE_MAX_SIZE 0x00002000
63 #define SMI_CMD_IO_ADDR 0xb2
64
65 #define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
66
67 static inline void outl(int addr, int val)
68 {
69 asm volatile ("outl %1, %w0" : : "d" (addr), "a" (val));
70 }
71
72 static inline void outw(int addr, int val)
73 {
74 asm volatile ("outw %w1, %w0" : : "d" (addr), "a" (val));
75 }
76
77 static inline void outb(int addr, int val)
78 {
79 asm volatile ("outb %b1, %w0" : : "d" (addr), "a" (val));
80 }
81
82 static inline uint32_t inl(int addr)
83 {
84 uint32_t val;
85 asm volatile ("inl %w1, %0" : "=a" (val) : "d" (addr));
86 return val;
87 }
88
89 static inline uint16_t inw(int addr)
90 {
91 uint16_t val;
92 asm volatile ("inw %w1, %w0" : "=a" (val) : "d" (addr));
93 return val;
94 }
95
96 static inline uint8_t inb(int addr)
97 {
98 uint8_t val;
99 asm volatile ("inb %w1, %b0" : "=a" (val) : "d" (addr));
100 return val;
101 }
102
103 static inline void writel(void *addr, uint32_t val)
104 {
105 *(volatile uint32_t *)addr = val;
106 }
107
108 static inline void writew(void *addr, uint16_t val)
109 {
110 *(volatile uint16_t *)addr = val;
111 }
112
113 static inline void writeb(void *addr, uint8_t val)
114 {
115 *(volatile uint8_t *)addr = val;
116 }
117
118 static inline uint32_t readl(const void *addr)
119 {
120 return *(volatile const uint32_t *)addr;
121 }
122
123 static inline uint16_t readw(const void *addr)
124 {
125 return *(volatile const uint16_t *)addr;
126 }
127
128 static inline uint8_t readb(const void *addr)
129 {
130 return *(volatile const uint8_t *)addr;
131 }
132
133 static inline void putc(int c)
134 {
135 outb(INFO_PORT, c);
136 }
137
138 static inline int isdigit(int c)
139 {
140 return c >= '0' && c <= '9';
141 }
142
143 void *memset(void *d1, int val, size_t len)
144 {
145 uint8_t *d = d1;
146
147 while (len--) {
148 *d++ = val;
149 }
150 return d1;
151 }
152
153 void *memcpy(void *d1, const void *s1, size_t len)
154 {
155 uint8_t *d = d1;
156 const uint8_t *s = s1;
157
158 while (len--) {
159 *d++ = *s++;
160 }
161 return d1;
162 }
163
164 void *memmove(void *d1, const void *s1, size_t len)
165 {
166 uint8_t *d = d1;
167 const uint8_t *s = s1;
168
169 if (d <= s) {
170 while (len--) {
171 *d++ = *s++;
172 }
173 } else {
174 d += len;
175 s += len;
176 while (len--) {
177 *--d = *--s;
178 }
179 }
180 return d1;
181 }
182
183 size_t strlen(const char *s)
184 {
185 const char *s1;
186 for(s1 = s; *s1 != '\0'; s1++);
187 return s1 - s;
188 }
189
190 /* from BSD ppp sources */
191 int vsnprintf(char *buf, int buflen, const char *fmt, va_list args)
192 {
193 int c, i, n;
194 int width, prec, fillch;
195 int base, len, neg;
196 unsigned long val = 0;
197 const char *f;
198 char *str, *buf0;
199 char num[32];
200 static const char hexchars[] = "0123456789abcdef";
201
202 buf0 = buf;
203 --buflen;
204 while (buflen > 0) {
205 for (f = fmt; *f != '%' && *f != 0; ++f)
206 ;
207 if (f > fmt) {
208 len = f - fmt;
209 if (len > buflen)
210 len = buflen;
211 memcpy(buf, fmt, len);
212 buf += len;
213 buflen -= len;
214 fmt = f;
215 }
216 if (*fmt == 0)
217 break;
218 c = *++fmt;
219 width = prec = 0;
220 fillch = ' ';
221 if (c == '0') {
222 fillch = '0';
223 c = *++fmt;
224 }
225 if (c == '*') {
226 width = va_arg(args, int);
227 c = *++fmt;
228 } else {
229 while (isdigit(c)) {
230 width = width * 10 + c - '0';
231 c = *++fmt;
232 }
233 }
234 if (c == '.') {
235 c = *++fmt;
236 if (c == '*') {
237 prec = va_arg(args, int);
238 c = *++fmt;
239 } else {
240 while (isdigit(c)) {
241 prec = prec * 10 + c - '0';
242 c = *++fmt;
243 }
244 }
245 }
246 /* modifiers */
247 switch(c) {
248 case 'l':
249 c = *++fmt;
250 break;
251 default:
252 break;
253 }
254 str = 0;
255 base = 0;
256 neg = 0;
257 ++fmt;
258 switch (c) {
259 case 'd':
260 i = va_arg(args, int);
261 if (i < 0) {
262 neg = 1;
263 val = -i;
264 } else
265 val = i;
266 base = 10;
267 break;
268 case 'o':
269 val = va_arg(args, unsigned int);
270 base = 8;
271 break;
272 case 'x':
273 case 'X':
274 val = va_arg(args, unsigned int);
275 base = 16;
276 break;
277 case 'p':
278 val = (unsigned long) va_arg(args, void *);
279 base = 16;
280 neg = 2;
281 break;
282 case 's':
283 str = va_arg(args, char *);
284 break;
285 case 'c':
286 num[0] = va_arg(args, int);
287 num[1] = 0;
288 str = num;
289 break;
290 default:
291 *buf++ = '%';
292 if (c != '%')
293 --fmt; /* so %z outputs %z etc. */
294 --buflen;
295 continue;
296 }
297 if (base != 0) {
298 str = num + sizeof(num);
299 *--str = 0;
300 while (str > num + neg) {
301 *--str = hexchars[val % base];
302 val = val / base;
303 if (--prec <= 0 && val == 0)
304 break;
305 }
306 switch (neg) {
307 case 1:
308 *--str = '-';
309 break;
310 case 2:
311 *--str = 'x';
312 *--str = '0';
313 break;
314 }
315 len = num + sizeof(num) - 1 - str;
316 } else {
317 len = strlen(str);
318 if (prec > 0 && len > prec)
319 len = prec;
320 }
321 if (width > 0) {
322 if (width > buflen)
323 width = buflen;
324 if ((n = width - len) > 0) {
325 buflen -= n;
326 for (; n > 0; --n)
327 *buf++ = fillch;
328 }
329 }
330 if (len > buflen)
331 len = buflen;
332 memcpy(buf, str, len);
333 buf += len;
334 buflen -= len;
335 }
336 *buf = 0;
337 return buf - buf0;
338 }
339
340 void bios_printf(int flags, const char *fmt, ...)
341 {
342 va_list ap;
343 char buf[1024];
344 const char *s;
345
346 va_start(ap, fmt);
347 vsnprintf(buf, sizeof(buf), fmt, ap);
348 s = buf;
349 while (*s)
350 putc(*s++);
351 va_end(ap);
352 }
353
354 void delay_ms(int n)
355 {
356 int i, j;
357 for(i = 0; i < n; i++) {
358 #ifdef BX_QEMU
359 /* approximative ! */
360 for(j = 0; j < 1000000; j++);
361 #else
362 {
363 int r1, r2;
364 j = 66;
365 r1 = inb(0x61) & 0x10;
366 do {
367 r2 = inb(0x61) & 0x10;
368 if (r1 != r2) {
369 j--;
370 r1 = r2;
371 }
372 } while (j > 0);
373 }
374 #endif
375 }
376 }
377
378 int smp_cpus;
379 uint32_t cpuid_features;
380 uint32_t cpuid_ext_features;
381 unsigned long ram_size;
382 #ifdef BX_USE_EBDA_TABLES
383 unsigned long ebda_cur_addr;
384 #endif
385 int acpi_enabled;
386 uint32_t pm_io_base, smb_io_base;
387 int pm_sci_int;
388 unsigned long bios_table_cur_addr;
389 unsigned long bios_table_end_addr;
390
391 void cpu_probe(void)
392 {
393 uint32_t eax, ebx, ecx, edx;
394 cpuid(1, eax, ebx, ecx, edx);
395 cpuid_features = edx;
396 cpuid_ext_features = ecx;
397 }
398
399 static int cmos_readb(int addr)
400 {
401 outb(0x70, addr);
402 return inb(0x71);
403 }
404
405 void ram_probe(void)
406 {
407 if (cmos_readb(0x34) | cmos_readb(0x35))
408 ram_size = (cmos_readb(0x34) | (cmos_readb(0x35) << 8)) * 65536 +
409 16 * 1024 * 1024;
410 else
411 ram_size = (cmos_readb(0x17) | (cmos_readb(0x18) << 8)) * 1024;
412 #ifdef BX_USE_EBDA_TABLES
413 ebda_cur_addr = ((*(uint16_t *)(0x40e)) << 4) + 0x380;
414 #endif
415 BX_INFO("ram_size=0x%08lx\n", ram_size);
416 }
417
418 /****************************************************/
419 /* SMP probe */
420
421 extern uint8_t smp_ap_boot_code_start;
422 extern uint8_t smp_ap_boot_code_end;
423
424 /* find the number of CPUs by launching a SIPI to them */
425 void smp_probe(void)
426 {
427 uint32_t val, sipi_vector;
428
429 smp_cpus = 1;
430 if (cpuid_features & CPUID_APIC) {
431
432 /* enable local APIC */
433 val = readl(APIC_BASE + APIC_SVR);
434 val |= APIC_ENABLED;
435 writel(APIC_BASE + APIC_SVR, val);
436
437 writew((void *)CPU_COUNT_ADDR, 1);
438 /* copy AP boot code */
439 memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
440 &smp_ap_boot_code_end - &smp_ap_boot_code_start);
441
442 /* broadcast SIPI */
443 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
444 sipi_vector = AP_BOOT_ADDR >> 12;
445 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
446
447 delay_ms(10);
448
449 smp_cpus = readw((void *)CPU_COUNT_ADDR);
450 }
451 BX_INFO("Found %d cpu(s)\n", smp_cpus);
452 }
453
454 /****************************************************/
455 /* PCI init */
456
457 #define PCI_ADDRESS_SPACE_MEM 0x00
458 #define PCI_ADDRESS_SPACE_IO 0x01
459 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
460
461 #define PCI_ROM_SLOT 6
462 #define PCI_NUM_REGIONS 7
463
464 #define PCI_DEVICES_MAX 64
465
466 #define PCI_VENDOR_ID 0x00 /* 16 bits */
467 #define PCI_DEVICE_ID 0x02 /* 16 bits */
468 #define PCI_COMMAND 0x04 /* 16 bits */
469 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
470 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
471 #define PCI_CLASS_DEVICE 0x0a /* Device class */
472 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
473 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
474 #define PCI_MIN_GNT 0x3e /* 8 bits */
475 #define PCI_MAX_LAT 0x3f /* 8 bits */
476
477 typedef struct PCIDevice {
478 int bus;
479 int devfn;
480 } PCIDevice;
481
482 static uint32_t pci_bios_io_addr;
483 static uint32_t pci_bios_mem_addr;
484 static uint32_t pci_bios_bigmem_addr;
485 /* host irqs corresponding to PCI irqs A-D */
486 static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
487 static PCIDevice i440_pcidev;
488
489 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
490 {
491 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
492 outl(0xcfc, val);
493 }
494
495 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
496 {
497 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
498 outw(0xcfc + (addr & 2), val);
499 }
500
501 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
502 {
503 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
504 outb(0xcfc + (addr & 3), val);
505 }
506
507 static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
508 {
509 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
510 return inl(0xcfc);
511 }
512
513 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
514 {
515 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
516 return inw(0xcfc + (addr & 2));
517 }
518
519 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
520 {
521 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
522 return inb(0xcfc + (addr & 3));
523 }
524
525 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
526 {
527 uint16_t cmd;
528 uint32_t ofs, old_addr;
529
530 if ( region_num == PCI_ROM_SLOT ) {
531 ofs = 0x30;
532 }else{
533 ofs = 0x10 + region_num * 4;
534 }
535
536 old_addr = pci_config_readl(d, ofs);
537
538 pci_config_writel(d, ofs, addr);
539 BX_INFO("region %d: 0x%08x\n", region_num, addr);
540
541 /* enable memory mappings */
542 cmd = pci_config_readw(d, PCI_COMMAND);
543 if ( region_num == PCI_ROM_SLOT )
544 cmd |= 2;
545 else if (old_addr & PCI_ADDRESS_SPACE_IO)
546 cmd |= 1;
547 else
548 cmd |= 2;
549 pci_config_writew(d, PCI_COMMAND, cmd);
550 }
551
552 /* return the global irq number corresponding to a given device irq
553 pin. We could also use the bus number to have a more precise
554 mapping. */
555 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
556 {
557 int slot_addend;
558 slot_addend = (pci_dev->devfn >> 3) - 1;
559 return (irq_num + slot_addend) & 3;
560 }
561
562 static int find_bios_table_area(void)
563 {
564 unsigned long addr;
565 for(addr = 0xf0000; addr < 0x100000; addr += 16) {
566 if (*(uint32_t *)addr == 0xaafb4442) {
567 bios_table_cur_addr = addr + 8;
568 bios_table_end_addr = bios_table_cur_addr + *(uint32_t *)(addr + 4);
569 BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
570 bios_table_cur_addr, bios_table_end_addr);
571 return 0;
572 }
573 }
574 return -1;
575 }
576
577 static void bios_shadow_init(PCIDevice *d)
578 {
579 int v;
580
581 if (find_bios_table_area() < 0)
582 return;
583
584 /* remap the BIOS to shadow RAM an keep it read/write while we
585 are writing tables */
586 v = pci_config_readb(d, 0x59);
587 v &= 0xcf;
588 pci_config_writeb(d, 0x59, v);
589 memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
590 v |= 0x30;
591 pci_config_writeb(d, 0x59, v);
592 memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
593
594 i440_pcidev = *d;
595 }
596
597 static void bios_lock_shadow_ram(void)
598 {
599 PCIDevice *d = &i440_pcidev;
600 int v;
601
602 wbinvd();
603 v = pci_config_readb(d, 0x59);
604 v = (v & 0x0f) | (0x10);
605 pci_config_writeb(d, 0x59, v);
606 }
607
608 static void pci_bios_init_bridges(PCIDevice *d)
609 {
610 uint16_t vendor_id, device_id;
611
612 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
613 device_id = pci_config_readw(d, PCI_DEVICE_ID);
614
615 if (vendor_id == 0x8086 && device_id == 0x7000) {
616 int i, irq;
617 uint8_t elcr[2];
618
619 /* PIIX3 bridge */
620
621 elcr[0] = 0x00;
622 elcr[1] = 0x00;
623 for(i = 0; i < 4; i++) {
624 irq = pci_irqs[i];
625 /* set to trigger level */
626 elcr[irq >> 3] |= (1 << (irq & 7));
627 /* activate irq remapping in PIIX */
628 pci_config_writeb(d, 0x60 + i, irq);
629 }
630 outb(0x4d0, elcr[0]);
631 outb(0x4d1, elcr[1]);
632 BX_INFO("PIIX3 init: elcr=%02x %02x\n",
633 elcr[0], elcr[1]);
634 } else if (vendor_id == 0x8086 && device_id == 0x1237) {
635 /* i440 PCI bridge */
636 bios_shadow_init(d);
637 }
638 }
639
640 extern uint8_t smm_relocation_start, smm_relocation_end;
641 extern uint8_t smm_code_start, smm_code_end;
642
643 #ifdef BX_USE_SMM
644 static void smm_init(PCIDevice *d)
645 {
646 /* copy the SMM relocation code */
647 memcpy((void *)0x38000, &smm_relocation_start,
648 &smm_relocation_end - &smm_relocation_start);
649
650 /* enable SMI generation when writing to the APMC register */
651 pci_config_writel(d, 0x58, pci_config_readl(d, 0x58) | (1 << 25));
652
653 /* init APM status port */
654 outb(0xb3, 0x01);
655
656 /* raise an SMI interrupt */
657 outb(0xb2, 0x00);
658
659 /* wait until SMM code executed */
660 while (inb(0xb3) != 0x00);
661
662 /* enable the SMM memory window */
663 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
664
665 /* copy the SMM code */
666 memcpy((void *)0xa8000, &smm_code_start,
667 &smm_code_end - &smm_code_start);
668 wbinvd();
669
670 /* close the SMM memory window and enable normal SMM */
671 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
672 }
673 #endif
674
675 static void pci_bios_init_device(PCIDevice *d)
676 {
677 int class;
678 uint32_t *paddr;
679 int i, pin, pic_irq, vendor_id, device_id;
680
681 class = pci_config_readw(d, PCI_CLASS_DEVICE);
682 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
683 device_id = pci_config_readw(d, PCI_DEVICE_ID);
684 BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
685 d->bus, d->devfn, vendor_id, device_id);
686 switch(class) {
687 case 0x0101:
688 if (vendor_id == 0x8086 && device_id == 0x7010) {
689 /* PIIX3 IDE */
690 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
691 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
692 goto default_map;
693 } else {
694 /* IDE: we map it as in ISA mode */
695 pci_set_io_region_addr(d, 0, 0x1f0);
696 pci_set_io_region_addr(d, 1, 0x3f4);
697 pci_set_io_region_addr(d, 2, 0x170);
698 pci_set_io_region_addr(d, 3, 0x374);
699 }
700 break;
701 case 0x0300:
702 if (vendor_id != 0x1234)
703 goto default_map;
704 /* VGA: map frame buffer to default Bochs VBE address */
705 pci_set_io_region_addr(d, 0, 0xE0000000);
706 break;
707 case 0x0800:
708 /* PIC */
709 if (vendor_id == 0x1014) {
710 /* IBM */
711 if (device_id == 0x0046 || device_id == 0xFFFF) {
712 /* MPIC & MPIC2 */
713 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
714 }
715 }
716 break;
717 case 0xff00:
718 if (vendor_id == 0x0106b &&
719 (device_id == 0x0017 || device_id == 0x0022)) {
720 /* macio bridge */
721 pci_set_io_region_addr(d, 0, 0x80800000);
722 }
723 break;
724 default:
725 default_map:
726 /* default memory mappings */
727 for(i = 0; i < PCI_NUM_REGIONS; i++) {
728 int ofs;
729 uint32_t val, size ;
730
731 if (i == PCI_ROM_SLOT)
732 ofs = 0x30;
733 else
734 ofs = 0x10 + i * 4;
735 pci_config_writel(d, ofs, 0xffffffff);
736 val = pci_config_readl(d, ofs);
737 if (val != 0) {
738 size = (~(val & ~0xf)) + 1;
739 if (val & PCI_ADDRESS_SPACE_IO)
740 paddr = &pci_bios_io_addr;
741 else if (size >= 0x04000000)
742 paddr = &pci_bios_bigmem_addr;
743 else
744 paddr = &pci_bios_mem_addr;
745 *paddr = (*paddr + size - 1) & ~(size - 1);
746 pci_set_io_region_addr(d, i, *paddr);
747 *paddr += size;
748 }
749 }
750 break;
751 }
752
753 /* map the interrupt */
754 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
755 if (pin != 0) {
756 pin = pci_slot_get_pirq(d, pin - 1);
757 pic_irq = pci_irqs[pin];
758 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
759 }
760
761 if (vendor_id == 0x8086 && device_id == 0x7113) {
762 /* PIIX4 Power Management device (for ACPI) */
763 pm_io_base = PM_IO_BASE;
764 pci_config_writel(d, 0x40, pm_io_base | 1);
765 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
766 smb_io_base = SMB_IO_BASE;
767 pci_config_writel(d, 0x90, smb_io_base | 1);
768 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
769 pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
770 #ifdef BX_USE_SMM
771 smm_init(d);
772 #endif
773 acpi_enabled = 1;
774 }
775 }
776
777 void pci_for_each_device(void (*init_func)(PCIDevice *d))
778 {
779 PCIDevice d1, *d = &d1;
780 int bus, devfn;
781 uint16_t vendor_id, device_id;
782
783 for(bus = 0; bus < 1; bus++) {
784 for(devfn = 0; devfn < 256; devfn++) {
785 d->bus = bus;
786 d->devfn = devfn;
787 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
788 device_id = pci_config_readw(d, PCI_DEVICE_ID);
789 if (vendor_id != 0xffff || device_id != 0xffff) {
790 init_func(d);
791 }
792 }
793 }
794 }
795
796 void pci_bios_init(void)
797 {
798 pci_bios_io_addr = 0xc000;
799 pci_bios_mem_addr = 0xf0000000;
800 pci_bios_bigmem_addr = ram_size;
801 if (pci_bios_bigmem_addr < 0x90000000)
802 pci_bios_bigmem_addr = 0x90000000;
803
804 pci_for_each_device(pci_bios_init_bridges);
805
806 pci_for_each_device(pci_bios_init_device);
807 }
808
809 /****************************************************/
810 /* Multi Processor table init */
811
812 static void putb(uint8_t **pp, int val)
813 {
814 uint8_t *q;
815 q = *pp;
816 *q++ = val;
817 *pp = q;
818 }
819
820 static void putstr(uint8_t **pp, const char *str)
821 {
822 uint8_t *q;
823 q = *pp;
824 while (*str)
825 *q++ = *str++;
826 *pp = q;
827 }
828
829 static void putle16(uint8_t **pp, int val)
830 {
831 uint8_t *q;
832 q = *pp;
833 *q++ = val;
834 *q++ = val >> 8;
835 *pp = q;
836 }
837
838 static void putle32(uint8_t **pp, int val)
839 {
840 uint8_t *q;
841 q = *pp;
842 *q++ = val;
843 *q++ = val >> 8;
844 *q++ = val >> 16;
845 *q++ = val >> 24;
846 *pp = q;
847 }
848
849 static int mpf_checksum(const uint8_t *data, int len)
850 {
851 int sum, i;
852 sum = 0;
853 for(i = 0; i < len; i++)
854 sum += data[i];
855 return sum & 0xff;
856 }
857
858 static unsigned long align(unsigned long addr, unsigned long v)
859 {
860 return (addr + v - 1) & ~(v - 1);
861 }
862
863 static void mptable_init(void)
864 {
865 uint8_t *mp_config_table, *q, *float_pointer_struct;
866 int ioapic_id, i, len;
867 int mp_config_table_size;
868
869 #ifdef BX_USE_EBDA_TABLES
870 mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
871 #else
872 bios_table_cur_addr = align(bios_table_cur_addr, 16);
873 mp_config_table = (uint8_t *)bios_table_cur_addr;
874 #endif
875 q = mp_config_table;
876 putstr(&q, "PCMP"); /* "PCMP signature */
877 putle16(&q, 0); /* table length (patched later) */
878 putb(&q, 4); /* spec rev */
879 putb(&q, 0); /* checksum (patched later) */
880 #ifdef BX_QEMU
881 putstr(&q, "QEMUCPU "); /* OEM id */
882 #else
883 putstr(&q, "BOCHSCPU");
884 #endif
885 putstr(&q, "0.1 "); /* vendor id */
886 putle32(&q, 0); /* OEM table ptr */
887 putle16(&q, 0); /* OEM table size */
888 putle16(&q, smp_cpus + 18); /* entry count */
889 putle32(&q, 0xfee00000); /* local APIC addr */
890 putle16(&q, 0); /* ext table length */
891 putb(&q, 0); /* ext table checksum */
892 putb(&q, 0); /* reserved */
893
894 for(i = 0; i < smp_cpus; i++) {
895 putb(&q, 0); /* entry type = processor */
896 putb(&q, i); /* APIC id */
897 putb(&q, 0x11); /* local APIC version number */
898 if (i == 0)
899 putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
900 else
901 putb(&q, 1); /* cpu flags: enabled */
902 putb(&q, 0); /* cpu signature */
903 putb(&q, 6);
904 putb(&q, 0);
905 putb(&q, 0);
906 putle16(&q, 0x201); /* feature flags */
907 putle16(&q, 0);
908
909 putle16(&q, 0); /* reserved */
910 putle16(&q, 0);
911 putle16(&q, 0);
912 putle16(&q, 0);
913 }
914
915 /* isa bus */
916 putb(&q, 1); /* entry type = bus */
917 putb(&q, 0); /* bus ID */
918 putstr(&q, "ISA ");
919
920 /* ioapic */
921 ioapic_id = smp_cpus;
922 putb(&q, 2); /* entry type = I/O APIC */
923 putb(&q, ioapic_id); /* apic ID */
924 putb(&q, 0x11); /* I/O APIC version number */
925 putb(&q, 1); /* enable */
926 putle32(&q, 0xfec00000); /* I/O APIC addr */
927
928 /* irqs */
929 for(i = 0; i < 16; i++) {
930 putb(&q, 3); /* entry type = I/O interrupt */
931 putb(&q, 0); /* interrupt type = vectored interrupt */
932 putb(&q, 0); /* flags: po=0, el=0 */
933 putb(&q, 0);
934 putb(&q, 0); /* source bus ID = ISA */
935 putb(&q, i); /* source bus IRQ */
936 putb(&q, ioapic_id); /* dest I/O APIC ID */
937 putb(&q, i); /* dest I/O APIC interrupt in */
938 }
939 /* patch length */
940 len = q - mp_config_table;
941 mp_config_table[4] = len;
942 mp_config_table[5] = len >> 8;
943
944 mp_config_table[7] = -mpf_checksum(mp_config_table, q - mp_config_table);
945
946 mp_config_table_size = q - mp_config_table;
947
948 #ifndef BX_USE_EBDA_TABLES
949 bios_table_cur_addr += mp_config_table_size;
950 #endif
951
952 /* floating pointer structure */
953 #ifdef BX_USE_EBDA_TABLES
954 ebda_cur_addr = align(ebda_cur_addr, 16);
955 float_pointer_struct = (uint8_t *)ebda_cur_addr;
956 #else
957 bios_table_cur_addr = align(bios_table_cur_addr, 16);
958 float_pointer_struct = (uint8_t *)bios_table_cur_addr;
959 #endif
960 q = float_pointer_struct;
961 putstr(&q, "_MP_");
962 /* pointer to MP config table */
963 putle32(&q, (unsigned long)mp_config_table);
964
965 putb(&q, 1); /* length in 16 byte units */
966 putb(&q, 4); /* MP spec revision */
967 putb(&q, 0); /* checksum (patched later) */
968 putb(&q, 0); /* MP feature byte 1 */
969
970 putb(&q, 0);
971 putb(&q, 0);
972 putb(&q, 0);
973 putb(&q, 0);
974 float_pointer_struct[10] =
975 -mpf_checksum(float_pointer_struct, q - float_pointer_struct);
976 #ifdef BX_USE_EBDA_TABLES
977 ebda_cur_addr += (q - float_pointer_struct);
978 #else
979 bios_table_cur_addr += (q - float_pointer_struct);
980 #endif
981 BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
982 (unsigned long)float_pointer_struct,
983 (unsigned long)mp_config_table,
984 mp_config_table_size);
985 }
986
987 /****************************************************/
988 /* ACPI tables init */
989
990 /* Table structure from Linux kernel (the ACPI tables are under the
991 BSD license) */
992
993 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
994 uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
995 uint32_t length; /* Length of table, in bytes, including header */\
996 uint8_t revision; /* ACPI Specification minor version # */\
997 uint8_t checksum; /* To make sum of entire table == 0 */\
998 uint8_t oem_id [6]; /* OEM identification */\
999 uint8_t oem_table_id [8]; /* OEM table identification */\
1000 uint32_t oem_revision; /* OEM revision number */\
1001 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
1002 uint32_t asl_compiler_revision; /* ASL compiler revision number */
1003
1004
1005 struct acpi_table_header /* ACPI common table header */
1006 {
1007 ACPI_TABLE_HEADER_DEF
1008 };
1009
1010 struct rsdp_descriptor /* Root System Descriptor Pointer */
1011 {
1012 uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */
1013 uint8_t checksum; /* To make sum of struct == 0 */
1014 uint8_t oem_id [6]; /* OEM identification */
1015 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
1016 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
1017 uint32_t length; /* XSDT Length in bytes including hdr */
1018 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
1019 uint8_t extended_checksum; /* Checksum of entire table */
1020 uint8_t reserved [3]; /* Reserved field must be 0 */
1021 };
1022
1023 /*
1024 * ACPI 1.0 Root System Description Table (RSDT)
1025 */
1026 struct rsdt_descriptor_rev1
1027 {
1028 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1029 uint32_t table_offset_entry [2]; /* Array of pointers to other */
1030 /* ACPI tables */
1031 };
1032
1033 /*
1034 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
1035 */
1036 struct facs_descriptor_rev1
1037 {
1038 uint8_t signature[4]; /* ACPI Signature */
1039 uint32_t length; /* Length of structure, in bytes */
1040 uint32_t hardware_signature; /* Hardware configuration signature */
1041 uint32_t firmware_waking_vector; /* ACPI OS waking vector */
1042 uint32_t global_lock; /* Global Lock */
1043 uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */
1044 uint32_t reserved1 : 31; /* Must be 0 */
1045 uint8_t resverved3 [40]; /* Reserved - must be zero */
1046 };
1047
1048
1049 /*
1050 * ACPI 1.0 Fixed ACPI Description Table (FADT)
1051 */
1052 struct fadt_descriptor_rev1
1053 {
1054 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1055 uint32_t firmware_ctrl; /* Physical address of FACS */
1056 uint32_t dsdt; /* Physical address of DSDT */
1057 uint8_t model; /* System Interrupt Model */
1058 uint8_t reserved1; /* Reserved */
1059 uint16_t sci_int; /* System vector of SCI interrupt */
1060 uint32_t smi_cmd; /* Port address of SMI command port */
1061 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
1062 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
1063 uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
1064 uint8_t reserved2; /* Reserved - must be zero */
1065 uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
1066 uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
1067 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
1068 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
1069 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
1070 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
1071 uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
1072 uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
1073 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
1074 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
1075 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
1076 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
1077 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
1078 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
1079 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
1080 uint8_t reserved3; /* Reserved */
1081 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
1082 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
1083 uint16_t flush_size; /* Size of area read to flush caches */
1084 uint16_t flush_stride; /* Stride used in flushing caches */
1085 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
1086 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
1087 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
1088 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
1089 uint8_t century; /* Index to century in RTC CMOS RAM */
1090 uint8_t reserved4; /* Reserved */
1091 uint8_t reserved4a; /* Reserved */
1092 uint8_t reserved4b; /* Reserved */
1093 #if 0
1094 uint32_t wb_invd : 1; /* The wbinvd instruction works properly */
1095 uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
1096 uint32_t proc_c1 : 1; /* All processors support C1 state */
1097 uint32_t plvl2_up : 1; /* C2 state works on MP system */
1098 uint32_t pwr_button : 1; /* Power button is handled as a generic feature */
1099 uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
1100 uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
1101 uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
1102 uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
1103 uint32_t reserved5 : 23; /* Reserved - must be zero */
1104 #else
1105 uint32_t flags;
1106 #endif
1107 };
1108
1109 /*
1110 * MADT values and structures
1111 */
1112
1113 /* Values for MADT PCATCompat */
1114
1115 #define DUAL_PIC 0
1116 #define MULTIPLE_APIC 1
1117
1118
1119 /* Master MADT */
1120
1121 struct multiple_apic_table
1122 {
1123 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1124 uint32_t local_apic_address; /* Physical address of local APIC */
1125 #if 0
1126 uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */
1127 uint32_t reserved1 : 31;
1128 #else
1129 uint32_t flags;
1130 #endif
1131 };
1132
1133
1134 /* Values for Type in APIC_HEADER_DEF */
1135
1136 #define APIC_PROCESSOR 0
1137 #define APIC_IO 1
1138 #define APIC_XRUPT_OVERRIDE 2
1139 #define APIC_NMI 3
1140 #define APIC_LOCAL_NMI 4
1141 #define APIC_ADDRESS_OVERRIDE 5
1142 #define APIC_IO_SAPIC 6
1143 #define APIC_LOCAL_SAPIC 7
1144 #define APIC_XRUPT_SOURCE 8
1145 #define APIC_RESERVED 9 /* 9 and greater are reserved */
1146
1147 /*
1148 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
1149 */
1150 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
1151 uint8_t type; \
1152 uint8_t length;
1153
1154 /* Sub-structures for MADT */
1155
1156 struct madt_processor_apic
1157 {
1158 APIC_HEADER_DEF
1159 uint8_t processor_id; /* ACPI processor id */
1160 uint8_t local_apic_id; /* Processor's local APIC id */
1161 #if 0
1162 uint32_t processor_enabled: 1; /* Processor is usable if set */
1163 uint32_t reserved2 : 31; /* Reserved, must be zero */
1164 #else
1165 uint32_t flags;
1166 #endif
1167 };
1168
1169 struct madt_io_apic
1170 {
1171 APIC_HEADER_DEF
1172 uint8_t io_apic_id; /* I/O APIC ID */
1173 uint8_t reserved; /* Reserved - must be zero */
1174 uint32_t address; /* APIC physical address */
1175 uint32_t interrupt; /* Global system interrupt where INTI
1176 * lines start */
1177 };
1178
1179 #include "acpi-dsdt.hex"
1180
1181 static inline uint16_t cpu_to_le16(uint16_t x)
1182 {
1183 return x;
1184 }
1185
1186 static inline uint32_t cpu_to_le32(uint32_t x)
1187 {
1188 return x;
1189 }
1190
1191 static int acpi_checksum(const uint8_t *data, int len)
1192 {
1193 int sum, i;
1194 sum = 0;
1195 for(i = 0; i < len; i++)
1196 sum += data[i];
1197 return (-sum) & 0xff;
1198 }
1199
1200 static void acpi_build_table_header(struct acpi_table_header *h,
1201 char *sig, int len, uint8_t rev)
1202 {
1203 memcpy(h->signature, sig, 4);
1204 h->length = cpu_to_le32(len);
1205 h->revision = rev;
1206 #ifdef BX_QEMU
1207 memcpy(h->oem_id, "QEMU ", 6);
1208 memcpy(h->oem_table_id, "QEMU", 4);
1209 #else
1210 memcpy(h->oem_id, "BOCHS ", 6);
1211 memcpy(h->oem_table_id, "BXPC", 4);
1212 #endif
1213 memcpy(h->oem_table_id + 4, sig, 4);
1214 h->oem_revision = cpu_to_le32(1);
1215 #ifdef BX_QEMU
1216 memcpy(h->asl_compiler_id, "QEMU", 4);
1217 #else
1218 memcpy(h->asl_compiler_id, "BXPC", 4);
1219 #endif
1220 h->asl_compiler_revision = cpu_to_le32(1);
1221 h->checksum = acpi_checksum((void *)h, len);
1222 }
1223
1224 /* base_addr must be a multiple of 4KB */
1225 void acpi_bios_init(void)
1226 {
1227 struct rsdp_descriptor *rsdp;
1228 struct rsdt_descriptor_rev1 *rsdt;
1229 struct fadt_descriptor_rev1 *fadt;
1230 struct facs_descriptor_rev1 *facs;
1231 struct multiple_apic_table *madt;
1232 uint8_t *dsdt;
1233 uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr;
1234 uint32_t acpi_tables_size, madt_addr, madt_size;
1235 int i;
1236
1237 /* reserve memory space for tables */
1238 #ifdef BX_USE_EBDA_TABLES
1239 ebda_cur_addr = align(ebda_cur_addr, 16);
1240 rsdp = (void *)(ebda_cur_addr);
1241 ebda_cur_addr += sizeof(*rsdp);
1242 #else
1243 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1244 rsdp = (void *)(bios_table_cur_addr);
1245 bios_table_cur_addr += sizeof(*rsdp);
1246 #endif
1247
1248 addr = base_addr = ram_size - ACPI_DATA_SIZE;
1249 rsdt_addr = addr;
1250 rsdt = (void *)(addr);
1251 addr += sizeof(*rsdt);
1252
1253 fadt_addr = addr;
1254 fadt = (void *)(addr);
1255 addr += sizeof(*fadt);
1256
1257 /* XXX: FACS should be in RAM */
1258 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
1259 facs_addr = addr;
1260 facs = (void *)(addr);
1261 addr += sizeof(*facs);
1262
1263 dsdt_addr = addr;
1264 dsdt = (void *)(addr);
1265 addr += sizeof(AmlCode);
1266
1267 addr = (addr + 7) & ~7;
1268 madt_addr = addr;
1269 madt_size = sizeof(*madt) +
1270 sizeof(struct madt_processor_apic) * smp_cpus +
1271 sizeof(struct madt_io_apic);
1272 madt = (void *)(addr);
1273 addr += madt_size;
1274
1275 acpi_tables_size = addr - base_addr;
1276
1277 BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
1278 (unsigned long)rsdp,
1279 (unsigned long)rsdt, acpi_tables_size);
1280
1281 /* RSDP */
1282 memset(rsdp, 0, sizeof(*rsdp));
1283 memcpy(rsdp->signature, "RSD PTR ", 8);
1284 #ifdef BX_QEMU
1285 memcpy(rsdp->oem_id, "QEMU ", 6);
1286 #else
1287 memcpy(rsdp->oem_id, "BOCHS ", 6);
1288 #endif
1289 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
1290 rsdp->checksum = acpi_checksum((void *)rsdp, 20);
1291
1292 /* RSDT */
1293 memset(rsdt, 0, sizeof(*rsdt));
1294 rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
1295 rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
1296 acpi_build_table_header((struct acpi_table_header *)rsdt,
1297 "RSDT", sizeof(*rsdt), 1);
1298
1299 /* FADT */
1300 memset(fadt, 0, sizeof(*fadt));
1301 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
1302 fadt->dsdt = cpu_to_le32(dsdt_addr);
1303 fadt->model = 1;
1304 fadt->reserved1 = 0;
1305 fadt->sci_int = cpu_to_le16(pm_sci_int);
1306 fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
1307 fadt->acpi_enable = 0xf1;
1308 fadt->acpi_disable = 0xf0;
1309 fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
1310 fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
1311 fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
1312 fadt->pm1_evt_len = 4;
1313 fadt->pm1_cnt_len = 2;
1314 fadt->pm_tmr_len = 4;
1315 fadt->plvl2_lat = cpu_to_le16(50);
1316 fadt->plvl3_lat = cpu_to_le16(50);
1317 fadt->plvl3_lat = cpu_to_le16(50);
1318 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
1319 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
1320 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
1321 sizeof(*fadt), 1);
1322
1323 /* FACS */
1324 memset(facs, 0, sizeof(*facs));
1325 memcpy(facs->signature, "FACS", 4);
1326 facs->length = cpu_to_le32(sizeof(*facs));
1327
1328 /* DSDT */
1329 memcpy(dsdt, AmlCode, sizeof(AmlCode));
1330
1331 /* MADT */
1332 {
1333 struct madt_processor_apic *apic;
1334 struct madt_io_apic *io_apic;
1335
1336 memset(madt, 0, madt_size);
1337 madt->local_apic_address = cpu_to_le32(0xfee00000);
1338 madt->flags = cpu_to_le32(1);
1339 apic = (void *)(madt + 1);
1340 for(i=0;i<smp_cpus;i++) {
1341 apic->type = APIC_PROCESSOR;
1342 apic->length = sizeof(*apic);
1343 apic->processor_id = i;
1344 apic->local_apic_id = i;
1345 apic->flags = cpu_to_le32(1);
1346 apic++;
1347 }
1348 io_apic = (void *)apic;
1349 io_apic->type = APIC_IO;
1350 io_apic->length = sizeof(*io_apic);
1351 io_apic->io_apic_id = smp_cpus;
1352 io_apic->address = cpu_to_le32(0xfec00000);
1353 io_apic->interrupt = cpu_to_le32(0);
1354
1355 acpi_build_table_header((struct acpi_table_header *)madt,
1356 "APIC", madt_size, 1);
1357 }
1358 }
1359
1360 void rombios32_init(void)
1361 {
1362 BX_INFO("Starting rombios32\n");
1363
1364 ram_probe();
1365
1366 cpu_probe();
1367
1368 smp_probe();
1369
1370 pci_bios_init();
1371
1372 if (bios_table_cur_addr != 0) {
1373
1374 mptable_init();
1375
1376 if (acpi_enabled)
1377 acpi_bios_init();
1378
1379 bios_lock_shadow_ram();
1380 }
1381 }
GPL Bios