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- implemented INT 15h/89h (patch by Sebastian Herbszt)
[gplbios.git] / rombios32.c
blob269f17523666126d12c24f2d8179ea89b2c9785f
1 /////////////////////////////////////////////////////////////////////////
2 // $Id$
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // 32 bit Bochs BIOS init code
6 // Copyright (C) 2006 Fabrice Bellard
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <stdarg.h>
22 #include <stddef.h>
23
24 #include "rombios.h"
25
26 typedef signed char int8_t;
27 typedef short int16_t;
28 typedef int int32_t;
29 typedef long long int64_t;
30 typedef unsigned char uint8_t;
31 typedef unsigned short uint16_t;
32 typedef unsigned int uint32_t;
33 typedef unsigned long long uint64_t;
34
35 /* if true, put the MP float table and ACPI RSDT in EBDA and the MP
36 table in RAM. Unfortunately, Linux has bugs with that, so we prefer
37 to modify the BIOS in shadow RAM */
38 //#define BX_USE_EBDA_TABLES
39
40 /* define it if the (emulated) hardware supports SMM mode */
41 #define BX_USE_SMM
42
43 #define cpuid(index, eax, ebx, ecx, edx) \
44 asm volatile ("cpuid" \
45 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
46 : "0" (index))
47
48 #define wbinvd() asm volatile("wbinvd")
49
50 #define CPUID_MSR (1 << 5)
51 #define CPUID_APIC (1 << 9)
52 #define CPUID_MTRR (1 << 12)
53
54 #define APIC_BASE ((uint8_t *)0xfee00000)
55 #define APIC_ICR_LOW 0x300
56 #define APIC_SVR 0x0F0
57 #define APIC_ID 0x020
58 #define APIC_LVT3 0x370
59
60 #define APIC_ENABLED 0x0100
61
62 #define AP_BOOT_ADDR 0x9f000
63
64 #define MPTABLE_MAX_SIZE 0x00002000
65 #define SMI_CMD_IO_ADDR 0xb2
66
67 #define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
68
69 #define MSR_MTRRcap 0x000000fe
70 #define MSR_MTRRfix64K_00000 0x00000250
71 #define MSR_MTRRfix16K_80000 0x00000258
72 #define MSR_MTRRfix16K_A0000 0x00000259
73 #define MSR_MTRRfix4K_C0000 0x00000268
74 #define MSR_MTRRfix4K_C8000 0x00000269
75 #define MSR_MTRRfix4K_D0000 0x0000026a
76 #define MSR_MTRRfix4K_D8000 0x0000026b
77 #define MSR_MTRRfix4K_E0000 0x0000026c
78 #define MSR_MTRRfix4K_E8000 0x0000026d
79 #define MSR_MTRRfix4K_F0000 0x0000026e
80 #define MSR_MTRRfix4K_F8000 0x0000026f
81 #define MSR_MTRRdefType 0x000002ff
82
83 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
84 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
85
86 static inline void outl(int addr, int val)
87 {
88 asm volatile ("outl %1, %w0" : : "d" (addr), "a" (val));
89 }
90
91 static inline void outw(int addr, int val)
92 {
93 asm volatile ("outw %w1, %w0" : : "d" (addr), "a" (val));
94 }
95
96 static inline void outb(int addr, int val)
97 {
98 asm volatile ("outb %b1, %w0" : : "d" (addr), "a" (val));
99 }
100
101 static inline uint32_t inl(int addr)
102 {
103 uint32_t val;
104 asm volatile ("inl %w1, %0" : "=a" (val) : "d" (addr));
105 return val;
106 }
107
108 static inline uint16_t inw(int addr)
109 {
110 uint16_t val;
111 asm volatile ("inw %w1, %w0" : "=a" (val) : "d" (addr));
112 return val;
113 }
114
115 static inline uint8_t inb(int addr)
116 {
117 uint8_t val;
118 asm volatile ("inb %w1, %b0" : "=a" (val) : "d" (addr));
119 return val;
120 }
121
122 static inline void writel(void *addr, uint32_t val)
123 {
124 *(volatile uint32_t *)addr = val;
125 }
126
127 static inline void writew(void *addr, uint16_t val)
128 {
129 *(volatile uint16_t *)addr = val;
130 }
131
132 static inline void writeb(void *addr, uint8_t val)
133 {
134 *(volatile uint8_t *)addr = val;
135 }
136
137 static inline uint32_t readl(const void *addr)
138 {
139 return *(volatile const uint32_t *)addr;
140 }
141
142 static inline uint16_t readw(const void *addr)
143 {
144 return *(volatile const uint16_t *)addr;
145 }
146
147 static inline uint8_t readb(const void *addr)
148 {
149 return *(volatile const uint8_t *)addr;
150 }
151
152 static inline void putch(int c)
153 {
154 outb(INFO_PORT, c);
155 }
156
157 static uint64_t rdmsr(unsigned index)
158 {
159 unsigned long long ret;
160
161 asm ("rdmsr" : "=A"(ret) : "c"(index));
162 return ret;
163 }
164
165 static void wrmsr(unsigned index, uint64_t val)
166 {
167 asm volatile ("wrmsr" : : "c"(index), "A"(val));
168 }
169
170 static inline int isdigit(int c)
171 {
172 return c >= '0' && c <= '9';
173 }
174
175 void *memset(void *d1, int val, size_t len)
176 {
177 uint8_t *d = d1;
178
179 while (len--) {
180 *d++ = val;
181 }
182 return d1;
183 }
184
185 void *memcpy(void *d1, const void *s1, size_t len)
186 {
187 uint8_t *d = d1;
188 const uint8_t *s = s1;
189
190 while (len--) {
191 *d++ = *s++;
192 }
193 return d1;
194 }
195
196 void *memmove(void *d1, const void *s1, size_t len)
197 {
198 uint8_t *d = d1;
199 const uint8_t *s = s1;
200
201 if (d <= s) {
202 while (len--) {
203 *d++ = *s++;
204 }
205 } else {
206 d += len;
207 s += len;
208 while (len--) {
209 *--d = *--s;
210 }
211 }
212 return d1;
213 }
214
215 int memcmp(const void *s1, const void *s2, size_t len)
216 {
217 const int8_t *p1 = s1;
218 const int8_t *p2 = s2;
219
220 while (len--) {
221 int r = *p1++ - *p2++;
222 if(r)
223 return r;
224 }
225
226 return 0;
227 }
228
229 size_t strlen(const char *s)
230 {
231 const char *s1;
232 for(s1 = s; *s1 != '\0'; s1++);
233 return s1 - s;
234 }
235
236 /* from BSD ppp sources */
237 int vsnprintf(char *buf, int buflen, const char *fmt, va_list args)
238 {
239 int c, i, n;
240 int width, prec, fillch;
241 int base, len, neg;
242 unsigned long val = 0;
243 const char *f;
244 char *str, *buf0;
245 char num[32];
246 static const char hexchars[] = "0123456789abcdef";
247
248 buf0 = buf;
249 --buflen;
250 while (buflen > 0) {
251 for (f = fmt; *f != '%' && *f != 0; ++f)
252 ;
253 if (f > fmt) {
254 len = f - fmt;
255 if (len > buflen)
256 len = buflen;
257 memcpy(buf, fmt, len);
258 buf += len;
259 buflen -= len;
260 fmt = f;
261 }
262 if (*fmt == 0)
263 break;
264 c = *++fmt;
265 width = prec = 0;
266 fillch = ' ';
267 if (c == '0') {
268 fillch = '0';
269 c = *++fmt;
270 }
271 if (c == '*') {
272 width = va_arg(args, int);
273 c = *++fmt;
274 } else {
275 while (isdigit(c)) {
276 width = width * 10 + c - '0';
277 c = *++fmt;
278 }
279 }
280 if (c == '.') {
281 c = *++fmt;
282 if (c == '*') {
283 prec = va_arg(args, int);
284 c = *++fmt;
285 } else {
286 while (isdigit(c)) {
287 prec = prec * 10 + c - '0';
288 c = *++fmt;
289 }
290 }
291 }
292 /* modifiers */
293 switch(c) {
294 case 'l':
295 c = *++fmt;
296 break;
297 default:
298 break;
299 }
300 str = 0;
301 base = 0;
302 neg = 0;
303 ++fmt;
304 switch (c) {
305 case 'd':
306 i = va_arg(args, int);
307 if (i < 0) {
308 neg = 1;
309 val = -i;
310 } else
311 val = i;
312 base = 10;
313 break;
314 case 'o':
315 val = va_arg(args, unsigned int);
316 base = 8;
317 break;
318 case 'x':
319 case 'X':
320 val = va_arg(args, unsigned int);
321 base = 16;
322 break;
323 case 'p':
324 val = (unsigned long) va_arg(args, void *);
325 base = 16;
326 neg = 2;
327 break;
328 case 's':
329 str = va_arg(args, char *);
330 break;
331 case 'c':
332 num[0] = va_arg(args, int);
333 num[1] = 0;
334 str = num;
335 break;
336 default:
337 *buf++ = '%';
338 if (c != '%')
339 --fmt; /* so %z outputs %z etc. */
340 --buflen;
341 continue;
342 }
343 if (base != 0) {
344 str = num + sizeof(num);
345 *--str = 0;
346 while (str > num + neg) {
347 *--str = hexchars[val % base];
348 val = val / base;
349 if (--prec <= 0 && val == 0)
350 break;
351 }
352 switch (neg) {
353 case 1:
354 *--str = '-';
355 break;
356 case 2:
357 *--str = 'x';
358 *--str = '0';
359 break;
360 }
361 len = num + sizeof(num) - 1 - str;
362 } else {
363 len = strlen(str);
364 if (prec > 0 && len > prec)
365 len = prec;
366 }
367 if (width > 0) {
368 if (width > buflen)
369 width = buflen;
370 if ((n = width - len) > 0) {
371 buflen -= n;
372 for (; n > 0; --n)
373 *buf++ = fillch;
374 }
375 }
376 if (len > buflen)
377 len = buflen;
378 memcpy(buf, str, len);
379 buf += len;
380 buflen -= len;
381 }
382 *buf = 0;
383 return buf - buf0;
384 }
385
386 int snprintf(char * buf, size_t size, const char *fmt, ...)
387 {
388 va_list args;
389 int i;
390
391 va_start(args, fmt);
392 i = vsnprintf(buf, size, fmt, args);
393 va_end(args);
394 return i;
395 }
396
397 void bios_printf(int flags, const char *fmt, ...)
398 {
399 va_list ap;
400 char buf[1024];
401 const char *s;
402
403 if ((flags & BIOS_PRINTF_DEBHALT) == BIOS_PRINTF_DEBHALT)
404 outb(PANIC_PORT2, 0x00);
405
406 va_start(ap, fmt);
407 vsnprintf(buf, sizeof(buf), fmt, ap);
408 s = buf;
409 while (*s)
410 putch(*s++);
411 va_end(ap);
412 }
413
414 void delay_ms(int n)
415 {
416 int i, j;
417 for(i = 0; i < n; i++) {
418 #ifdef BX_QEMU
419 volatile int k;
420 /* approximative ! */
421 for(j = 0; j < 1000000; j++) {
422 k++;
423 }
424 #else
425 {
426 int r1, r2;
427 j = 66;
428 r1 = inb(0x61) & 0x10;
429 do {
430 r2 = inb(0x61) & 0x10;
431 if (r1 != r2) {
432 j--;
433 r1 = r2;
434 }
435 } while (j > 0);
436 }
437 #endif
438 }
439 }
440
441 uint16_t smp_cpus;
442 uint32_t cpuid_signature;
443 uint32_t cpuid_features;
444 uint32_t cpuid_ext_features;
445 unsigned long ram_size;
446 uint64_t ram_end;
447 uint8_t bios_uuid[16];
448 #ifdef BX_USE_EBDA_TABLES
449 unsigned long ebda_cur_addr;
450 #endif
451 int acpi_enabled;
452 uint32_t pm_io_base, smb_io_base;
453 int pm_sci_int;
454 unsigned long bios_table_cur_addr;
455 unsigned long bios_table_end_addr;
456
457 void wrmsr_smp(uint32_t index, uint64_t val)
458 {
459 static struct { uint32_t ecx, eax, edx; } *p = (void *)SMP_MSR_ADDR;
460
461 wrmsr(index, val);
462 p->ecx = index;
463 p->eax = val;
464 p->edx = val >> 32;
465 ++p;
466 p->ecx = 0;
467 }
468
469 #ifdef BX_QEMU
470 #define QEMU_CFG_CTL_PORT 0x510
471 #define QEMU_CFG_DATA_PORT 0x511
472 #define QEMU_CFG_SIGNATURE 0x00
473 #define QEMU_CFG_ID 0x01
474 #define QEMU_CFG_UUID 0x02
475
476 int qemu_cfg_port;
477
478 void qemu_cfg_select(int f)
479 {
480 outw(QEMU_CFG_CTL_PORT, f);
481 }
482
483 int qemu_cfg_port_probe()
484 {
485 char *sig = "QEMU";
486 int i;
487
488 qemu_cfg_select(QEMU_CFG_SIGNATURE);
489
490 for (i = 0; i < 4; i++)
491 if (inb(QEMU_CFG_DATA_PORT) != sig[i])
492 return 0;
493
494 return 1;
495 }
496
497 void qemu_cfg_read(uint8_t *buf, int len)
498 {
499 while (len--)
500 *(buf++) = inb(QEMU_CFG_DATA_PORT);
501 }
502 #endif
503
504 void uuid_probe(void)
505 {
506 #ifdef BX_QEMU
507 if(qemu_cfg_port) {
508 qemu_cfg_select(QEMU_CFG_UUID);
509 qemu_cfg_read(bios_uuid, 16);
510 return;
511 }
512 #endif
513 memset(bios_uuid, 0, 16);
514 }
515
516 void cpu_probe(void)
517 {
518 uint32_t eax, ebx, ecx, edx;
519 cpuid(1, eax, ebx, ecx, edx);
520 cpuid_signature = eax;
521 cpuid_features = edx;
522 cpuid_ext_features = ecx;
523 }
524
525 static int cmos_readb(int addr)
526 {
527 outb(0x70, addr);
528 return inb(0x71);
529 }
530
531 void setup_mtrr(void)
532 {
533 int i, vcnt, fix, wc;
534 uint32_t mtrr_cap;
535 union {
536 uint8_t valb[8];
537 uint64_t val;
538 } u;
539
540 *(uint32_t *)SMP_MSR_ADDR = 0;
541
542 if (!(cpuid_features & CPUID_MTRR))
543 return;
544
545 if (!(cpuid_features & CPUID_MSR))
546 return;
547
548 mtrr_cap = rdmsr(MSR_MTRRcap);
549 vcnt = mtrr_cap & 0xff;
550 fix = mtrr_cap & 0x100;
551 wc = mtrr_cap & 0x400;
552 if (!vcnt || !fix)
553 return;
554
555 u.val = 0;
556 for (i = 0; i < 8; ++i)
557 if (ram_size >= 65536 * (i + 1))
558 u.valb[i] = 6;
559 wrmsr_smp(MSR_MTRRfix64K_00000, u.val);
560 u.val = 0;
561 for (i = 0; i < 8; ++i)
562 if (ram_size >= 65536 * 8 + 16384 * (i + 1))
563 u.valb[i] = 6;
564 wrmsr_smp(MSR_MTRRfix16K_80000, u.val);
565 wrmsr_smp(MSR_MTRRfix16K_A0000, 0);
566 wrmsr_smp(MSR_MTRRfix4K_C0000, 0);
567 wrmsr_smp(MSR_MTRRfix4K_C8000, 0);
568 wrmsr_smp(MSR_MTRRfix4K_D0000, 0);
569 wrmsr_smp(MSR_MTRRfix4K_D8000, 0);
570 wrmsr_smp(MSR_MTRRfix4K_E0000, 0);
571 wrmsr_smp(MSR_MTRRfix4K_E8000, 0);
572 wrmsr_smp(MSR_MTRRfix4K_F0000, 0);
573 wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
574 /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
575 wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
576 wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
577 wrmsr_smp(MSR_MTRRdefType, 0xc06);
578 }
579
580 void ram_probe(void)
581 {
582 if (cmos_readb(0x34) | cmos_readb(0x35))
583 ram_size = (cmos_readb(0x34) | (cmos_readb(0x35) << 8)) * 65536 +
584 16 * 1024 * 1024;
585 else
586 ram_size = (cmos_readb(0x30) | (cmos_readb(0x31) << 8)) * 1024 +
587 1 * 1024 * 1024;
588 BX_INFO("ram_size=0x%08lx\n", ram_size);
589
590 if (cmos_readb(0x5b) | cmos_readb(0x5c) | cmos_readb(0x5d))
591 ram_end = (((uint64_t)cmos_readb(0x5b) << 16) |
592 ((uint64_t)cmos_readb(0x5c) << 24) |
593 ((uint64_t)cmos_readb(0x5d) << 32)) + (1ull << 32);
594 else
595 ram_end = ram_size;
596 BX_INFO("ram_end=%ldMB\n", ram_end >> 20);
597 #ifdef BX_USE_EBDA_TABLES
598 ebda_cur_addr = ((*(uint16_t *)(0x40e)) << 4) + 0x380;
599 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
600 #endif
601 }
602
603 /****************************************************/
604 /* SMP probe */
605
606 extern uint8_t smp_ap_boot_code_start;
607 extern uint8_t smp_ap_boot_code_end;
608
609 /* find the number of CPUs by launching a SIPI to them */
610 void smp_probe(void)
611 {
612 uint32_t val, sipi_vector;
613
614 writew(&smp_cpus, 1);
615 if (cpuid_features & CPUID_APIC) {
616
617 /* enable local APIC */
618 val = readl(APIC_BASE + APIC_SVR);
619 val |= APIC_ENABLED;
620 writel(APIC_BASE + APIC_SVR, val);
621
622 /* copy AP boot code */
623 memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
624 &smp_ap_boot_code_end - &smp_ap_boot_code_start);
625
626 /* broadcast SIPI */
627 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
628 sipi_vector = AP_BOOT_ADDR >> 12;
629 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
630
631 #ifndef BX_QEMU
632 delay_ms(10);
633 #else
634 while (cmos_readb(0x5f) + 1 != readw(&smp_cpus))
635 ;
636 #endif
637 }
638 BX_INFO("Found %d cpu(s)\n", readw(&smp_cpus));
639 }
640
641 /****************************************************/
642 /* PCI init */
643
644 #define PCI_ADDRESS_SPACE_MEM 0x00
645 #define PCI_ADDRESS_SPACE_IO 0x01
646 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
647
648 #define PCI_ROM_SLOT 6
649 #define PCI_NUM_REGIONS 7
650
651 #define PCI_DEVICES_MAX 64
652
653 #define PCI_VENDOR_ID 0x00 /* 16 bits */
654 #define PCI_DEVICE_ID 0x02 /* 16 bits */
655 #define PCI_COMMAND 0x04 /* 16 bits */
656 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
657 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
658 #define PCI_CLASS_DEVICE 0x0a /* Device class */
659 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
660 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
661 #define PCI_MIN_GNT 0x3e /* 8 bits */
662 #define PCI_MAX_LAT 0x3f /* 8 bits */
663
664 #define PCI_VENDOR_ID_INTEL 0x8086
665 #define PCI_DEVICE_ID_INTEL_82441 0x1237
666 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
667 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
668 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
669 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
670 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
671
672 #define PCI_VENDOR_ID_IBM 0x1014
673 #define PCI_VENDOR_ID_APPLE 0x106b
674
675 typedef struct PCIDevice {
676 int bus;
677 int devfn;
678 } PCIDevice;
679
680 static uint32_t pci_bios_io_addr;
681 static uint32_t pci_bios_mem_addr;
682 static uint32_t pci_bios_bigmem_addr;
683 /* host irqs corresponding to PCI irqs A-D */
684 static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
685 static PCIDevice i440_pcidev;
686
687 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
688 {
689 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
690 outl(0xcfc, val);
691 }
692
693 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
694 {
695 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
696 outw(0xcfc + (addr & 2), val);
697 }
698
699 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
700 {
701 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
702 outb(0xcfc + (addr & 3), val);
703 }
704
705 static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
706 {
707 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
708 return inl(0xcfc);
709 }
710
711 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
712 {
713 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
714 return inw(0xcfc + (addr & 2));
715 }
716
717 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
718 {
719 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
720 return inb(0xcfc + (addr & 3));
721 }
722
723 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
724 {
725 uint16_t cmd;
726 uint32_t ofs, old_addr;
727
728 if ( region_num == PCI_ROM_SLOT ) {
729 ofs = 0x30;
730 }else{
731 ofs = 0x10 + region_num * 4;
732 }
733
734 old_addr = pci_config_readl(d, ofs);
735
736 pci_config_writel(d, ofs, addr);
737 BX_INFO("region %d: 0x%08x\n", region_num, addr);
738
739 /* enable memory mappings */
740 cmd = pci_config_readw(d, PCI_COMMAND);
741 if ( region_num == PCI_ROM_SLOT )
742 cmd |= 2;
743 else if (old_addr & PCI_ADDRESS_SPACE_IO)
744 cmd |= 1;
745 else
746 cmd |= 2;
747 pci_config_writew(d, PCI_COMMAND, cmd);
748 }
749
750 /* return the global irq number corresponding to a given device irq
751 pin. We could also use the bus number to have a more precise
752 mapping. */
753 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
754 {
755 int slot_addend;
756 slot_addend = (pci_dev->devfn >> 3) - 1;
757 return (irq_num + slot_addend) & 3;
758 }
759
760 static void find_bios_table_area(void)
761 {
762 unsigned long addr;
763 for(addr = 0xf0000; addr < 0x100000; addr += 16) {
764 if (*(uint32_t *)addr == 0xaafb4442) {
765 bios_table_cur_addr = addr + 8;
766 bios_table_end_addr = bios_table_cur_addr + *(uint32_t *)(addr + 4);
767 BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
768 bios_table_cur_addr, bios_table_end_addr);
769 return;
770 }
771 }
772 return;
773 }
774
775 static void bios_shadow_init(PCIDevice *d)
776 {
777 int v;
778
779 if (bios_table_cur_addr == 0)
780 return;
781
782 /* remap the BIOS to shadow RAM an keep it read/write while we
783 are writing tables */
784 v = pci_config_readb(d, 0x59);
785 v &= 0xcf;
786 pci_config_writeb(d, 0x59, v);
787 memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
788 v |= 0x30;
789 pci_config_writeb(d, 0x59, v);
790 memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
791
792 i440_pcidev = *d;
793 }
794
795 static void bios_lock_shadow_ram(void)
796 {
797 PCIDevice *d = &i440_pcidev;
798 int v;
799
800 wbinvd();
801 v = pci_config_readb(d, 0x59);
802 v = (v & 0x0f) | (0x10);
803 pci_config_writeb(d, 0x59, v);
804 }
805
806 static void pci_bios_init_bridges(PCIDevice *d)
807 {
808 uint16_t vendor_id, device_id;
809
810 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
811 device_id = pci_config_readw(d, PCI_DEVICE_ID);
812
813 if (vendor_id == PCI_VENDOR_ID_INTEL &&
814 (device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
815 device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
816 int i, irq;
817 uint8_t elcr[2];
818
819 /* PIIX3/PIIX4 PCI to ISA bridge */
820
821 elcr[0] = 0x00;
822 elcr[1] = 0x00;
823 for(i = 0; i < 4; i++) {
824 irq = pci_irqs[i];
825 /* set to trigger level */
826 elcr[irq >> 3] |= (1 << (irq & 7));
827 /* activate irq remapping in PIIX */
828 pci_config_writeb(d, 0x60 + i, irq);
829 }
830 outb(0x4d0, elcr[0]);
831 outb(0x4d1, elcr[1]);
832 BX_INFO("PIIX3/PIIX4 init: elcr=%02x %02x\n",
833 elcr[0], elcr[1]);
834 } else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
835 /* i440 PCI bridge */
836 bios_shadow_init(d);
837 }
838 }
839
840 extern uint8_t smm_relocation_start, smm_relocation_end;
841 extern uint8_t smm_code_start, smm_code_end;
842
843 #ifdef BX_USE_SMM
844 static void smm_init(PCIDevice *d)
845 {
846 uint32_t value;
847
848 /* check if SMM init is already done */
849 value = pci_config_readl(d, 0x58);
850 if ((value & (1 << 25)) == 0) {
851
852 /* enable the SMM memory window */
853 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
854
855 /* save original memory content */
856 memcpy((void *)0xa8000, (void *)0x38000, 0x8000);
857
858 /* copy the SMM relocation code */
859 memcpy((void *)0x38000, &smm_relocation_start,
860 &smm_relocation_end - &smm_relocation_start);
861
862 /* enable SMI generation when writing to the APMC register */
863 pci_config_writel(d, 0x58, value | (1 << 25));
864
865 /* init APM status port */
866 outb(0xb3, 0x01);
867
868 /* raise an SMI interrupt */
869 outb(0xb2, 0x00);
870
871 /* wait until SMM code executed */
872 while (inb(0xb3) != 0x00);
873
874 /* restore original memory content */
875 memcpy((void *)0x38000, (void *)0xa8000, 0x8000);
876
877 /* copy the SMM code */
878 memcpy((void *)0xa8000, &smm_code_start,
879 &smm_code_end - &smm_code_start);
880 wbinvd();
881
882 /* close the SMM memory window and enable normal SMM */
883 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
884 }
885 }
886 #endif
887
888 static void piix4_pm_enable(PCIDevice *d)
889 {
890 /* PIIX4 Power Management device (for ACPI) */
891 pci_config_writel(d, 0x40, PM_IO_BASE | 1);
892 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
893 pci_config_writel(d, 0x90, SMB_IO_BASE | 1);
894 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
895 #ifdef BX_USE_SMM
896 smm_init(d);
897 #endif
898 }
899
900 static void pci_bios_init_device(PCIDevice *d)
901 {
902 int class;
903 uint32_t *paddr;
904 int i, pin, pic_irq, vendor_id, device_id;
905
906 class = pci_config_readw(d, PCI_CLASS_DEVICE);
907 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
908 device_id = pci_config_readw(d, PCI_DEVICE_ID);
909 BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x class=0x%04x\n",
910 d->bus, d->devfn, vendor_id, device_id, class);
911 switch(class) {
912 case 0x0101: /* Mass storage controller - IDE interface */
913 if (vendor_id == PCI_VENDOR_ID_INTEL &&
914 (device_id == PCI_DEVICE_ID_INTEL_82371SB_1 ||
915 device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
916 /* PIIX3/PIIX4 IDE */
917 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
918 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
919 goto default_map;
920 } else {
921 /* IDE: we map it as in ISA mode */
922 pci_set_io_region_addr(d, 0, 0x1f0);
923 pci_set_io_region_addr(d, 1, 0x3f4);
924 pci_set_io_region_addr(d, 2, 0x170);
925 pci_set_io_region_addr(d, 3, 0x374);
926 }
927 break;
928 case 0x0800: /* Generic system peripheral - PIC */
929 if (vendor_id == PCI_VENDOR_ID_IBM) {
930 /* IBM */
931 if (device_id == 0x0046 || device_id == 0xFFFF) {
932 /* MPIC & MPIC2 */
933 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
934 }
935 }
936 break;
937 case 0xff00:
938 if (vendor_id == PCI_VENDOR_ID_APPLE &&
939 (device_id == 0x0017 || device_id == 0x0022)) {
940 /* macio bridge */
941 pci_set_io_region_addr(d, 0, 0x80800000);
942 }
943 break;
944 default:
945 default_map:
946 /* default memory mappings */
947 for(i = 0; i < PCI_NUM_REGIONS; i++) {
948 int ofs;
949 uint32_t val, size ;
950
951 if (i == PCI_ROM_SLOT)
952 ofs = 0x30;
953 else
954 ofs = 0x10 + i * 4;
955 pci_config_writel(d, ofs, 0xffffffff);
956 val = pci_config_readl(d, ofs);
957 if (val != 0) {
958 size = (~(val & ~0xf)) + 1;
959 if (val & PCI_ADDRESS_SPACE_IO)
960 paddr = &pci_bios_io_addr;
961 else if (size >= 0x04000000)
962 paddr = &pci_bios_bigmem_addr;
963 else
964 paddr = &pci_bios_mem_addr;
965 *paddr = (*paddr + size - 1) & ~(size - 1);
966 pci_set_io_region_addr(d, i, *paddr);
967 *paddr += size;
968 }
969 }
970 break;
971 }
972
973 /* map the interrupt */
974 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
975 if (pin != 0) {
976 pin = pci_slot_get_pirq(d, pin - 1);
977 pic_irq = pci_irqs[pin];
978 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
979 }
980
981 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
982 /* PIIX4 Power Management device (for ACPI) */
983 pm_io_base = PM_IO_BASE;
984 smb_io_base = SMB_IO_BASE;
985 // acpi sci is hardwired to 9
986 pci_config_writeb(d, PCI_INTERRUPT_LINE, 9);
987 pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
988 piix4_pm_enable(d);
989 acpi_enabled = 1;
990 }
991 }
992
993 void pci_for_each_device(void (*init_func)(PCIDevice *d))
994 {
995 PCIDevice d1, *d = &d1;
996 int bus, devfn;
997 uint16_t vendor_id, device_id;
998
999 for(bus = 0; bus < 1; bus++) {
1000 for(devfn = 0; devfn < 256; devfn++) {
1001 d->bus = bus;
1002 d->devfn = devfn;
1003 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1004 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1005 if (vendor_id != 0xffff || device_id != 0xffff) {
1006 init_func(d);
1007 }
1008 }
1009 }
1010 }
1011
1012 void pci_bios_init(void)
1013 {
1014 pci_bios_io_addr = 0xc000;
1015 pci_bios_mem_addr = 0xc0000000;
1016 pci_bios_bigmem_addr = ram_size;
1017 if (pci_bios_bigmem_addr < 0x90000000)
1018 pci_bios_bigmem_addr = 0x90000000;
1019
1020 pci_for_each_device(pci_bios_init_bridges);
1021
1022 pci_for_each_device(pci_bios_init_device);
1023 }
1024
1025 /****************************************************/
1026 /* Multi Processor table init */
1027
1028 static void putb(uint8_t **pp, int val)
1029 {
1030 uint8_t *q;
1031 q = *pp;
1032 *q++ = val;
1033 *pp = q;
1034 }
1035
1036 static void putstr(uint8_t **pp, const char *str)
1037 {
1038 uint8_t *q;
1039 q = *pp;
1040 while (*str)
1041 *q++ = *str++;
1042 *pp = q;
1043 }
1044
1045 static void putle16(uint8_t **pp, int val)
1046 {
1047 uint8_t *q;
1048 q = *pp;
1049 *q++ = val;
1050 *q++ = val >> 8;
1051 *pp = q;
1052 }
1053
1054 static void putle32(uint8_t **pp, int val)
1055 {
1056 uint8_t *q;
1057 q = *pp;
1058 *q++ = val;
1059 *q++ = val >> 8;
1060 *q++ = val >> 16;
1061 *q++ = val >> 24;
1062 *pp = q;
1063 }
1064
1065 static int mpf_checksum(const uint8_t *data, int len)
1066 {
1067 int sum, i;
1068 sum = 0;
1069 for(i = 0; i < len; i++)
1070 sum += data[i];
1071 return sum & 0xff;
1072 }
1073
1074 static unsigned long align(unsigned long addr, unsigned long v)
1075 {
1076 return (addr + v - 1) & ~(v - 1);
1077 }
1078
1079 static void mptable_init(void)
1080 {
1081 uint8_t *mp_config_table, *q, *float_pointer_struct;
1082 int ioapic_id, i, len;
1083 int mp_config_table_size;
1084
1085 #ifdef BX_USE_EBDA_TABLES
1086 mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
1087 #else
1088 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1089 mp_config_table = (uint8_t *)bios_table_cur_addr;
1090 #endif
1091 q = mp_config_table;
1092 putstr(&q, "PCMP"); /* "PCMP signature */
1093 putle16(&q, 0); /* table length (patched later) */
1094 putb(&q, 4); /* spec rev */
1095 putb(&q, 0); /* checksum (patched later) */
1096 #ifdef BX_QEMU
1097 putstr(&q, "QEMUCPU "); /* OEM id */
1098 #else
1099 putstr(&q, "BOCHSCPU");
1100 #endif
1101 putstr(&q, "0.1 "); /* vendor id */
1102 putle32(&q, 0); /* OEM table ptr */
1103 putle16(&q, 0); /* OEM table size */
1104 putle16(&q, smp_cpus + 18); /* entry count */
1105 putle32(&q, 0xfee00000); /* local APIC addr */
1106 putle16(&q, 0); /* ext table length */
1107 putb(&q, 0); /* ext table checksum */
1108 putb(&q, 0); /* reserved */
1109
1110 for(i = 0; i < smp_cpus; i++) {
1111 putb(&q, 0); /* entry type = processor */
1112 putb(&q, i); /* APIC id */
1113 putb(&q, 0x11); /* local APIC version number */
1114 if (i == 0)
1115 putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
1116 else
1117 putb(&q, 1); /* cpu flags: enabled */
1118 if (cpuid_signature) {
1119 putle32(&q, cpuid_signature);
1120 putle32(&q, cpuid_features);
1121 } else {
1122 putb(&q, 0); /* cpu signature */
1123 putb(&q, 6);
1124 putb(&q, 0);
1125 putb(&q, 0);
1126 putle16(&q, 0x201); /* feature flags */
1127 putle16(&q, 0);
1128 }
1129 putle16(&q, 0); /* reserved */
1130 putle16(&q, 0);
1131 putle16(&q, 0);
1132 putle16(&q, 0);
1133 }
1134
1135 /* isa bus */
1136 putb(&q, 1); /* entry type = bus */
1137 putb(&q, 0); /* bus ID */
1138 putstr(&q, "ISA ");
1139
1140 /* ioapic */
1141 ioapic_id = smp_cpus;
1142 putb(&q, 2); /* entry type = I/O APIC */
1143 putb(&q, ioapic_id); /* apic ID */
1144 putb(&q, 0x11); /* I/O APIC version number */
1145 putb(&q, 1); /* enable */
1146 putle32(&q, 0xfec00000); /* I/O APIC addr */
1147
1148 /* irqs */
1149 for(i = 0; i < 16; i++) {
1150 #ifdef BX_QEMU
1151 /* One entry per ioapic input. Input 2 is covered by
1152 irq0->inti2 override (i == 0). irq 2 is unused */
1153 if (i == 2)
1154 continue;
1155 #endif
1156 putb(&q, 3); /* entry type = I/O interrupt */
1157 putb(&q, 0); /* interrupt type = vectored interrupt */
1158 putb(&q, 0); /* flags: po=0, el=0 */
1159 putb(&q, 0);
1160 putb(&q, 0); /* source bus ID = ISA */
1161 putb(&q, i); /* source bus IRQ */
1162 putb(&q, ioapic_id); /* dest I/O APIC ID */
1163 #ifdef BX_QEMU
1164 putb(&q, i == 0 ? 2 : i); /* dest I/O APIC interrupt in */
1165 #else
1166 putb(&q, i); /* dest I/O APIC interrupt in */
1167 #endif
1168 }
1169 /* patch length */
1170 len = q - mp_config_table;
1171 mp_config_table[4] = len;
1172 mp_config_table[5] = len >> 8;
1173
1174 mp_config_table[7] = -mpf_checksum(mp_config_table, q - mp_config_table);
1175
1176 mp_config_table_size = q - mp_config_table;
1177
1178 #ifndef BX_USE_EBDA_TABLES
1179 bios_table_cur_addr += mp_config_table_size;
1180 #endif
1181
1182 /* floating pointer structure */
1183 #ifdef BX_USE_EBDA_TABLES
1184 ebda_cur_addr = align(ebda_cur_addr, 16);
1185 float_pointer_struct = (uint8_t *)ebda_cur_addr;
1186 #else
1187 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1188 float_pointer_struct = (uint8_t *)bios_table_cur_addr;
1189 #endif
1190 q = float_pointer_struct;
1191 putstr(&q, "_MP_");
1192 /* pointer to MP config table */
1193 putle32(&q, (unsigned long)mp_config_table);
1194
1195 putb(&q, 1); /* length in 16 byte units */
1196 putb(&q, 4); /* MP spec revision */
1197 putb(&q, 0); /* checksum (patched later) */
1198 putb(&q, 0); /* MP feature byte 1 */
1199
1200 putb(&q, 0);
1201 putb(&q, 0);
1202 putb(&q, 0);
1203 putb(&q, 0);
1204 float_pointer_struct[10] =
1205 -mpf_checksum(float_pointer_struct, q - float_pointer_struct);
1206 #ifdef BX_USE_EBDA_TABLES
1207 ebda_cur_addr += (q - float_pointer_struct);
1208 #else
1209 bios_table_cur_addr += (q - float_pointer_struct);
1210 #endif
1211 BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
1212 (unsigned long)float_pointer_struct,
1213 (unsigned long)mp_config_table,
1214 mp_config_table_size);
1215 }
1216
1217 /****************************************************/
1218 /* ACPI tables init */
1219
1220 /* Table structure from Linux kernel (the ACPI tables are under the
1221 BSD license) */
1222
1223 /*
1224 * All tables must be byte-packed to match the ACPI specification, since
1225 * the tables are provided by the system BIOS.
1226 */
1227
1228 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
1229 uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
1230 uint32_t length; /* Length of table, in bytes, including header */\
1231 uint8_t revision; /* ACPI Specification minor version # */\
1232 uint8_t checksum; /* To make sum of entire table == 0 */\
1233 uint8_t oem_id [6]; /* OEM identification */\
1234 uint8_t oem_table_id [8]; /* OEM table identification */\
1235 uint32_t oem_revision; /* OEM revision number */\
1236 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
1237 uint32_t asl_compiler_revision; /* ASL compiler revision number */
1238
1239
1240 struct acpi_table_header /* ACPI common table header */
1241 {
1242 ACPI_TABLE_HEADER_DEF
1243 } __attribute__((__packed__));
1244
1245 struct rsdp_descriptor /* Root System Descriptor Pointer */
1246 {
1247 uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */
1248 uint8_t checksum; /* To make sum of struct == 0 */
1249 uint8_t oem_id [6]; /* OEM identification */
1250 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
1251 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
1252 uint32_t length; /* XSDT Length in bytes including hdr */
1253 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
1254 uint8_t extended_checksum; /* Checksum of entire table */
1255 uint8_t reserved [3]; /* Reserved field must be 0 */
1256 } __attribute__((__packed__));
1257
1258 /*
1259 * ACPI 1.0 Root System Description Table (RSDT)
1260 */
1261 struct rsdt_descriptor_rev1
1262 {
1263 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1264 #ifdef BX_QEMU
1265 uint32_t table_offset_entry [4]; /* Array of pointers to other */
1266 #else
1267 uint32_t table_offset_entry [3]; /* Array of pointers to other */
1268 #endif
1269 /* ACPI tables */
1270 } __attribute__((__packed__));
1271
1272 /*
1273 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
1274 */
1275 struct facs_descriptor_rev1
1276 {
1277 uint8_t signature[4]; /* ACPI Signature */
1278 uint32_t length; /* Length of structure, in bytes */
1279 uint32_t hardware_signature; /* Hardware configuration signature */
1280 uint32_t firmware_waking_vector; /* ACPI OS waking vector */
1281 uint32_t global_lock; /* Global Lock */
1282 uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */
1283 uint32_t reserved1 : 31; /* Must be 0 */
1284 uint8_t resverved3 [40]; /* Reserved - must be zero */
1285 } __attribute__((__packed__));
1286
1287
1288 /*
1289 * ACPI 1.0 Fixed ACPI Description Table (FADT)
1290 */
1291 struct fadt_descriptor_rev1
1292 {
1293 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1294 uint32_t firmware_ctrl; /* Physical address of FACS */
1295 uint32_t dsdt; /* Physical address of DSDT */
1296 uint8_t model; /* System Interrupt Model */
1297 uint8_t reserved1; /* Reserved */
1298 uint16_t sci_int; /* System vector of SCI interrupt */
1299 uint32_t smi_cmd; /* Port address of SMI command port */
1300 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
1301 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
1302 uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
1303 uint8_t reserved2; /* Reserved - must be zero */
1304 uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
1305 uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
1306 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
1307 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
1308 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
1309 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
1310 uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
1311 uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
1312 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
1313 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
1314 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
1315 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
1316 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
1317 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
1318 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
1319 uint8_t reserved3; /* Reserved */
1320 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
1321 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
1322 uint16_t flush_size; /* Size of area read to flush caches */
1323 uint16_t flush_stride; /* Stride used in flushing caches */
1324 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
1325 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
1326 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
1327 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
1328 uint8_t century; /* Index to century in RTC CMOS RAM */
1329 uint8_t reserved4; /* Reserved */
1330 uint8_t reserved4a; /* Reserved */
1331 uint8_t reserved4b; /* Reserved */
1332 #if 0
1333 uint32_t wb_invd : 1; /* The wbinvd instruction works properly */
1334 uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
1335 uint32_t proc_c1 : 1; /* All processors support C1 state */
1336 uint32_t plvl2_up : 1; /* C2 state works on MP system */
1337 uint32_t pwr_button : 1; /* Power button is handled as a generic feature */
1338 uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
1339 uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
1340 uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
1341 uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
1342 uint32_t reserved5 : 23; /* Reserved - must be zero */
1343 #else
1344 uint32_t flags;
1345 #endif
1346 } __attribute__((__packed__));
1347
1348 /*
1349 * MADT values and structures
1350 */
1351
1352 /* Values for MADT PCATCompat */
1353
1354 #define DUAL_PIC 0
1355 #define MULTIPLE_APIC 1
1356
1357
1358 /* Master MADT */
1359
1360 struct multiple_apic_table
1361 {
1362 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1363 uint32_t local_apic_address; /* Physical address of local APIC */
1364 #if 0
1365 uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */
1366 uint32_t reserved1 : 31;
1367 #else
1368 uint32_t flags;
1369 #endif
1370 } __attribute__((__packed__));
1371
1372
1373 /* Values for Type in APIC_HEADER_DEF */
1374
1375 #define APIC_PROCESSOR 0
1376 #define APIC_IO 1
1377 #define APIC_XRUPT_OVERRIDE 2
1378 #define APIC_NMI 3
1379 #define APIC_LOCAL_NMI 4
1380 #define APIC_ADDRESS_OVERRIDE 5
1381 #define APIC_IO_SAPIC 6
1382 #define APIC_LOCAL_SAPIC 7
1383 #define APIC_XRUPT_SOURCE 8
1384 #define APIC_RESERVED 9 /* 9 and greater are reserved */
1385
1386 /*
1387 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
1388 */
1389 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
1390 uint8_t type; \
1391 uint8_t length;
1392
1393 /* Sub-structures for MADT */
1394
1395 struct madt_processor_apic
1396 {
1397 APIC_HEADER_DEF
1398 uint8_t processor_id; /* ACPI processor id */
1399 uint8_t local_apic_id; /* Processor's local APIC id */
1400 #if 0
1401 uint32_t processor_enabled: 1; /* Processor is usable if set */
1402 uint32_t reserved2 : 31; /* Reserved, must be zero */
1403 #else
1404 uint32_t flags;
1405 #endif
1406 } __attribute__((__packed__));
1407
1408 #ifdef BX_QEMU
1409 /*
1410 * * ACPI 2.0 Generic Address Space definition.
1411 * */
1412 struct acpi_20_generic_address {
1413 uint8_t address_space_id;
1414 uint8_t register_bit_width;
1415 uint8_t register_bit_offset;
1416 uint8_t reserved;
1417 uint64_t address;
1418 } __attribute__((__packed__));
1419
1420 /*
1421 * * HPET Description Table
1422 * */
1423 struct acpi_20_hpet {
1424 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1425 uint32_t timer_block_id;
1426 struct acpi_20_generic_address addr;
1427 uint8_t hpet_number;
1428 uint16_t min_tick;
1429 uint8_t page_protect;
1430 } __attribute__((__packed__));
1431 #define ACPI_HPET_ADDRESS 0xFED00000UL
1432 #endif
1433
1434 struct madt_io_apic
1435 {
1436 APIC_HEADER_DEF
1437 uint8_t io_apic_id; /* I/O APIC ID */
1438 uint8_t reserved; /* Reserved - must be zero */
1439 uint32_t address; /* APIC physical address */
1440 uint32_t interrupt; /* Global system interrupt where INTI
1441 * lines start */
1442 } __attribute__((__packed__));
1443
1444 #ifdef BX_QEMU
1445 struct madt_int_override
1446 {
1447 APIC_HEADER_DEF
1448 uint8_t bus; /* Identifies ISA Bus */
1449 uint8_t source; /* Bus-relative interrupt source */
1450 uint32_t gsi; /* GSI that source will signal */
1451 uint16_t flags; /* MPS INTI flags */
1452 } __attribute__((__packed__));
1453 #endif
1454
1455 #include "acpi-dsdt.hex"
1456
1457 static inline uint16_t cpu_to_le16(uint16_t x)
1458 {
1459 return x;
1460 }
1461
1462 static inline uint32_t cpu_to_le32(uint32_t x)
1463 {
1464 return x;
1465 }
1466
1467 static int acpi_checksum(const uint8_t *data, int len)
1468 {
1469 int sum, i;
1470 sum = 0;
1471 for(i = 0; i < len; i++)
1472 sum += data[i];
1473 return (-sum) & 0xff;
1474 }
1475
1476 static void acpi_build_table_header(struct acpi_table_header *h,
1477 char *sig, int len, uint8_t rev)
1478 {
1479 memcpy(h->signature, sig, 4);
1480 h->length = cpu_to_le32(len);
1481 h->revision = rev;
1482 #ifdef BX_QEMU
1483 memcpy(h->oem_id, "QEMU ", 6);
1484 memcpy(h->oem_table_id, "QEMU", 4);
1485 #else
1486 memcpy(h->oem_id, "BOCHS ", 6);
1487 memcpy(h->oem_table_id, "BXPC", 4);
1488 #endif
1489 memcpy(h->oem_table_id + 4, sig, 4);
1490 h->oem_revision = cpu_to_le32(1);
1491 #ifdef BX_QEMU
1492 memcpy(h->asl_compiler_id, "QEMU", 4);
1493 #else
1494 memcpy(h->asl_compiler_id, "BXPC", 4);
1495 #endif
1496 h->asl_compiler_revision = cpu_to_le32(1);
1497 h->checksum = acpi_checksum((void *)h, len);
1498 }
1499
1500 int acpi_build_processor_ssdt(uint8_t *ssdt)
1501 {
1502 uint8_t *ssdt_ptr = ssdt;
1503 int i, length;
1504 int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
1505
1506 ssdt_ptr[9] = 0; // checksum;
1507 ssdt_ptr += sizeof(struct acpi_table_header);
1508
1509 // caluculate the length of processor block and scope block excluding PkgLength
1510 length = 0x0d * acpi_cpus + 4;
1511
1512 // build processor scope header
1513 *(ssdt_ptr++) = 0x10; // ScopeOp
1514 if (length <= 0x3e) {
1515 *(ssdt_ptr++) = length + 1;
1516 } else {
1517 *(ssdt_ptr++) = 0x7F;
1518 *(ssdt_ptr++) = (length + 2) >> 6;
1519 }
1520 *(ssdt_ptr++) = '_'; // Name
1521 *(ssdt_ptr++) = 'P';
1522 *(ssdt_ptr++) = 'R';
1523 *(ssdt_ptr++) = '_';
1524
1525 // build object for each processor
1526 for(i=0;i<acpi_cpus;i++) {
1527 *(ssdt_ptr++) = 0x5B; // ProcessorOp
1528 *(ssdt_ptr++) = 0x83;
1529 *(ssdt_ptr++) = 0x0B; // Length
1530 *(ssdt_ptr++) = 'C'; // Name (CPUxx)
1531 *(ssdt_ptr++) = 'P';
1532 if ((i & 0xf0) != 0)
1533 *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
1534 else
1535 *(ssdt_ptr++) = 'U';
1536 *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
1537 *(ssdt_ptr++) = i;
1538 *(ssdt_ptr++) = 0x10; // Processor block address
1539 *(ssdt_ptr++) = 0xb0;
1540 *(ssdt_ptr++) = 0;
1541 *(ssdt_ptr++) = 0;
1542 *(ssdt_ptr++) = 6; // Processor block length
1543 }
1544
1545 acpi_build_table_header((struct acpi_table_header *)ssdt,
1546 "SSDT", ssdt_ptr - ssdt, 1);
1547
1548 return ssdt_ptr - ssdt;
1549 }
1550
1551 /* base_addr must be a multiple of 4KB */
1552 void acpi_bios_init(void)
1553 {
1554 struct rsdp_descriptor *rsdp;
1555 struct rsdt_descriptor_rev1 *rsdt;
1556 struct fadt_descriptor_rev1 *fadt;
1557 struct facs_descriptor_rev1 *facs;
1558 struct multiple_apic_table *madt;
1559 uint8_t *dsdt, *ssdt;
1560 #ifdef BX_QEMU
1561 struct acpi_20_hpet *hpet;
1562 uint32_t hpet_addr;
1563 #endif
1564 uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
1565 uint32_t acpi_tables_size, madt_addr, madt_size;
1566 int i;
1567
1568 /* reserve memory space for tables */
1569 #ifdef BX_USE_EBDA_TABLES
1570 ebda_cur_addr = align(ebda_cur_addr, 16);
1571 rsdp = (void *)(ebda_cur_addr);
1572 ebda_cur_addr += sizeof(*rsdp);
1573 #else
1574 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1575 rsdp = (void *)(bios_table_cur_addr);
1576 bios_table_cur_addr += sizeof(*rsdp);
1577 #endif
1578
1579 addr = base_addr = ram_size - ACPI_DATA_SIZE;
1580 rsdt_addr = addr;
1581 rsdt = (void *)(addr);
1582 addr += sizeof(*rsdt);
1583
1584 fadt_addr = addr;
1585 fadt = (void *)(addr);
1586 addr += sizeof(*fadt);
1587
1588 /* XXX: FACS should be in RAM */
1589 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
1590 facs_addr = addr;
1591 facs = (void *)(addr);
1592 addr += sizeof(*facs);
1593
1594 dsdt_addr = addr;
1595 dsdt = (void *)(addr);
1596 addr += sizeof(AmlCode);
1597
1598 ssdt_addr = addr;
1599 ssdt = (void *)(addr);
1600 addr += acpi_build_processor_ssdt(ssdt);
1601
1602 addr = (addr + 7) & ~7;
1603 madt_addr = addr;
1604 madt_size = sizeof(*madt) +
1605 sizeof(struct madt_processor_apic) * smp_cpus +
1606 #ifdef BX_QEMU
1607 sizeof(struct madt_io_apic) + sizeof(struct madt_int_override);
1608 #else
1609 sizeof(struct madt_io_apic);
1610 #endif
1611 madt = (void *)(addr);
1612 addr += madt_size;
1613
1614 #ifdef BX_QEMU
1615 addr = (addr + 7) & ~7;
1616 hpet_addr = addr;
1617 hpet = (void *)(addr);
1618 addr += sizeof(*hpet);
1619 #endif
1620
1621 acpi_tables_size = addr - base_addr;
1622
1623 BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
1624 (unsigned long)rsdp,
1625 (unsigned long)rsdt, acpi_tables_size);
1626
1627 /* RSDP */
1628 memset(rsdp, 0, sizeof(*rsdp));
1629 memcpy(rsdp->signature, "RSD PTR ", 8);
1630 #ifdef BX_QEMU
1631 memcpy(rsdp->oem_id, "QEMU ", 6);
1632 #else
1633 memcpy(rsdp->oem_id, "BOCHS ", 6);
1634 #endif
1635 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
1636 rsdp->checksum = acpi_checksum((void *)rsdp, 20);
1637
1638 /* RSDT */
1639 memset(rsdt, 0, sizeof(*rsdt));
1640 rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
1641 rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
1642 rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
1643 #ifdef BX_QEMU
1644 rsdt->table_offset_entry[3] = cpu_to_le32(hpet_addr);
1645 #endif
1646 acpi_build_table_header((struct acpi_table_header *)rsdt,
1647 "RSDT", sizeof(*rsdt), 1);
1648
1649 /* FADT */
1650 memset(fadt, 0, sizeof(*fadt));
1651 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
1652 fadt->dsdt = cpu_to_le32(dsdt_addr);
1653 fadt->model = 1;
1654 fadt->reserved1 = 0;
1655 fadt->sci_int = cpu_to_le16(pm_sci_int);
1656 fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
1657 fadt->acpi_enable = 0xf1;
1658 fadt->acpi_disable = 0xf0;
1659 fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
1660 fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
1661 fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
1662 fadt->pm1_evt_len = 4;
1663 fadt->pm1_cnt_len = 2;
1664 fadt->pm_tmr_len = 4;
1665 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
1666 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
1667 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
1668 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
1669 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
1670 sizeof(*fadt), 1);
1671
1672 /* FACS */
1673 memset(facs, 0, sizeof(*facs));
1674 memcpy(facs->signature, "FACS", 4);
1675 facs->length = cpu_to_le32(sizeof(*facs));
1676 BX_INFO("Firmware waking vector %p\n", &facs->firmware_waking_vector);
1677
1678 /* DSDT */
1679 memcpy(dsdt, AmlCode, sizeof(AmlCode));
1680
1681 /* MADT */
1682 {
1683 struct madt_processor_apic *apic;
1684 struct madt_io_apic *io_apic;
1685 #ifdef BX_QEMU
1686 struct madt_int_override *int_override;
1687 #endif
1688
1689 memset(madt, 0, madt_size);
1690 madt->local_apic_address = cpu_to_le32(0xfee00000);
1691 madt->flags = cpu_to_le32(1);
1692 apic = (void *)(madt + 1);
1693 for(i=0;i<smp_cpus;i++) {
1694 apic->type = APIC_PROCESSOR;
1695 apic->length = sizeof(*apic);
1696 apic->processor_id = i;
1697 apic->local_apic_id = i;
1698 apic->flags = cpu_to_le32(1);
1699 apic++;
1700 }
1701 io_apic = (void *)apic;
1702 io_apic->type = APIC_IO;
1703 io_apic->length = sizeof(*io_apic);
1704 io_apic->io_apic_id = smp_cpus;
1705 io_apic->address = cpu_to_le32(0xfec00000);
1706 io_apic->interrupt = cpu_to_le32(0);
1707 #ifdef BX_QEMU
1708 io_apic++;
1709
1710 int_override = (void *)io_apic;
1711 int_override->type = APIC_XRUPT_OVERRIDE;
1712 int_override->length = sizeof(*int_override);
1713 int_override->bus = cpu_to_le32(0);
1714 int_override->source = cpu_to_le32(0);
1715 int_override->gsi = cpu_to_le32(2);
1716 int_override->flags = cpu_to_le32(0);
1717 #endif
1718
1719 acpi_build_table_header((struct acpi_table_header *)madt,
1720 "APIC", madt_size, 1);
1721 }
1722
1723 #ifdef BX_QEMU
1724 /* HPET */
1725 memset(hpet, 0, sizeof(*hpet));
1726 /* Note timer_block_id value must be kept in sync with value advertised by
1727 * emulated hpet
1728 */
1729 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1730 hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
1731 acpi_build_table_header((struct acpi_table_header *)hpet,
1732 "HPET", sizeof(*hpet), 1);
1733 #endif
1734
1735 }
1736
1737 /* SMBIOS entry point -- must be written to a 16-bit aligned address
1738 between 0xf0000 and 0xfffff.
1739 */
1740 struct smbios_entry_point {
1741 char anchor_string[4];
1742 uint8_t checksum;
1743 uint8_t length;
1744 uint8_t smbios_major_version;
1745 uint8_t smbios_minor_version;
1746 uint16_t max_structure_size;
1747 uint8_t entry_point_revision;
1748 uint8_t formatted_area[5];
1749 char intermediate_anchor_string[5];
1750 uint8_t intermediate_checksum;
1751 uint16_t structure_table_length;
1752 uint32_t structure_table_address;
1753 uint16_t number_of_structures;
1754 uint8_t smbios_bcd_revision;
1755 } __attribute__((__packed__));
1756
1757 /* This goes at the beginning of every SMBIOS structure. */
1758 struct smbios_structure_header {
1759 uint8_t type;
1760 uint8_t length;
1761 uint16_t handle;
1762 } __attribute__((__packed__));
1763
1764 /* SMBIOS type 0 - BIOS Information */
1765 struct smbios_type_0 {
1766 struct smbios_structure_header header;
1767 uint8_t vendor_str;
1768 uint8_t bios_version_str;
1769 uint16_t bios_starting_address_segment;
1770 uint8_t bios_release_date_str;
1771 uint8_t bios_rom_size;
1772 uint8_t bios_characteristics[8];
1773 uint8_t bios_characteristics_extension_bytes[2];
1774 uint8_t system_bios_major_release;
1775 uint8_t system_bios_minor_release;
1776 uint8_t embedded_controller_major_release;
1777 uint8_t embedded_controller_minor_release;
1778 } __attribute__((__packed__));
1779
1780 /* SMBIOS type 1 - System Information */
1781 struct smbios_type_1 {
1782 struct smbios_structure_header header;
1783 uint8_t manufacturer_str;
1784 uint8_t product_name_str;
1785 uint8_t version_str;
1786 uint8_t serial_number_str;
1787 uint8_t uuid[16];
1788 uint8_t wake_up_type;
1789 uint8_t sku_number_str;
1790 uint8_t family_str;
1791 } __attribute__((__packed__));
1792
1793 /* SMBIOS type 3 - System Enclosure (v2.3) */
1794 struct smbios_type_3 {
1795 struct smbios_structure_header header;
1796 uint8_t manufacturer_str;
1797 uint8_t type;
1798 uint8_t version_str;
1799 uint8_t serial_number_str;
1800 uint8_t asset_tag_number_str;
1801 uint8_t boot_up_state;
1802 uint8_t power_supply_state;
1803 uint8_t thermal_state;
1804 uint8_t security_status;
1805 uint32_t oem_defined;
1806 uint8_t height;
1807 uint8_t number_of_power_cords;
1808 uint8_t contained_element_count;
1809 // contained elements follow
1810 } __attribute__((__packed__));
1811
1812 /* SMBIOS type 4 - Processor Information (v2.0) */
1813 struct smbios_type_4 {
1814 struct smbios_structure_header header;
1815 uint8_t socket_designation_str;
1816 uint8_t processor_type;
1817 uint8_t processor_family;
1818 uint8_t processor_manufacturer_str;
1819 uint32_t processor_id[2];
1820 uint8_t processor_version_str;
1821 uint8_t voltage;
1822 uint16_t external_clock;
1823 uint16_t max_speed;
1824 uint16_t current_speed;
1825 uint8_t status;
1826 uint8_t processor_upgrade;
1827 uint16_t l1_cache_handle;
1828 uint16_t l2_cache_handle;
1829 uint16_t l3_cache_handle;
1830 } __attribute__((__packed__));
1831
1832 /* SMBIOS type 16 - Physical Memory Array
1833 * Associated with one type 17 (Memory Device).
1834 */
1835 struct smbios_type_16 {
1836 struct smbios_structure_header header;
1837 uint8_t location;
1838 uint8_t use;
1839 uint8_t error_correction;
1840 uint32_t maximum_capacity;
1841 uint16_t memory_error_information_handle;
1842 uint16_t number_of_memory_devices;
1843 } __attribute__((__packed__));
1844
1845 /* SMBIOS type 17 - Memory Device
1846 * Associated with one type 19
1847 */
1848 struct smbios_type_17 {
1849 struct smbios_structure_header header;
1850 uint16_t physical_memory_array_handle;
1851 uint16_t memory_error_information_handle;
1852 uint16_t total_width;
1853 uint16_t data_width;
1854 uint16_t size;
1855 uint8_t form_factor;
1856 uint8_t device_set;
1857 uint8_t device_locator_str;
1858 uint8_t bank_locator_str;
1859 uint8_t memory_type;
1860 uint16_t type_detail;
1861 } __attribute__((__packed__));
1862
1863 /* SMBIOS type 19 - Memory Array Mapped Address */
1864 struct smbios_type_19 {
1865 struct smbios_structure_header header;
1866 uint32_t starting_address;
1867 uint32_t ending_address;
1868 uint16_t memory_array_handle;
1869 uint8_t partition_width;
1870 } __attribute__((__packed__));
1871
1872 /* SMBIOS type 20 - Memory Device Mapped Address */
1873 struct smbios_type_20 {
1874 struct smbios_structure_header header;
1875 uint32_t starting_address;
1876 uint32_t ending_address;
1877 uint16_t memory_device_handle;
1878 uint16_t memory_array_mapped_address_handle;
1879 uint8_t partition_row_position;
1880 uint8_t interleave_position;
1881 uint8_t interleaved_data_depth;
1882 } __attribute__((__packed__));
1883
1884 /* SMBIOS type 32 - System Boot Information */
1885 struct smbios_type_32 {
1886 struct smbios_structure_header header;
1887 uint8_t reserved[6];
1888 uint8_t boot_status;
1889 } __attribute__((__packed__));
1890
1891 /* SMBIOS type 127 -- End-of-table */
1892 struct smbios_type_127 {
1893 struct smbios_structure_header header;
1894 } __attribute__((__packed__));
1895
1896 static void
1897 smbios_entry_point_init(void *start,
1898 uint16_t max_structure_size,
1899 uint16_t structure_table_length,
1900 uint32_t structure_table_address,
1901 uint16_t number_of_structures)
1902 {
1903 uint8_t sum;
1904 int i;
1905 struct smbios_entry_point *ep = (struct smbios_entry_point *)start;
1906
1907 memcpy(ep->anchor_string, "_SM_", 4);
1908 ep->length = 0x1f;
1909 ep->smbios_major_version = 2;
1910 ep->smbios_minor_version = 4;
1911 ep->max_structure_size = max_structure_size;
1912 ep->entry_point_revision = 0;
1913 memset(ep->formatted_area, 0, 5);
1914 memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
1915
1916 ep->structure_table_length = structure_table_length;
1917 ep->structure_table_address = structure_table_address;
1918 ep->number_of_structures = number_of_structures;
1919 ep->smbios_bcd_revision = 0x24;
1920
1921 ep->checksum = 0;
1922 ep->intermediate_checksum = 0;
1923
1924 sum = 0;
1925 for (i = 0; i < 0x10; i++)
1926 sum += ((int8_t *)start)[i];
1927 ep->checksum = -sum;
1928
1929 sum = 0;
1930 for (i = 0x10; i < ep->length; i++)
1931 sum += ((int8_t *)start)[i];
1932 ep->intermediate_checksum = -sum;
1933 }
1934
1935 /* Type 0 -- BIOS Information */
1936 #define RELEASE_DATE_STR "01/01/2007"
1937 static void *
1938 smbios_type_0_init(void *start)
1939 {
1940 struct smbios_type_0 *p = (struct smbios_type_0 *)start;
1941
1942 p->header.type = 0;
1943 p->header.length = sizeof(struct smbios_type_0);
1944 p->header.handle = 0;
1945
1946 p->vendor_str = 1;
1947 p->bios_version_str = 1;
1948 p->bios_starting_address_segment = 0xe800;
1949 p->bios_release_date_str = 2;
1950 p->bios_rom_size = 0; /* FIXME */
1951
1952 memset(p->bios_characteristics, 0, 8);
1953 p->bios_characteristics[0] = 0x08; /* BIOS characteristics not supported */
1954 p->bios_characteristics_extension_bytes[0] = 0;
1955 p->bios_characteristics_extension_bytes[1] = 0;
1956
1957 p->system_bios_major_release = 1;
1958 p->system_bios_minor_release = 0;
1959 p->embedded_controller_major_release = 0xff;
1960 p->embedded_controller_minor_release = 0xff;
1961
1962 start += sizeof(struct smbios_type_0);
1963 memcpy((char *)start, BX_APPNAME, sizeof(BX_APPNAME));
1964 start += sizeof(BX_APPNAME);
1965 memcpy((char *)start, RELEASE_DATE_STR, sizeof(RELEASE_DATE_STR));
1966 start += sizeof(RELEASE_DATE_STR);
1967 *((uint8_t *)start) = 0;
1968
1969 return start+1;
1970 }
1971
1972 /* Type 1 -- System Information */
1973 static void *
1974 smbios_type_1_init(void *start)
1975 {
1976 struct smbios_type_1 *p = (struct smbios_type_1 *)start;
1977 p->header.type = 1;
1978 p->header.length = sizeof(struct smbios_type_1);
1979 p->header.handle = 0x100;
1980
1981 p->manufacturer_str = 0;
1982 p->product_name_str = 0;
1983 p->version_str = 0;
1984 p->serial_number_str = 0;
1985
1986 memcpy(p->uuid, bios_uuid, 16);
1987
1988 p->wake_up_type = 0x06; /* power switch */
1989 p->sku_number_str = 0;
1990 p->family_str = 0;
1991
1992 start += sizeof(struct smbios_type_1);
1993 *((uint16_t *)start) = 0;
1994
1995 return start+2;
1996 }
1997
1998 /* Type 3 -- System Enclosure */
1999 static void *
2000 smbios_type_3_init(void *start)
2001 {
2002 struct smbios_type_3 *p = (struct smbios_type_3 *)start;
2003
2004 p->header.type = 3;
2005 p->header.length = sizeof(struct smbios_type_3);
2006 p->header.handle = 0x300;
2007
2008 p->manufacturer_str = 0;
2009 p->type = 0x01; /* other */
2010 p->version_str = 0;
2011 p->serial_number_str = 0;
2012 p->asset_tag_number_str = 0;
2013 p->boot_up_state = 0x03; /* safe */
2014 p->power_supply_state = 0x03; /* safe */
2015 p->thermal_state = 0x03; /* safe */
2016 p->security_status = 0x02; /* unknown */
2017 p->oem_defined = 0;
2018 p->height = 0;
2019 p->number_of_power_cords = 0;
2020 p->contained_element_count = 0;
2021
2022 start += sizeof(struct smbios_type_3);
2023 *((uint16_t *)start) = 0;
2024
2025 return start+2;
2026 }
2027
2028 /* Type 4 -- Processor Information */
2029 static void *
2030 smbios_type_4_init(void *start, unsigned int cpu_number)
2031 {
2032 struct smbios_type_4 *p = (struct smbios_type_4 *)start;
2033
2034 p->header.type = 4;
2035 p->header.length = sizeof(struct smbios_type_4);
2036 p->header.handle = 0x400 + cpu_number;
2037
2038 p->socket_designation_str = 1;
2039 p->processor_type = 0x03; /* CPU */
2040 p->processor_family = 0x01; /* other */
2041 p->processor_manufacturer_str = 0;
2042
2043 p->processor_id[0] = cpuid_signature;
2044 p->processor_id[1] = cpuid_features;
2045
2046 p->processor_version_str = 0;
2047 p->voltage = 0;
2048 p->external_clock = 0;
2049
2050 p->max_speed = 0; /* unknown */
2051 p->current_speed = 0; /* unknown */
2052
2053 p->status = 0x41; /* socket populated, CPU enabled */
2054 p->processor_upgrade = 0x01; /* other */
2055
2056 p->l1_cache_handle = 0xffff; /* cache information structure not provided */
2057 p->l2_cache_handle = 0xffff;
2058 p->l3_cache_handle = 0xffff;
2059
2060 start += sizeof(struct smbios_type_4);
2061
2062 memcpy((char *)start, "CPU " "\0" "" "\0" "", 7);
2063 ((char *)start)[4] = cpu_number + '0';
2064
2065 return start+7;
2066 }
2067
2068 /* Type 16 -- Physical Memory Array */
2069 static void *
2070 smbios_type_16_init(void *start, uint32_t memsize, int nr_mem_devs)
2071 {
2072 struct smbios_type_16 *p = (struct smbios_type_16*)start;
2073
2074 p->header.type = 16;
2075 p->header.length = sizeof(struct smbios_type_16);
2076 p->header.handle = 0x1000;
2077
2078 p->location = 0x01; /* other */
2079 p->use = 0x03; /* system memory */
2080 p->error_correction = 0x01; /* other */
2081 p->maximum_capacity = memsize * 1024;
2082 p->memory_error_information_handle = 0xfffe; /* none provided */
2083 p->number_of_memory_devices = nr_mem_devs;
2084
2085 start += sizeof(struct smbios_type_16);
2086 *((uint16_t *)start) = 0;
2087
2088 return start + 2;
2089 }
2090
2091 /* Type 17 -- Memory Device */
2092 static void *
2093 smbios_type_17_init(void *start, uint32_t memory_size_mb, int instance)
2094 {
2095 struct smbios_type_17 *p = (struct smbios_type_17 *)start;
2096
2097 p->header.type = 17;
2098 p->header.length = sizeof(struct smbios_type_17);
2099 p->header.handle = 0x1100 + instance;
2100
2101 p->physical_memory_array_handle = 0x1000;
2102 p->total_width = 64;
2103 p->data_width = 64;
2104 /* TODO: should assert in case something is wrong ASSERT((memory_size_mb & ~0x7fff) == 0); */
2105 p->size = memory_size_mb;
2106 p->form_factor = 0x09; /* DIMM */
2107 p->device_set = 0;
2108 p->device_locator_str = 1;
2109 p->bank_locator_str = 0;
2110 p->memory_type = 0x07; /* RAM */
2111 p->type_detail = 0;
2112
2113 start += sizeof(struct smbios_type_17);
2114 snprintf(start, 8, "DIMM %d", instance);
2115 start += strlen(start) + 1;
2116 *((uint8_t *)start) = 0;
2117
2118 return start+1;
2119 }
2120
2121 /* Type 19 -- Memory Array Mapped Address */
2122 static void *
2123 smbios_type_19_init(void *start, uint32_t memory_size_mb, int instance)
2124 {
2125 struct smbios_type_19 *p = (struct smbios_type_19 *)start;
2126
2127 p->header.type = 19;
2128 p->header.length = sizeof(struct smbios_type_19);
2129 p->header.handle = 0x1300 + instance;
2130
2131 p->starting_address = instance << 24;
2132 p->ending_address = p->starting_address + (memory_size_mb << 10) - 1;
2133 p->memory_array_handle = 0x1000;
2134 p->partition_width = 1;
2135
2136 start += sizeof(struct smbios_type_19);
2137 *((uint16_t *)start) = 0;
2138
2139 return start + 2;
2140 }
2141
2142 /* Type 20 -- Memory Device Mapped Address */
2143 static void *
2144 smbios_type_20_init(void *start, uint32_t memory_size_mb, int instance)
2145 {
2146 struct smbios_type_20 *p = (struct smbios_type_20 *)start;
2147
2148 p->header.type = 20;
2149 p->header.length = sizeof(struct smbios_type_20);
2150 p->header.handle = 0x1400 + instance;
2151
2152 p->starting_address = instance << 24;
2153 p->ending_address = p->starting_address + (memory_size_mb << 10) - 1;
2154 p->memory_device_handle = 0x1100 + instance;
2155 p->memory_array_mapped_address_handle = 0x1300 + instance;
2156 p->partition_row_position = 1;
2157 p->interleave_position = 0;
2158 p->interleaved_data_depth = 0;
2159
2160 start += sizeof(struct smbios_type_20);
2161
2162 *((uint16_t *)start) = 0;
2163 return start+2;
2164 }
2165
2166 /* Type 32 -- System Boot Information */
2167 static void *
2168 smbios_type_32_init(void *start)
2169 {
2170 struct smbios_type_32 *p = (struct smbios_type_32 *)start;
2171
2172 p->header.type = 32;
2173 p->header.length = sizeof(struct smbios_type_32);
2174 p->header.handle = 0x2000;
2175 memset(p->reserved, 0, 6);
2176 p->boot_status = 0; /* no errors detected */
2177
2178 start += sizeof(struct smbios_type_32);
2179 *((uint16_t *)start) = 0;
2180
2181 return start+2;
2182 }
2183
2184 /* Type 127 -- End of Table */
2185 static void *
2186 smbios_type_127_init(void *start)
2187 {
2188 struct smbios_type_127 *p = (struct smbios_type_127 *)start;
2189
2190 p->header.type = 127;
2191 p->header.length = sizeof(struct smbios_type_127);
2192 p->header.handle = 0x7f00;
2193
2194 start += sizeof(struct smbios_type_127);
2195 *((uint16_t *)start) = 0;
2196
2197 return start + 2;
2198 }
2199
2200 void smbios_init(void)
2201 {
2202 unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
2203 char *start, *p, *q;
2204 int memsize = (ram_end == ram_size) ? ram_size / (1024 * 1024) :
2205 (ram_end - (1ull << 32) + ram_size) / (1024 * 1024);
2206 int i, nr_mem_devs;
2207
2208 #ifdef BX_USE_EBDA_TABLES
2209 ebda_cur_addr = align(ebda_cur_addr, 16);
2210 start = (void *)(ebda_cur_addr);
2211 #else
2212 bios_table_cur_addr = align(bios_table_cur_addr, 16);
2213 start = (void *)(bios_table_cur_addr);
2214 #endif
2215
2216 p = (char *)start + sizeof(struct smbios_entry_point);
2217
2218 #define add_struct(fn) do { \
2219 q = (fn); \
2220 nr_structs++; \
2221 if ((q - p) > max_struct_size) \
2222 max_struct_size = q - p; \
2223 p = q; \
2224 } while (0)
2225
2226 add_struct(smbios_type_0_init(p));
2227 add_struct(smbios_type_1_init(p));
2228 add_struct(smbios_type_3_init(p));
2229 for (cpu_num = 1; cpu_num <= smp_cpus; cpu_num++)
2230 add_struct(smbios_type_4_init(p, cpu_num));
2231
2232 /* Each 'memory device' covers up to 16GB of address space. */
2233 nr_mem_devs = (memsize + 0x3fff) >> 14;
2234 add_struct(smbios_type_16_init(p, memsize, nr_mem_devs));
2235 for ( i = 0; i < nr_mem_devs; i++ )
2236 {
2237 uint32_t dev_memsize = ((i == (nr_mem_devs - 1))
2238 ? (((memsize - 1) & 0x3fff) + 1) : 0x4000);
2239 add_struct(smbios_type_17_init(p, dev_memsize, i));
2240 add_struct(smbios_type_19_init(p, dev_memsize, i));
2241 add_struct(smbios_type_20_init(p, dev_memsize, i));
2242 }
2243
2244 add_struct(smbios_type_32_init(p));
2245 add_struct(smbios_type_127_init(p));
2246
2247 #undef add_struct
2248
2249 smbios_entry_point_init(
2250 start, max_struct_size,
2251 (p - (char *)start) - sizeof(struct smbios_entry_point),
2252 (uint32_t)(start + sizeof(struct smbios_entry_point)),
2253 nr_structs);
2254
2255 #ifdef BX_USE_EBDA_TABLES
2256 ebda_cur_addr += (p - (char *)start);
2257 #else
2258 bios_table_cur_addr += (p - (char *)start);
2259 #endif
2260
2261 BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
2262 }
2263
2264 static uint32_t find_resume_vector(void)
2265 {
2266 unsigned long addr, start, end;
2267
2268 #ifdef BX_USE_EBDA_TABLES
2269 start = align(ebda_cur_addr, 16);
2270 end = 0xa000 << 4;
2271 #else
2272 if (bios_table_cur_addr == 0)
2273 return 0;
2274 start = align(bios_table_cur_addr, 16);
2275 end = bios_table_end_addr;
2276 #endif
2277
2278 for (addr = start; addr < end; addr += 16) {
2279 if (!memcmp((void*)addr, "RSD PTR ", 8)) {
2280 struct rsdp_descriptor *rsdp = (void*)addr;
2281 struct rsdt_descriptor_rev1 *rsdt = (void*)rsdp->rsdt_physical_address;
2282 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[0];
2283 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
2284 return facs->firmware_waking_vector;
2285 }
2286 }
2287
2288 return 0;
2289 }
2290
2291 static void find_440fx(PCIDevice *d)
2292 {
2293 uint16_t vendor_id, device_id;
2294
2295 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2296 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2297
2298 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441)
2299 i440_pcidev = *d;
2300 }
2301
2302 static void reinit_piix4_pm(PCIDevice *d)
2303 {
2304 uint16_t vendor_id, device_id;
2305
2306 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2307 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2308
2309 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3)
2310 piix4_pm_enable(d);
2311 }
2312
2313 void rombios32_init(uint32_t *s3_resume_vector, uint8_t *shutdown_flag)
2314 {
2315 BX_INFO("Starting rombios32\n");
2316 BX_INFO("Shutdown flag %x\n", *shutdown_flag);
2317
2318 #ifdef BX_QEMU
2319 qemu_cfg_port = qemu_cfg_port_probe();
2320 #endif
2321
2322 ram_probe();
2323
2324 cpu_probe();
2325
2326 setup_mtrr();
2327
2328 smp_probe();
2329
2330 find_bios_table_area();
2331
2332 if (*shutdown_flag == 0xfe) {
2333 /* redirect bios read access to RAM */
2334 pci_for_each_device(find_440fx);
2335 bios_lock_shadow_ram(); /* bios is already copied */
2336 *s3_resume_vector = find_resume_vector();
2337 if (!*s3_resume_vector) {
2338 BX_INFO("This is S3 resume but wakeup vector is NULL\n");
2339 } else {
2340 BX_INFO("S3 resume vector %p\n", *s3_resume_vector);
2341 pci_for_each_device(reinit_piix4_pm);
2342 }
2343 return;
2344 }
2345
2346 pci_bios_init();
2347
2348 if (bios_table_cur_addr != 0) {
2349
2350 mptable_init();
2351
2352 uuid_probe();
2353
2354 smbios_init();
2355
2356 if (acpi_enabled)
2357 acpi_bios_init();
2358
2359 bios_lock_shadow_ram();
2360
2361 BX_INFO("bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
2362 if (bios_table_cur_addr > bios_table_end_addr)
2363 BX_PANIC("bios_table_end_addr overflow!\n");
2364 #ifdef BX_USE_EBDA_TABLES
2365 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
2366 if (ebda_cur_addr > 0xA0000)
2367 BX_PANIC("ebda_cur_addr overflow!\n");
2368 #endif
2369 }
2370 }
GPL Bios