lib/fpe-trapping.h

   1 /* Trapping floating-point exceptions.
   2    Copyright (C) 2023-2024 Free Software Foundation, Inc.
   3
   4    This program is free software: you can redistribute it and/or modify
   5    it under the terms of the GNU General Public License as published by
   6    the Free Software Foundation, either version 3 of the License, or
   7    (at your option) any later version.
   8
   9    This program is distributed in the hope that it will be useful,
  10    but WITHOUT ANY WARRANTY; without even the implied warranty of
  11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12    GNU General Public License for more details.
  13
  14    You should have received a copy of the GNU General Public License
  15    along with this program.  If not, see <https://www.gnu.org/licenses/>.  */
  16
  17 /* HAVE_FPE_TRAPPING
  18    Defined to 1 when sigfpe_on_invalid is available.  */
  19
  20 /* sigfpe_on_invalid
  21    Enables a SIGFPE signal when an FE_INVALID exception occurs.
  22    A SIGFPE signal by default terminates the program.
  23    Returns >= 0 when successful, -1 upon failure.  */
  24
  25
  26 #include <fenv.h>
  27
  28 static int
  29 sigfpe_on_invalid ()
  30 {
  31   /* Clear FE_INVALID exceptions from past operations.  */
  32   feclearexcept (FE_INVALID);
  33
  34   /* An FE_INVALID exception shall trigger a SIGFPE signal.
  35      This call may fail on arm, arm64, riscv64 CPUs.
  36      Also, possibly a bug in glibc/sysdeps/m68k/fpu/feenablxcpt.c: it sets
  37      only bit 13, but should better set bits 15, 14, 13 of the control
  38      register together.  See
  39      <https://sourceware.org/bugzilla/show_bug.cgi?id=30993>.  */
  40   int ret = feenableexcept (FE_INVALID);
  41   if (ret == -1)
  42     return -1;
  43
  44   return 0;
  45 }
  46
  47 /* But it does not work on RISC-V.  That's because the fcsr register has only
  48    bits for floating-point exception status, but no bits for trapping
  49    floating-point exceptions.  */
  50 /* And it does not work on arm with software floating-point emulation.  */
  51 #if !(defined __riscv || (defined __GLIBC__ && defined __arm__ && defined __SOFTFP__))
  52 # define HAVE_FPE_TRAPPING 1
  53 #endif