sysdeps/aarch64/cpu-features.h

   1 /* Initialize CPU feature data.  AArch64 version.
   2    This file is part of the GNU C Library.
   3    Copyright (C) 2017-2024 Free Software Foundation, Inc.
   4    Copyright The GNU Toolchain Authors.
   5
   6    The GNU C Library is free software; you can redistribute it and/or
   7    modify it under the terms of the GNU Lesser General Public
   8    License as published by the Free Software Foundation; either
   9    version 2.1 of the License, or (at your option) any later version.
  10
  11    The GNU C Library is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    Lesser General Public License for more details.
  15
  16    You should have received a copy of the GNU Lesser General Public
  17    License along with the GNU C Library; if not, see
  18    <https://www.gnu.org/licenses/>.  */
  19
  20 #ifndef _CPU_FEATURES_AARCH64_H
  21 #define _CPU_FEATURES_AARCH64_H
  22
  23 #include <stdint.h>
  24 #include <stdbool.h>
  25
  26 #define MIDR_PARTNUM_SHIFT      4
  27 #define MIDR_PARTNUM_MASK       (0xfff << MIDR_PARTNUM_SHIFT)
  28 #define MIDR_PARTNUM(midr)      \
  29         (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
  30 #define MIDR_ARCHITECTURE_SHIFT 16
  31 #define MIDR_ARCHITECTURE_MASK  (0xf << MIDR_ARCHITECTURE_SHIFT)
  32 #define MIDR_ARCHITECTURE(midr) \
  33         (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
  34 #define MIDR_VARIANT_SHIFT      20
  35 #define MIDR_VARIANT_MASK       (0xf << MIDR_VARIANT_SHIFT)
  36 #define MIDR_VARIANT(midr)      \
  37         (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
  38 #define MIDR_IMPLEMENTOR_SHIFT  24
  39 #define MIDR_IMPLEMENTOR_MASK   (0xff << MIDR_IMPLEMENTOR_SHIFT)
  40 #define MIDR_IMPLEMENTOR(midr)  \
  41         (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
  42
  43 #define IS_THUNDERX(midr) (MIDR_IMPLEMENTOR(midr) == 'C'        \
  44                            && MIDR_PARTNUM(midr) == 0x0a1)
  45
  46 #define IS_THUNDERX2PA(midr) (MIDR_IMPLEMENTOR(midr) == 'B'     \
  47                            && MIDR_PARTNUM(midr) == 0x516)
  48 #define IS_THUNDERX2(midr) (MIDR_IMPLEMENTOR(midr) == 'C'       \
  49                            && MIDR_PARTNUM(midr) == 0xaf)
  50
  51 #define IS_EMAG(midr) (MIDR_IMPLEMENTOR(midr) == 'P'                          \
  52                        && MIDR_PARTNUM(midr) == 0x000)
  53
  54 #define IS_KUNPENG920(midr) (MIDR_IMPLEMENTOR(midr) == 'H'                         \
  55                         && MIDR_PARTNUM(midr) == 0xd01)
  56
  57 #define IS_A64FX(midr) (MIDR_IMPLEMENTOR(midr) == 'F'                         \
  58                         && MIDR_PARTNUM(midr) == 0x001)
  59
  60 #define IS_ORYON1(midr) (MIDR_IMPLEMENTOR(midr) == 'Q'                  \
  61                          && (MIDR_PARTNUM(midr) == 0x001                \
  62                              || (MIDR_PARTNUM(midr) == 0x002            \
  63                                  && MIDR_VARIANT(midr) == 0)))
  64
  65 struct cpu_features
  66 {
  67   uint64_t midr_el1;
  68   unsigned zva_size;
  69   bool bti;
  70   /* Currently, the GLIBC memory tagging tunable only defines 8 bits.  */
  71   uint8_t mte_state;
  72   bool sve;
  73   bool prefer_sve_ifuncs;
  74   bool mops;
  75 };
  76
  77 #endif /* _CPU_FEATURES_AARCH64_H  */