1 // -----------------------------------------------------------------------
3 // Copyright 2004 Tommy Thorn - All Rights Reserved
5 // This program is free software; you can redistribute it and/or modify
6 // it under the terms of the GNU General Public License as published by
7 // the Free Software Foundation, Inc., 53 Temple Place Ste 330,
8 // Bostom MA 02111-1307, USA; either version 2 of the License, or
9 // (at your option) any later version; incorporated herein by reference.
11 // -----------------------------------------------------------------------
15 module rs232in(// Control
20 input wire serial_rxd
,
21 output reg attention
= 0,
22 output reg [7:0] data
= 0);
24 //parameter bps = 9_600;
25 parameter bps
= 115_200;
26 parameter frequency
= 25_000_000;
27 parameter period
= frequency
/ bps
- 1;
29 reg [16:0] ttyclk
= 0;
30 reg [7:0] shift_in
= 0;
37 * The theory: look for a negedge, then wait 1.5 bit period to skip
38 * start bit and center in first bit. Keep shifting bits until a full
42 * data ~\__ B0 B1 B2 B3 B4 B5 B6 B7 ~~
43 * count 8 7 6 5 4 3 2 1
45 always @(posedge clk25MHz
)
56 // Get rid of meta stability.
57 {rxd2
,rxd
} <= {rxd
,serial_rxd
};
59 if (~ttyclk
[16]) begin
61 end else if (count
) begin
63 data
<= {rxd2
, shift_in
[7:1]};
68 shift_in
<= {rxd2
, shift_in
[7:1]}; // Shift in from the left
70 end else if (~rxd2
) begin
71 // Just saw the negedge of the start bit
72 ttyclk
<= (3 * period
) / 2 - 2;