rtl/rs232in.v

   1 // -----------------------------------------------------------------------
   2 //
   3 //   Copyright 2004 Tommy Thorn - All Rights Reserved
   4 //
   5 //   This program is free software; you can redistribute it and/or modify
   6 //   it under the terms of the GNU General Public License as published by
   7 //   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
   8 //   Bostom MA 02111-1307, USA; either version 2 of the License, or
   9 //   (at your option) any later version; incorporated herein by reference.
  10 //
  11 // -----------------------------------------------------------------------
  12
  13 `timescale 1ns/10ps
  14
  15 module rs232in(// Control
  16                 input  wire        clk25MHz,
  17                 input  wire        reset,
  18
  19                 // Serial line
  20                 input  wire        serial_rxd,
  21                 output reg         attention = 0,
  22                 output reg   [7:0] data      = 0);
  23
  24    //parameter         bps        =    9_600;
  25    parameter           bps        =    115_200;
  26    parameter           frequency  = 25_000_000;
  27    parameter           period     = frequency / bps - 1;
  28
  29    reg [16:0] ttyclk     = 0;
  30    reg [7:0]  shift_in   = 0;
  31    reg [4:0]  count      = 0;
  32
  33    reg        rxd         = 0;
  34    reg        rxd2        = 0;
  35
  36    /*
  37     * The theory: look for a negedge, then wait 1.5 bit period to skip
  38     * start bit and center in first bit.  Keep shifting bits until a full
  39     * byte is collected.
  40     *
  41     *        Start                        Stop
  42     * data   ~\__ B0 B1 B2 B3 B4 B5 B6 B7 ~~
  43     * count        8  7  6  5  4  3  2  1
  44     */
  45    always @(posedge clk25MHz)
  46      if (reset) begin
  47         shift_in   <= 0;
  48         ttyclk     <= 0;
  49         count      <= 0;
  50         attention  <= 0;
  51         rxd2       <= ~0;
  52         rxd        <= ~0;
  53      end else begin
  54         attention <= 0;
  55
  56         // Get rid of meta stability.
  57         {rxd2,rxd} <= {rxd,serial_rxd};
  58
  59         if (~ttyclk[16]) begin
  60            ttyclk <= ttyclk - 1;
  61         end else if (count) begin
  62            if (count == 1) begin
  63               data        <= {rxd2, shift_in[7:1]};
  64               attention   <= 1;
  65            end
  66
  67            count       <= count - 1;
  68            shift_in    <= {rxd2, shift_in[7:1]}; // Shift in from the left
  69            ttyclk      <= period - 2;
  70         end else if (~rxd2) begin
  71            // Just saw the negedge of the start bit
  72            ttyclk      <= (3 * period) / 2 - 2;
  73            count       <= 8;
  74         end
  75      end
  76 endmodule